CN108962772B - 封装结构及其形成方法 - Google Patents

封装结构及其形成方法 Download PDF

Info

Publication number
CN108962772B
CN108962772B CN201810796545.6A CN201810796545A CN108962772B CN 108962772 B CN108962772 B CN 108962772B CN 201810796545 A CN201810796545 A CN 201810796545A CN 108962772 B CN108962772 B CN 108962772B
Authority
CN
China
Prior art keywords
layer
chip
improvement
opening
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810796545.6A
Other languages
English (en)
Other versions
CN108962772A (zh
Inventor
石磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN201810796545.6A priority Critical patent/CN108962772B/zh
Publication of CN108962772A publication Critical patent/CN108962772A/zh
Priority to US16/393,139 priority patent/US11139267B2/en
Application granted granted Critical
Publication of CN108962772B publication Critical patent/CN108962772B/zh
Priority to US17/458,907 priority patent/US11791310B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0239Material of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/024Material of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/067Polyphenylene
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0695Polyamide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/07Polyamine or polyimide
    • H01L2924/07025Polyimide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种封装结构及其形成方法,其中封装结构的形成方法包括:提供基板,所述基板表面具有粘合层;在所述粘合层表面形成改善层,所述改善层内具有开口,所述开口底部暴露出粘合层表面;提供若干芯片,所述芯片包括功能面;贴装芯片,使所述功能面与开口底部的粘合层贴合。所述方法形成的封装结构较好。

Description

封装结构及其形成方法
技术领域
本发明涉及封装领域,尤其涉及一种芯片的封装结构及其形成方法。
背景技术
随着集成电路制造业的快速发展,人们对集成电路的封装技术的要求也不断提高,现有的封装技术包括球栅阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和系统封装(SiP)。其中,圆片级封装(WLP)由于其出色的优点逐渐被大部分的半导体制造者所采用,它的全部或者大部分工艺步骤是在已完成前工序的硅圆片上完成的,最后将圆片直接切割成分离的独立器件。圆片级封装具有如下独特优势:封装加工效率高,可以多个圆片同时加工;具有倒装芯片封装的优点,即:轻、薄、短、小;与前工序相比,只是增加了引脚重新布线(RDL)和凸点制作两个工序,其余全部是传统工艺;减少了传统封装中的多次测试。因此,世界上各大型IC封装公司纷纷投入圆片级封装的研究、开发和生产。
然而,现有圆片级封装技术仍存在较多的问题,使得封装结构的性能仍较差。
发明内容
本发明解决的技术问题是提供一种封装结构及其形成方法,以提高封装结构的性能。
为解决上述技术问题,本发明提供一种封装结构的形成方法,包括:提供基板,所述基板表面具有粘合层;在所述粘合层表面形成改善层,所述改善层内具有开口,所述开口底部暴露出粘合层表面;提供芯片,所述芯片包括功能面;贴装芯片,使所述功能面与开口底部的粘合层贴合。
可选的,所述芯片表面高于改善层表面。
可选的,所述粘合层包括:紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
可选的,所述改善层和开口的形成方法包括:在所述粘合层表面形成改善膜;对所述改善膜进行曝光显影,形成所述改善层,所述改善层内具有开口。
可选的,所述改善膜的材料包括光刻胶。
可选的,贴装所述芯片之后,还包括:在所述改善层表面、以及芯片的侧壁和表面形成塑封层;形成所述塑封层之后,去除所述基板和粘合层,暴露出芯片的功能面;去除所述基板和粘合层之后,在所述功能面上形成布线层和位于布线层表面的钝化层,所述钝化层内具有暴露出布线层表面的焊料开口;在所述焊料开口内形成焊球;形成所述焊球之后,进行切割处理,形成芯片结构。
可选的,所述芯片结构不包括改善层;或者,所述芯片结构包括部分改善层。
相应的,本发明还提供一种封装结构,包括:基板,所述基板表面具有粘合层;位于所述粘合层表面的改善层,所述改善层内具有开口,所述开口底部暴露出粘合层表面;位于所述开口内的芯片,所述芯片包括功能面,所述功能面与粘合层贴合。
可选的,所述芯片表面高于改善层表面。
可选的,所述粘合层包括:紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
可选的,所述改善层的材料包括光刻胶。
与现有技术相比,本发明的技术方案具有以下有益效果:
本发明技术方案提供的封装结构的形成方法中,改善层内具有开口,所述开口用于后续容纳芯片,且所述开口侧壁的改善层能够防止芯片发生偏移,因此,有利于提高封装结构的性能。
附图说明
图1是一种封装结构的结构示意图;
图2至图11是本发明一实施例的封装结构的形成方法的各步骤的结构示意图;
图12至图14是本发明另一实施例的封装结构的形成方法的各步骤的结构示意图。
具体实施方式
正如背景技术所述,封装结构的性能较差。
图1是一种封装结构的结构示意图。
请参考图1,提供基底100,所述基底100表面具有粘合层101;提供芯片102,所述芯片102包括功能面1,所述功能面1的芯片102内具有焊盘102a;贴装所述芯片102,使所述功能面1与粘合层101贴合。
上述封装结构中,所述芯片102的材料包括硅,硅的热膨胀系数较小,而所述粘合层101的材料的热膨胀系数较芯片102大的多,则在后续高温工艺过程中,所述粘合层101和芯片102的热膨胀程度不同,使得芯片102和粘合层101之间易发生相对位移,使得封装结构的性能较差。
为解决所述技术问题,本发明提供了一种封装结构的形成方法,通过在所述粘合层顶部形成若干相互分离的改善层,相邻改善层之间具有开口,所述开口用于限定芯片的位置,因此,有利于防止芯片发生偏移,提高封装结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图2至图11是本发明一实施例的封装结构的形成方法的各步骤的结构示意图。
请参考图2,提基板200,所述基板200表面具有粘合层201。
所述基板200的材料包括:玻璃、陶瓷、金属或者聚合物。
所述基板200的形状包括圆形、矩形或者三角形。
所述粘合层201用于将后续芯片粘附与基板200表面。
在本实施例中,所述粘合层201为紫外粘合胶,所述紫外粘合胶在未经过紫外照射时粘性很高,而经过紫外光照射后材料内的交联化学键被打断导致粘性大幅下降或消失,有利于后续剥离粘合层201和基板200。
在其他实施例中,所述粘合层包括:丙烯酸压敏胶或者环氧树脂压敏胶。
所述粘合层201的形成工艺包括:旋涂工艺、喷涂工艺、滚压工艺、印刷工艺、非旋转涂覆工艺、热压工艺、真空压合工艺或者压力压合工艺。
所述粘合层201的材料具有第一热膨胀系数,所述第一热膨胀系数较高。
请参考图3,在所述粘合层201表面形成改善膜202。
所述改善膜202的材料包括:光刻胶,所述改善膜202的形成工艺包括:印刷工艺或者旋涂工艺。
所述改善膜202用于后续形成改善层。
所述改善膜202具有第二热膨胀系数,所述第二热膨胀系数也较高,且所述第二热膨胀系数与第一热膨胀系数之间的差值落在预设范围内,具体的,预设范围为:-50~50,使得在后续高温工艺过程中,所述改善层和粘合层201之间不易发生相对位移,而后续改善层内的开口用于限制芯片发生位移,因此,有利于减少封装结构发生偏移或者翘曲。
请参考图4,对所述改善膜202(见图3)进行曝光显影,形成改善层220,所述改善层220内具有开口203。
所述改善层220是由改善膜202形成,而第二热膨胀系数与第一热膨胀系数之间的差值落在预设范围内,则在后续高温工艺过程中,所述改善层220和粘合层201之间不易发生相对位移。
并且,所述开口203用于限定后续芯片的位置,则芯片与改善层220之间的相对位置不变。综上,所述芯片、改善层220和粘合层201之间均不易发生相对位移,有利于减少封装结构发生偏移或者翘曲。
所述开口203的深度为:10微米~50微米,选择所述开口203的深度的意义在于:若所述开口203的深度小于10微米,即:所述开口203的深度过浅,则所述开口203的改善层220对后续芯片的限制能力较弱,使得芯片在后续工艺过程中仍易发生偏移;若所述开口203的深度大于50微米,使得形成开口203的工艺难度较大。
请参考图5,提供芯片204,所述芯片204包括功能面11,所述功能面11内具有焊盘204a;贴装芯片204,使所述功能面11与开口203(见图5)底部的粘合层201贴合。
所述芯片204的材料包括硅,所述芯片204的热膨胀系数为2.2~2.4。所述焊盘204a用于将芯片204内的电信号输出。
所述芯片204的厚度为:20微米~100微米。
所述芯片204通过粘合层201贴装与基板200上。
在本实施例中,所述芯片204的表面高于改善层220的表面,则部分所述芯片204位于开口203内。所述开口203侧壁的改善层220用于限制芯片204的位置,防止芯片204与改善层220和粘合层201之间发生相对位移,有利于减少封装结构发生偏移或者翘曲。
请参考图6,在所述改善层220表面、以及芯片204的侧壁和表面形成塑封层205。
在本实施例中,所述塑封层205的材料为环氧树脂,所述环氧树脂的密封性能好,塑型容易,是形成塑封层205较佳的材料。
在其他实施例中,所述塑封层的材料为塑封材料,所述塑封材料包括聚酰亚胺树脂、苯并环丁烯树脂、聚苯并恶唑树脂、聚对苯二甲酸丁二酯、聚碳酸酯、聚对苯二甲酸乙二醇酯、聚乙烯、聚丙烯、聚烯烃、聚氨酯、聚烯烃、聚醚砜、聚酰胺、聚亚氨酯、乙烯-醋酸乙烯共聚物、聚乙烯醇。
在本实施例中,所述塑封层205的形成工艺为注塑工艺(injection molding)。在其他实施例中,所述塑封层的形成工艺包括:转塑工艺(transfer molding)或丝网印刷工艺。
采用注塑工艺形成塑封层205的方法包括:提供模具;在所述模具中填充塑封材料,使所述塑封材料包覆所述芯片204;对所述塑封材料进行升温固化,形成塑封层205。
所述塑封层205既能够保护芯片204又可作为后续工艺的承载体。
在形成所述塑封层205的过程中,尽管所述芯片204材料的热膨胀系数与改善层220和粘合层201的热膨胀系数之间的差值较大,但是,部分所述芯片204位于开口203内,所述开口203在升温固化的过程中用于限制芯片204与改善层220和粘合层201发生相对位移。
并且,改善层220与粘合层201的热膨胀系数之间的差值落在预设范围之内,则在所述升温固化过程中,所述改善层220和粘合层201之间不易发生相对位移。综上、芯片204、改善层220和粘合层201之间不易发生相对位移,有利于减少封装结构发生偏移或者翘曲。
在本实施例中,形成所述塑封层205之后,不对塑封层205进行减薄处理。
在其他实施例中,形成所述塑封层之后,对塑封层进行减薄处理,直至暴露出芯片的表面。
请参考图7,形成所述塑封层205之后,去除所述基板200(见图6)和粘合层201(见图6),暴露出芯片204的功能面11。
在本实施例中,所述粘合层201的材料为紫外粘合胶,去除所述基板200(见图6)和粘合层201(见图6)的方法包括:利用紫外光照射照射,使粘合层201的粘性降低,从而使得粘合层201和基板200剥离。
去除所述基板200(见图6)和粘合层201(见图6),暴露出芯片204的功能面11,有利于后续在所述功能面11上形成布线层和位于布线层表面的焊球。所述布线层与焊盘204a实现电连接
请参考图8,去除所述基板200和粘合层201之后,在所述焊盘204a表面形成布线层206。
所述布线层206的材料为金属,如:铝、铜、锡、镍、金或者银。
所述布线层206的形成工艺包括蒸镀工艺、溅射工艺、电镀工艺或者化学镀工艺。
所述布线层206底部与焊盘204a顶部电连接,所述布线层206顶部与后续焊球之间的电连接。
请参考图9,在所述改善层220表面和布线层206的侧壁形成钝化层207,所述钝化层207内具有暴露出布线层206表面的焊料开口208。
所述钝化层207的材料包括:聚酰亚胺、聚对苯撑苯并双恶唑或光敏苯并环丁烯,所述钝化层207的形成工艺包括:旋涂工艺或者印刷工艺。
所述钝化层207暴露出部分布线层206,有利于后续的焊球与布线层206电连接。
所述焊料开口208用于后续容纳焊球。
请参考图10,在所述焊料开口208(见图9)内形成焊球209。
所述焊球209包括金锡焊球、银锡焊球或者铜锡焊球。
在本实施例中,所述焊球209为金锡焊球,所述金锡焊球的形成方法包括:在所述焊料开口208内形成金锡层;形成所述金锡层之后,进行高温回流工艺,使金锡层回流成球状,降温后形成金锡焊球。
请参考图11,形成所述焊球209之后,进行切割处理,形成芯片结构250。
在本实施例中,所述芯片结构250不包含改善层220,则后续无需去除所述改善层220的工艺,使得工艺步骤较少,有利于降低工艺的复杂度。
在本实施例中,形成所述芯片结构250之后,不对塑封层205进行减薄处理。
在其他实施例中,形成所述芯片结构之后,对塑封层进行减薄处理,直至暴露出芯片的表面。
图12至图14是本发明封装结构另一实施例封装结构的形成方法的各步骤的结构示意图。
请参考图12,进行切割处理,形成芯片结构300。
需要说明的是图12是在上述实施例图10基础上的后续步骤的结构示意图。
在本实施例中,所述芯片结构300包含部分改善层220。
请参考图13,形成所述芯片结构300之后,去除所述改善层220。
去除所述改善层220的工艺包括干法刻蚀工艺和湿法刻蚀工艺中的一种或者两种组合。
请参考图14,去除所述改善层220之后,对塑封层205进行减薄处理,直至暴露出芯片204表面。
在本实施例中,去除所述改善层220之后,对塑封层205进行减薄处理。
在其他实施例中,去除所述改善层之后,不对塑封层205进行减薄处理。
相应的,本发明还提供一种封装结构,请参考图5,包括:
基板200,所述基板200表面具有粘合层201;
位于所述粘合层201表面的改善层220,所述改善层220内具有开口203(见图4),所述开口203底部暴露出粘合层201表面;
位于所述开口203内的芯片204,所述芯片204包括功能面11,所述功能面11与粘合层201贴合。
所述芯片204表面高于改善层220的表面。
所述粘合层201包括:紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
所述改善层220的材料包括光刻胶。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (8)

1.一种封装结构的形成方法,其特征在于,包括:
提供基板,所述基板表面具有粘合层;
在所述粘合层表面形成改善层,所述改善层内具有开口,所述开口底部暴露出粘合层表面;
提供若干芯片,所述芯片具有功能面;
贴装芯片,使所述功能面与开口底部的粘合层贴合;
其中,所述改善层的热膨胀系数,与粘合层的热膨胀系数之间的差值落在预设范围之内,所述预设范围为:-50~50,使得在后续高温工艺过程中,所述改善层和粘合层之间不易发生相对位移;
所述改善层和开口的形成方法包括:在所述粘合层表面形成改善膜;对所述改善膜进行曝光显影,形成所述改善层,所述改善层内具有开口;所述改善膜的材料包括光刻胶。
2.如权利要求1所述的封装结构的形成方法,其特征在于,所述芯片表面高于改善层表面。
3.如权利要求1所述的封装结构的形成方法,其特征在于,所述粘合层包括:紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
4.如权利要求1所述的封装结构的形成方法,其特征在于,贴装所述芯片之后,还包括:在所述改善层表面、以及芯片的侧壁和表面形成塑封层;形成所述塑封层之后,去除所述基板和粘合层,暴露出芯片的功能面;去除所述基板和粘合层之后,在所述功能面上形成布线层和位于布线层表面的钝化层,所述钝化层内具有暴露出布线层表面的焊料开口;在所述焊料开口内形成焊球;形成所述焊球之后,进行切割处理,形成芯片结构。
5.如权利要求4所述的封装结构的形成方法,其特征在于,所述芯片结构不包括改善层;或者,所述芯片结构包括部分改善层。
6.一种封装结构,其特征在于,包括:
基板,所述基板表面具有粘合层;
位于所述粘合层表面的改善层,所述改善层内具有开口,所述开口底部暴露出粘合层表面;
位于所述开口内的芯片,所述芯片包括功能面,所述功能面与粘合层贴合;
其中,所述改善层的热膨胀系数,与粘合层的热膨胀系数之间的差值落在预设范围之内,所述预设范围为:-50~50,使得所述改善层和粘合层之间不易发生相对位移;所述改善层的材料包括光刻胶。
7.如权利要求6所述的封装结构,其特征在于,所述芯片表面高于改善层表面。
8.如权利要求6所述的封装结构,其特征在于,所述粘合层包括:紫外粘合胶、丙烯酸压敏胶或者环氧树脂压敏胶。
CN201810796545.6A 2018-07-19 2018-07-19 封装结构及其形成方法 Active CN108962772B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201810796545.6A CN108962772B (zh) 2018-07-19 2018-07-19 封装结构及其形成方法
US16/393,139 US11139267B2 (en) 2018-07-19 2019-04-24 Packaging structure and forming method thereof
US17/458,907 US11791310B2 (en) 2018-07-19 2021-08-27 Semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810796545.6A CN108962772B (zh) 2018-07-19 2018-07-19 封装结构及其形成方法

Publications (2)

Publication Number Publication Date
CN108962772A CN108962772A (zh) 2018-12-07
CN108962772B true CN108962772B (zh) 2021-01-22

Family

ID=64497850

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810796545.6A Active CN108962772B (zh) 2018-07-19 2018-07-19 封装结构及其形成方法

Country Status (2)

Country Link
US (2) US11139267B2 (zh)
CN (1) CN108962772B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037082B (zh) * 2018-07-19 2021-01-22 通富微电子股份有限公司 封装结构及其形成方法
CN114038814A (zh) * 2021-11-18 2022-02-11 苏州通富超威半导体有限公司 封装结构及封装结构的形成方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
JP2007035688A (ja) * 2005-07-22 2007-02-08 Fujitsu Ltd 半導体装置およびその製造方法
US20080099910A1 (en) * 2006-08-31 2008-05-01 Ati Technologies Inc. Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
US7781877B2 (en) * 2007-08-07 2010-08-24 Micron Technology, Inc. Packaged integrated circuit devices with through-body conductive vias, and methods of making same
US7968446B2 (en) * 2008-10-06 2011-06-28 Wan-Ling Yu Metallic bump structure without under bump metallurgy and manufacturing method thereof
WO2011014409A1 (en) * 2009-07-30 2011-02-03 Megica Corporation System-in packages
US9087701B2 (en) * 2011-04-30 2015-07-21 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP
US9881894B2 (en) * 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US9385102B2 (en) * 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
CN104241217A (zh) * 2014-06-25 2014-12-24 中国科学院微电子研究所 一种芯片背面裸露的扇出型封装结构及制造方法
CN104681456B (zh) * 2015-01-27 2017-07-14 华进半导体封装先导技术研发中心有限公司 一种扇出型晶圆级封装方法
CN104637967A (zh) * 2015-02-13 2015-05-20 苏州晶方半导体科技股份有限公司 封装方法及封装结构
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
CN105206539A (zh) * 2015-09-01 2015-12-30 华进半导体封装先导技术研发中心有限公司 扇出型封装制备方法
US10304700B2 (en) * 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US20170133334A1 (en) * 2015-11-09 2017-05-11 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10014260B2 (en) * 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
JP6834469B2 (ja) * 2016-12-27 2021-02-24 日亜化学工業株式会社 発光装置及びその製造方法
US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
US10586763B2 (en) * 2017-11-15 2020-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Also Published As

Publication number Publication date
US11791310B2 (en) 2023-10-17
US20200027857A1 (en) 2020-01-23
CN108962772A (zh) 2018-12-07
US20210391300A1 (en) 2021-12-16
US11139267B2 (en) 2021-10-05

Similar Documents

Publication Publication Date Title
TWI654726B (zh) 具有虛設連接器的半導體封裝及其形成方法
US10867897B2 (en) PoP device
CN210182379U (zh) 芯片封装结构
TWI446419B (zh) 堆疊裝置的製造方法及裝置晶圓處理方法
WO2017124671A1 (zh) 一种扇出型芯片的封装方法及封装结构
WO2017124670A1 (zh) 一种扇出型芯片的封装方法及封装结构
CN111883521B (zh) 多芯片3d封装结构及其制作方法
WO2017041519A1 (zh) 一种芯片封装方法
WO2017024847A1 (zh) 晶圆级芯片封装方法
US10163854B2 (en) Package structure and method for manufacturing thereof
US20210233890A1 (en) Packaging structures
US11855067B2 (en) Integrated circuit package and method
CN215069984U (zh) 双层堆叠的3d扇出型封装结构
US11791310B2 (en) Semiconductor packaging structure
CN108962766B (zh) 封装结构及其形成方法
WO2022161464A1 (zh) 晶圆级系统封装方法及晶圆级系统封装结构
US11735564B2 (en) Three-dimensional chip packaging structure and method thereof
WO2017024846A1 (zh) 晶圆级芯片封装方法
CN114446918A (zh) Mcm封装结构及其制作方法
CN112133695B (zh) 系统级封装结构及其制作方法
CN210516718U (zh) 一种封装结构
US12113045B2 (en) Three-dimensional stacked fan-out packaging structure and method making the same
US20220271009A1 (en) Double-layer packaged 3d fan-out packaging structure and method making the same
KR20230047783A (ko) 웨이퍼와 지지 캐리어 접착용 접착 부재 및 이를 이용한 반도체 소자의 제조 방법
CN115101426A (zh) 一种半导体封装结构及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant