WO2022161464A1 - 晶圆级系统封装方法及晶圆级系统封装结构 - Google Patents

晶圆级系统封装方法及晶圆级系统封装结构 Download PDF

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Publication number
WO2022161464A1
WO2022161464A1 PCT/CN2022/074632 CN2022074632W WO2022161464A1 WO 2022161464 A1 WO2022161464 A1 WO 2022161464A1 CN 2022074632 W CN2022074632 W CN 2022074632W WO 2022161464 A1 WO2022161464 A1 WO 2022161464A1
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Prior art keywords
chip
wafer
bonding
pad
pads
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PCT/CN2022/074632
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English (en)
French (fr)
Inventor
黄河
向阳辉
刘孟彬
Original Assignee
中芯集成电路（宁波）有限公司上海分公司
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Priority claimed from CN202110129147.0A external-priority patent/CN114823355A/zh
Priority claimed from CN202110129135.8A external-priority patent/CN114823354A/zh
Priority claimed from CN202110130759.1A external-priority patent/CN114823356A/zh
Priority claimed from CN202110133089.9A external-priority patent/CN114823357A/zh
Application filed by 中芯集成电路（宁波）有限公司上海分公司 filed Critical 中芯集成电路（宁波）有限公司上海分公司
Publication of WO2022161464A1 publication Critical patent/WO2022161464A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Definitions

  • Embodiments of the present invention relate to the technical field of semiconductor packaging, and in particular, to a wafer-level system packaging method and a wafer-level system packaging structure.
  • advanced packaging methods mainly adopt the three-dimensional stacking mode of wafer-level system packaging (wafer level package system in package, WLPSIP), compared with the traditional system package, the wafer level system package is to complete the packaging integration process on the wafer, which has the advantages of greatly reducing the area of the package structure, reducing the manufacturing cost, optimizing the electrical performance, batch Sub-manufacturing and other advantages can significantly reduce workload and equipment requirements.
  • wafer level package system in package WLPSIP
  • the problem solved by the embodiments of the present invention is to provide a wafer-level system packaging method and a wafer-level system packaging structure, which can improve packaging efficiency and packaging reliability and reduce packaging costs while implementing wafer-level packaging.
  • an embodiment of the present invention provides a wafer-level system packaging method, including: providing a first wafer in which a plurality of first chips are formed, the first chips including opposing first and second surfaces, the first surface of the first chip having exposed first pads; providing a cap or a plurality of second chips, the second chips or caps having exposed surfaces the second pad; the second chip or the cover is bonded to the first wafer by a bonding layer, the second pad and the first pad are opposite up and down, forming a first gap; relatively
  • the first bonding pad and the second bonding pad include a facing portion and a staggered portion; through an electroplating process, a first conductive pad for electrically connecting the first bonding pad and the second bonding pad is formed in the first gap bump.
  • an embodiment of the present invention further provides a wafer level system packaging structure, including: a first wafer including a plurality of first chips, the first chips including opposite first surfaces and second surfaces, so The first surface has exposed and spaced first bonding pads; a cover or a plurality of second chips has exposed second bonding pads on the surface of the cover or the second chips; The second chip or the cover is bonded to the first surface of the first wafer, the second pad and the first pad are opposite to each other, the first pad and the second pad are It includes a facing part and a staggered part; a first conductive bump formed by an electroplating process connects the second bonding pad and the first bonding pad.
  • the embodiments of the present invention form the first conductive bumps filled in the first voids through an electroplating process, so as to realize wafer-level packaging.
  • the packaging efficiency and packaging reliability are improved, and the packaging cost is reduced.
  • the first pad and the second pad have a facing part and a staggered part, and the staggered part can be more easily contacted with the electroplating solution, which can avoid that the electroplating solution is not easy to flow into the gap due to the small gap, resulting in the inability to form a relatively complete first.
  • the problem of one conductive bump can better realize the electroplating process, so that the formed first conductive bump can fill the gap as completely as possible, and the contact area between the formed conductive bump and the pad is prevented from being too small and the resistance increases.
  • 1 to 4 are schematic structural diagrams corresponding to each step in the first embodiment of the wafer level system packaging method of the present invention.
  • Embodiment 2 are schematic structural diagrams corresponding to each step in Embodiment 2 of the wafer-level system packaging method of the present invention.
  • FIG. 9 is a schematic structural diagram corresponding to each step in Embodiment 3 of the wafer-level system packaging method of the present invention.
  • FIG. 10 is a schematic structural diagram corresponding to each step in Embodiment 4 of the wafer-level system packaging method of the present invention.
  • 11 to 13 are schematic structural diagrams corresponding to each step in Embodiment 5 of the wafer level system packaging method of the present invention.
  • FIG. 14 to 16 are schematic structural diagrams corresponding to each step in Embodiment 6 of the wafer-level system packaging method of the present invention.
  • a first wafer 100 is provided in which a plurality of first chips 110 are formed, the first chips 110 include opposing first and second surfaces, and the first surface of the first chip 110 has The exposed first pad 130 .
  • the first wafer 100 is a to-be-packaged wafer after device fabrication.
  • the first wafer 100 is a device wafer (CMOS wafer)
  • the semiconductor substrate of the first wafer 100 is a silicon substrate.
  • the semiconductor substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium
  • the semiconductor substrate can also be a silicon-on-insulator substrate or a germanium substrate and other materials type of substrate.
  • the material of the semiconductor substrate may be a material suitable for process requirements or easy integration. According to actual process requirements, the thickness of the first wafer 100 is 10 micrometers to 100 micrometers.
  • the plurality of first chips 110 formed in the first wafer 100 may be of the same type or different types of chips.
  • the first wafer 100 may be fabricated by using an integrated circuit fabrication technology, for example, an N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor) is formed on the first semiconductor substrate through processes such as deposition and etching. , NMOS) devices and P-Metal-Oxide-Semiconductor (PMOS) devices and other devices, on the device, a dielectric layer, a metal interconnection structure, and a pad electrically connected to the metal interconnection junction are formed. Thus, at least one first chip 110 is integrated in the first wafer 100 .
  • N-Metal-Oxide-Semiconductor N-type metal-oxide-semiconductor
  • PMOS P-Metal-Oxide-Semiconductor
  • the first bonding pads 130 located on the surface of the first chip 110 are used to realize electrical connection between the first chip 110 and other semiconductor devices.
  • the first pad 130 may be a lead pad (Pad).
  • the setting of the first bonding pads 130 also needs to meet certain requirements, for example, the area of the exposed first bonding pads 130 is 5 square microns to 200 mm square microns.
  • the exposed area of the first pad 130 is set within the above range, during the subsequent electroplating process, the first pad 130 can be in sufficient contact with the electroplating solution to prevent the first pad 130 from being in contact with the electroplating solution.
  • Sufficient contact will affect the contact performance between the first conductive bump and the first pad 130 , for example, the contact area is too small to affect the contact resistance, or the inability to make contact results in poor electrical contact, and it can also ensure that the contact area is not too large to reduce Electroplating efficiency, while also not taking up too much area.
  • a first dielectric layer 160 exposing the first pads 130 is formed on the surface of the first wafer 100 .
  • the first dielectric layer 160 has a certain thickness, which can provide space for forming the first voids 11 in the bonding step; in addition, the first dielectric layer 160 has insulating properties and is also used to form the first conductive bumps in the first voids 11 After the block, the insulation of the first conductive bump and other components is achieved.
  • the first dielectric layer 160 is also used as a bonding layer for realizing the physical connection between the first wafer 100 and the chip to be integrated.
  • the first dielectric layer 160 is a first oxide layer, and the material of the first oxide layer is silicon oxide.
  • the first oxide layer may also be an oxide material such as hafnium oxide, aluminum oxide, or lanthanum oxide.
  • the first dielectric layer 160 may also be an organic material, and the organic material includes a photoresistable bonding material, and the photoresistable material includes a dry film or a Die Attach Film (DAF).
  • DAF Die Attach Film
  • a plurality of second chips 200 are provided, and the surfaces of the second chips 200 have exposed second pads 210 ; the second chips 200 are bonded to the first wafer 100 by using a bonding layer, and the second pads
  • the first bonding pad 130 and the first bonding pad 210 are opposed to each other up and down, and form the first gap 11 ; the opposite first bonding pad 130 and the second bonding pad 210 include a facing portion and a staggered portion.
  • the second chip 200 is used as a chip to be integrated in the wafer-level system packaging, and the wafer-level system packaging method in this embodiment is used to realize heterogeneous integration.
  • the plurality of second chips 200 may be chips made of silicon wafers or chips made of other materials.
  • the second chip 200 is manufactured using an integrated circuit manufacturing technology, and the plurality of second chips 200 are chips with the same function; or, the plurality of second chips 200 include at least two chips with different functions.
  • the second chip 200 includes a bare chip, a chip with a cover layer 250, a chip with a shielding layer on the top surface, and a chip with electrical terminals on the top surface, or the second chip 200 includes a logic chip, a memory chip, a central processing unit chip, a microchip At least one of a processor chip and an analog-to-digital conversion chip, or the second chip 200 includes at least one MEMS chip among a microphone, a pressure sensor, a gyroscope, a speed sensor, and an acceleration sensor, and senses radio frequency signals and infrared radiation signals.
  • a sensor chip with one of visible light signals, acoustic wave signals, and electromagnetic wave signals the chip has a cavity or no cavity
  • the second chip 200 includes a PN junction device with at least one of CMOS, CIS, diode, and triode
  • the second chip 200 includes passive devices including at least one of an inductor, a capacitor, an optical filter, an MLCC, and a connector.
  • the types of the plurality of second chips 200 may be the same or different.
  • the sensor chip can be a radio frequency module chip used in 5G equipment, but is not limited to a 5G radio frequency sensor module chip, and can also be other types of radio frequency module chips.
  • the module chip that receives the infrared radiation signal may be an infrared sensor module chip that utilizes the infrared radiation signal, such as a thermal imager, a forehead temperature gun, and other types of temperature measurement or imaging.
  • the sensor module chip can also be a camera module chip, such as a module chip including a photosensitive chip and a filter, which can receive visible light for imaging.
  • the sensor module chip can also be a microphone module chip, which can receive sound waves to transmit sound signals.
  • the sensor module chips in the present invention are not limited to the types listed here, and can be various types of sensor module chips that can achieve certain functions in the art.
  • the MEMS chip includes at least one of a microphone, a pressure sensor, a gyroscope, a speed sensor, an acceleration sensor, and a thermopile sensor.
  • the filter chip includes at least one of a surface acoustic wave resonator and a bulk acoustic wave resonator.
  • MLCC chips include: NP0, C0G, Y5V, Z5U, X7R, X5R and other capacitors.
  • the second bonding pads 210 located on the surface of the second chip 200 are lead pads (Pad), which are used to realize electrical connection between the second chip 200 and other semiconductor devices.
  • the second pad 210 may be a lead pad (Pad).
  • the second bonding pad 210 may be a bonding pad, but is not limited to bonding pads, and may also be other conductive blocks with an electrical connection function.
  • the material of the second pad 210 is a conductive material.
  • the material of the second pad 210 includes any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.
  • the area of the exposed second bonding pads 210 is 5 to 200 square micrometers.
  • a second dielectric layer 260 exposing the second pads 210 is formed on the second chip 200 .
  • the function and material of the second dielectric layer 260 are the same as those of the first dielectric layer 160 .
  • the surface of the second chip 200 having the second bonding pads 210 is the front surface, and the surface opposite to the front surface is the back surface.
  • the step of providing a plurality of second chips 200 includes: providing a second wafer 600 , and the backsides of the plurality of second chips 200 are temporarily bonded to the second wafer 600 .
  • a plurality of second chips 200 are formed on the second wafer 600, the second wafer 600 is used as a carrier wafer for temporarily fixing the plurality of second chips 200, and the second wafer 600 is also used for the second wafer 600 on the second wafer 600.
  • the process of bonding the chip 200 to the first wafer 100 it plays a supporting role for the second chip 200 , thereby improving the reliability of the bonding.
  • an adhesive layer 610 is formed on the second wafer 600 , and the plurality of second chips 200 are temporarily bonded to the second wafer 600 through the adhesive layer 610 .
  • the adhesive layer 610 includes one or both of an adhesive film (Die Attach Film, DAF) and a dry film (Dry Film).
  • the dry film is a viscous photoresist film used for semiconductor chip packaging or printing the first wafer 100.
  • the dry film is produced by coating a solvent-free photoresist on polyester
  • the film base is covered with a polyethylene film; when in use, the polyethylene film is peeled off, and the solvent-free photoresist is pressed on the base plate. After exposure and development, the pattern can be formed in the dry film.
  • the illustrated adhesive layer 610 may also be a UV film or foam glue.
  • the UV film is viscous and debonded by UV light irradiation, and the foam is debonded by heating.
  • the second chip 200 may be temporarily bonded to the second wafer 600 by electrostatic bonding. Electrostatic bonding technology is a method to achieve bonding without any adhesive.
  • the second chip 200 and the second wafer 600 to be bonded are connected to different electrodes respectively, and under the action of voltage, charges are formed on the surfaces of the second chip 200 and the second wafer 600, and the second chip 200
  • the electric charge on the surface of the second wafer 600 is different from that of the second wafer 600 , so that a greater electrostatic attraction is generated during the bonding process of the second chip 200 and the second wafer 600 , so as to realize the physical connection between the two.
  • the second wafer 600 may not be provided, and the second chips 200 may be directly bonded to the first chips 110 in sequence.
  • the first dielectric layer 160 and the second dielectric layer 260 may not be formed, and the second chip 200 and the first chip 110 may be bonded through a dry film.
  • the second dielectric layer 260 is disposed opposite to the first dielectric layer 160, so that the second chip 200 is bonded to the first wafer 100, and the position of the second chip 200 corresponds to the position of the first chip 110, on the first bonding pad 130 A first gap 11 is formed between the second bonding pad 210 and the second bonding pad 210 .
  • the meaning that the positions of the second chip 200 and the first chip 110 correspond to each other means that when the second chip 200 and the first chip 110 are bonded, they are aligned with each other, and the second pads 210 on the second chip 200 are aligned with each other.
  • the first pads 130 of the first chip 110 are also disposed opposite and aligned with each other.
  • both the second dielectric layer 260 and the first dielectric layer 160 have a certain thickness, when the second dielectric layer 260 and the first dielectric layer 160 are disposed opposite to each other and are attached to each other, due to the supporting function of the two dielectric layers, the A first void 11 is formed between the first pad 130 exposed from the dielectric layer 160 and the second pad 210 exposed from the second dielectric layer 260 .
  • the first pad 130 is located at the end of the first chip 110 ; the second pad 210 is located at the end of the second chip 200 ; the second dielectric layer 260 is located at the end of the second pad 210 .
  • the position is not in contact with the first dielectric layer 160 , so that the first void 11 forms an opening between the second pad 210 and the first dielectric layer 160 .
  • the step of bonding the second chip 200 to the first wafer 100 includes: disposing the second wafer 600 opposite to the first wafer 100 so that the front surface of the second chip 200 on the second wafer 600 is bonded are combined with the first wafer 100 .
  • the second wafer 600 can provide greater support strength for the second chip 200 , thereby improving the relationship between the first chip 110 and the second chip 200 . bonding reliability.
  • the bonding between the second chip 200 and the first wafer 100 is achieved by a fusion bonding process of the first oxide layer and the second oxide layer.
  • the second chip 200 and the first wafer 100 are physically connected by means of silicon oxide-silicon oxide fusion bonding.
  • Fusion bonding is a process that mainly uses interfacial chemical force to complete the bonding.
  • the surface activity of the first oxide layer and the second oxide layer is improved, so that the first oxide layer and the second oxide layer are Covalent bonds are formed between the contact surfaces of the layers and the bonding is realized in the form of covalent bonds, and the bonding strength between the first oxide layer and the second oxide layer is relatively high, thereby improving the packaging of wafer-level system packaging. Yield.
  • the second chip 200 and the first wafer 100 may also be bonded in other manners, such as adhesive bonding or glass dielectric bonding.
  • the height of the first gap 11 is 5 ⁇ m to 200 ⁇ m.
  • it is not only conducive to making the electroplating solution easily enter the first gap 11 for the electroplating process, but also conducive to avoiding the first gap 11
  • the height is too large, which leads to the problem that the plating time is too long, so as to take into account the plating efficiency and the plating yield.
  • the first bonding pad 130 and the second bonding pad 210 may be designed to include a facing portion and a staggered portion.
  • the first bonding pad 130 and the second bonding pad 210 include facing parts to ensure that the first conductive bumps 31 formed subsequently have good contact with the first bonding pad 130 and the second bonding pad 210, and further It is ensured that through the first conductive bumps 31 , a good electrical connection can be achieved between the first bonding pad 130 and the second bonding pad 210 .
  • the first pad 130 and the second pad 210 also include staggered parts, and the staggered parts are more likely to be in contact with the electroplating solution, which is beneficial to make the electroplating solution easier to flow into the first gap 11 when the first gap 11 is small.
  • a gap 11 it is beneficial to form relatively intact first conductive bumps 31 .
  • the first bonding pad 130 and the second bonding pad 210 are facing each other, and the two may also be staggered.
  • the area of the facing portion of the first pad 130 and the second pad 210 is larger than half of the area of the first pad 130 or the second pad 210 , which can better realize the electroplating process.
  • first conductive bumps 31 fill in the first voids 11 as completely as possible, so as to ensure sufficient contact area between the first conductive bumps 31 and the first pads 130 and the second pads 210 , which is correspondingly beneficial to achieve lower contact resistance.
  • the second wafer 600 is debonded to separate the second wafer 600 from the second chip 200 ; the first pad 130 is formed in the first void 11 through an electroplating process.
  • the first conductive bumps 31 electrically connected to the second pads 210 .
  • the second wafer 600 is attached to the second chip 200 through the adhesive layer 610 . Accordingly, in the process of debonding, the second wafer 600 can be separated from the second wafer 600 by a chemical method or a mechanical peeling method. The two chips 200 are separated. In other embodiments, the second wafer 600 may be separated from the second chip 200 in other manners.
  • the adhesive layer 610 is a UV film
  • debonding is performed by irradiation of UV light
  • the adhesive layer 610 is a foam rubber
  • the debonding is performed by heating.
  • the first conductive bumps 31 are filled in the first voids 11 and are in contact with both the first pads 130 and the second pads 210 , so that the electrical connection between the first pads 130 and the second pads 210 can be achieved, and further The electrical connection between the first chip 110 and the second chip 200 is realized.
  • the first conductive bumps 31 may be formed through an electroplating process.
  • the first conductive bumps 31 formed by the electroplating method can achieve a good filling effect in the first voids 11 , thereby improving the reliability of the electrical connection between the first pads 130 and the second pads 210 .
  • the electroplating process is electroless plating.
  • the bonded second chip 200 and the first wafer 100 are placed in a solution containing metal ions (eg: electroless silver plating, nickel plating, copper plating, etc.)
  • the agent reduces the metal ions to metal and deposits them on the surface of the first pad 130 or the second pad 210 to form a metal coating.
  • the metal coating fills the first gap 11 to form a first conductive bump Block 31.
  • the first conductive bumps 31 are in contact with both the first bonding pads 130 and the second bonding pads 210 , thereby realizing electrical connection between the second chip 200 and the first wafer 100 .
  • the electroplating process includes electroless plating.
  • the plating solution used in the electroless plating is determined according to the materials of the first conductive bumps and the materials of the first bonding pads 130 and the second bonding pads 210 to be formed in practice.
  • the materials of the first pad 130 and the second pad 210 are selected from any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the material of the first conductive bump 31 includes: any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium or any combination thereof.
  • the height of the first conductive bumps 31 is 5-200 ⁇ m, such as 10 ⁇ m, 50 ⁇ m, and 100 ⁇ m.
  • the height of the first conductive bumps 31 ie the first voids 11 is 5-200 ⁇ m, it not only satisfies that the electroplating solution can easily enter the first voids 11 for electroplating, but also avoids the problem that the height of the first voids 11 is too high and the electroplating time is long. Therefore, both the electroplating efficiency and the electroplating yield are taken into account.
  • electroless palladium immersion gold wherein the time of chemical nickel is 30-50 minutes, the time of chemical gold is 4-40 minutes, and the time of chemical palladium is 7-32 minutes; The time is 30-50 minutes, and the time for chemical gold is 4-40 minutes.
  • electroplating process chooses electroless palladium immersion gold (ENEPIG) or electroless nickel gold (ENIG), the process parameters can refer to Table 1 below.
  • the surface of the pad Before electroless plating, in order to better complete the electroplating process, the surface of the pad can be cleaned first to remove the natural oxide layer on the surface of the pad and improve the surface wettability of the pad; after that, activation can be performed process to promote the nucleation and growth of the coating metal on the metal to be plated.
  • first conductive bumps 31 are formed, and the cross-sectional area of the formed first conductive bumps 31 is greater than 10 square microns, which can ensure that the area occupied by the first conductive bumps 31 will not be too large. If it is large, the bonding strength between the first conductive bumps 31 and the bonding pads can also be ensured.
  • the material of the first conductive bumps 31 is the same as that of the second bonding pads 210 and the first bonding pads 130 , so that the first conductive bumps 31 are more easily formed in the first voids 11 .
  • the material of the first bonding pad 130 and the second bonding pad 210 may be different from the material of the conductive bump.
  • the material may be formed on the first bonding pad 130 or the second bonding pad 210 first. layer, the material of the material layer is the same as the material of the conductive bump, and the method of forming the material layer can be a deposition process.
  • the first conductive bumps 31 may be solder connection bumps.
  • a capping layer 250 covering the second chip 200 is formed.
  • the cover layer 250 fills the gap between the second chips 200 and covers the first dielectric layer 160 on the surface of the first wafer 100 , and can be in contact with the first dielectric layer 160 to achieve sealing, so as to better Insulates air and moisture, thereby improving the encapsulation effect.
  • the cover layer 250 can be formed through an injection molding process, which has better filling performance, and can enable the injection molding agent to be well filled between the plurality of second chips 200 , so that the second chips 200 have a good encapsulation effect.
  • other processes may also be used to form the capping layer 250 .
  • the gap between the second chip 200 and the first wafer 100 is completely filled by the bonding layer, so the cover layer 250 does not need to be filled between the second chip 200 and the first wafer 100 , thereby saving energy The time of the plastic sealing process.
  • the cover layer 250 will enter the gap, and the first chip 110 will be better Insulation, sealing and protection.
  • a via interconnect structure 101 electrically connected to the first chip 110 is formed in the first wafer 100 .
  • the first wafer 100 is thinned through the backside of the first wafer 100 to reduce the thickness of the first wafer 100, thereby improving the heat dissipation effect of the first wafer 100;
  • the thickness of the wafer 100 is also beneficial to reduce the difficulty of forming the through-hole interconnection structure 101 and reduce the overall thickness of the package structure after packaging, thereby improving the performance of the package structure.
  • the process used in the thinning treatment may be a back grinding process, chemical mechanical polishing One or more of a (Chemical Mechanical Polishing, CMP) process and a wet etching process.
  • a deep trench isolation structure for defining the stop position is usually formed in the semiconductor substrate of the first wafer 100, so that the thinning Processing stops at the bottom of the deep trench isolation structure.
  • neutral doping ions eg, one or both of oxygen ions and nitrogen ions
  • a stop zone is formed in the bottom so that the thinning process stops at the bottom of the stop zone.
  • the bottom substrate layer of the semiconductor substrate may also be thinned, so that it can be more Good stop at the bottom of the insulator layer.
  • the thickness of the first wafer 100 should not be too small or too large. If the thickness is too small, the mechanical properties of the first wafer 100 will be correspondingly poor, and the The device and other structures in the first wafer 100 have adverse effects; if the thickness is too large, it is not conducive to improving the performance of the package structure. Therefore, in this embodiment, the thickness of the first wafer 100 after thinning is 5 ⁇ m to 10 ⁇ m.
  • the via interconnect structure 101 electrically connected to the first chip 110 is formed in the first wafer 100 . The electrical connection between the first chip 110 and other circuits is achieved through the via interconnect structure 101 .
  • the second chip 200 is electrically connected through the first conductive bumps 31 , the interconnect structure formed in the first chip 110 , and the via interconnect structure 101 is electrically connected with other circuits.
  • the silicon substrate of the first wafer 100 is formed with a through-hole interconnection structure 101 through a through-silicon via technology.
  • the via interconnect structure 101 may also be formed by other processes.
  • the material of the via interconnect structure 101 is copper.
  • the material of the via interconnect structure 101 may also be conductive materials such as aluminum, tungsten, and titanium.
  • the second wafer 600 before the step of forming the first conductive bumps 31 for electrically connecting the first pads 130 and the second pads 210 in the first voids 11 , the second wafer 600 is debonded. .
  • the cover layer 250 covering the second chip 200 may also be formed after the step of forming the first conductive bumps 31 for electrically connecting the first bonding pads 130 and the second bonding pads 210 in the first voids 11 . prior to the step of debonding the second wafer 600 .
  • the difference between this embodiment and the first embodiment is that the first surface of the first chip 110 also has an exposed external bonding pad 120 spaced apart from the first bonding pad 130 , and the second chip 200 is exposed to external bonding pads 120 . Pad 120 .
  • the first bonding pad 130 and the external bonding pad 120 are both interconnecting lead pads (Pad) of the first chip 110 , which are used to realize electrical connection between the first chip 110 and other chips or circuit structures.
  • the first bonding pad 130 and the external bonding pad 120 are electrically connected to different circuit structures in the first chip 110 .
  • the external bonding pads 120 are used to electrically lead out the stack formed by the first chip 110 and the second chip 200 , so as to realize the electrical connection between the stack and other substrates having circuit structures.
  • the exposed positions of the first pad 130 and the external pad 120 are protected by a dielectric layer (not marked) to prevent short circuits, and during the fabrication of the first wafer 100 , the dielectric layer is etched In order to expose the first pad 130 and the external pad 120, the surfaces of the first pad 130 and the external pad 120 are lower than the first surface, that is, the first surface is formed to expose the first pad 130 and the external pad respectively. 120 grooves.
  • a shielding layer 150 covering the external pads 120 is further formed.
  • the shielding layer 150 is used to protect the external pads 120 so as to prevent the external pads 120 from being exposed to the environment in which the first conductive bumps 31 are formed, thereby avoiding the formation of external interconnect bumps on the surface of the external pads 120 .
  • 31 has a certain volume, which accordingly can avoid the problem of connection between the external interconnection bump and the first conductive bump 31, which reduces the probability of electrical connection between the first pad 130 and the external pad 120, thereby improving the reliability of the package. sex.
  • the shielding layer 150 can prevent electroplating on the surface of the external pad 120 during the electroplating process, thereby preventing the external pad 120 from being electroplated.
  • External interconnection bumps are formed on the surface of 120 . Since the electroplating bodies formed by the electroplating process all have a certain volume, whether the connection between the external interconnection bumps and the first conductive bumps 31 can be avoided accordingly.
  • the process of forming the shielding layer 150 causes less damage to the first bonding pad 130 .
  • the shielding layer 150 will be removed later.
  • the process of removing the shielding layer 150 has little damage to the first pad 130 and can maintain the surface flatness of the first pad 130, thereby ensuring the reliability of the electroplating process.
  • the damage to the external bonding pads 120 is small, and the surface flatness of the external bonding pads 120 can be maintained, thereby ensuring the bonding reliability of the subsequent bonding wires 22 .
  • the material of the shielding layer 150 satisfies that the etching selection ratio between the shielding layer 150 and the first pad 130 is greater than 10:1, and the etching selection ratio between the shielding layer 150 and the external pad 120 is greater than 10:1.
  • the bonding layer 140 is formed for subsequently bonding the second chip 200 to the first surface of the first wafer 100 .
  • the bonding layer 140 can optionally be a photolithographic bonding material, an adhesive film, a metal dielectric layer or a polymer material, an adhesive film such as a DAF film (die attach film), a film-like material with double-sided adhesiveness, which can be used It can be patterned by etching or laser ablation; it can also be a dielectric layer, such as silicon oxide or nitride, which connects the chip and wafer by fusion bonding; or a polymer material. Combinations of these materials are also possible.
  • This embodiment uses a photolithographic bonding material, which can be formed on the surface of the first wafer 100 , the surface of the second chip 200 , or both on the first wafer 100 and the second chip 200 . .
  • Photolithographic bonding materials include dry film or liquid dry film, and may also include other photosensitive adhesive materials.
  • Liquid dry film means that the components in the film-like dry film exist in liquid form.
  • dry film is a permanently bonded film with high bond strength.
  • the film-like dry film may be formed on the first wafer 100 and/or the second chip 200 by means of film sticking, and the liquid dry film may be coated on the first wafer 100 and/or the second chip 200 by a spin coating process, and then The liquid dry film is cured.
  • the dry film needs to be subjected to a patterning process to expose the first pads 130 of the first wafer 100 and the second pads on the second chip 200, and to bond the first pads through the dry film
  • the dry film is a photolithographic material, which can form a desired pattern through a semiconductor process.
  • the process is simple and compatible with the semiconductor process, and can be mass-produced.
  • the elastic modulus of the dry film is relatively small, and can be easily deformed without being damaged when subjected to thermal stress, thereby reducing the bonding stress between the first wafer 100 and the second chip 200 .
  • the thickness of the photolithographic bonding material is 5-200 ⁇ m, such as 15 ⁇ m, 30 ⁇ m, 80 ⁇ m, 150 ⁇ m, and the like. It not only satisfies that the electroplating solution can easily enter the gap for electroplating, but also avoids the problem that the height of the gap is too high and leads to a long electroplating time, thus taking into account the electroplating efficiency and the electroplating yield.
  • the projection of the photolithographic bonding material in the direction of the surface of the first wafer 100 covers at least 10% of the area of the second chip.
  • the photolithographic bonding material is formed in a larger area, and especially the photolithographic bonding material is formed in the position where the capping layer is not easily filled in the later process.
  • the photoetchable bonding material of this solution not only plays the role of bonding, but also plays a role of sealing in advance.
  • the photoetchable bonding material and the cover layer in the subsequent process together play the role of sealing the first chip 110 .
  • the photolithographic bonding material covers the entire lower surface of the first chip 110 (except for the areas where the first pad 130 and the second pad are located), so that when the cover layer is formed in the subsequent process, the first There is no void below a chip 110, which improves the bonding strength and improves the yield.
  • the gap is set as non-closed, and the photolithographic bonding material leaves a fluid channel connecting the gap.
  • the lithographic bonding material surrounds the first pad 130 or the second bonding pad 210, but leaves a fluid channel to connect the gap to the edge of the chip, the fluid channel may or may not penetrate the lithographic bonding material ; Or the photolithographic bonding material does not surround or completely surround the first pad 130 or the second pad 210 , and the unsurrounded part communicates with the outside world as a fluid channel.
  • the gap communicates with the outside, and can also be used as a fluid channel; optionally, a channel is left in the photolithographic bonding material between the adjacent first chips 110 of the first wafer 100, and the channel communicates with the outside. , the channel extends to the gap formed by the first pad 130 and the second pad 210 , so that the external plating solution flows to the gap through the channel to form conductive bumps.
  • the photoetchable bonding material covers the peripheral area of the subsequently formed conductive bump, that is, defines the formation position of the conductive bump, that is to say, the photoetchable bonding material encloses the boundary of the gap , the subsequent conductive bumps cannot exceed the boundary, which facilitates the control of the electroplating process and prevents the lateral overflow of the formed conductive bumps. Because the physical connection between the first wafer 100 and the second chip 200 is achieved by the photolithographic bonding material, and the photolithographic bonding material covers the peripheral area of the conductive bump, the mechanical strength of the entire structure is directly enhanced, and the The filling and gluing process of the prior art is omitted. If the plastic encapsulation process is performed subsequently, the plastic encapsulation material does not need to fill the gap between the first chip 110 and the second chip 200 , thereby saving the time of the plastic encapsulation process.
  • the blocking layer 150 is removed.
  • the shielding layer 150 is removed to expose the external bonding pads 120 , so as to prepare for the subsequent electrical connection between the external bonding pads 120 and other substrates, chips or interconnect structures.
  • the process of removing the shielding layer 150 includes one or both of a plasma oxidation process and a plasma nitridation process.
  • the shielding layer 150 is removed by vaporization under the condition of oxygen) or nitrogen-containing gas (eg, nitrogen), which is not easy to damage the external bonding pad 120, and can maintain the surface flatness of the external bonding pad 120, thereby ensuring the subsequent bonding wire bonding reliability.
  • the material of the shielding layer 150 is a carbon-containing medium, therefore, the shielding layer 150 is removed by a plasma oxidation process.
  • the oxygen-containing gas (eg, oxygen) used in the plasma oxidation process can oxidize the carbon-containing medium to carbon dioxide, thereby directly removing the reaction by-products from the reaction chamber, so there is less damage to the electrodes, and it is also beneficial to reduce the generation of The probability of the blocking layer 150 remaining or reaction by-products.
  • the material of the shielding layer 150 is polyimide
  • a plasma oxidation process is used to remove the shielding layer 150 .
  • Polyimide is an organic material, therefore, the removal process of the polyimide layer does less damage to the first pad 130 and the external pad 120 .
  • the carbon-containing medium can react with the vapor-phase etchant to form a gas, and the process of removing the carbon-containing medium also causes less damage to the first pad 130 and the external pad 120 .
  • the carbonaceous medium may include amorphous carbon.
  • the first wafer 100 is cut to form a chip module (not shown), the chip module includes the second chip 200 and the first chip 110 bonded together .
  • the second chip 200 and the corresponding first chip 110 form an independent chip module, so as to prepare for the subsequent fixing of the chip module to other substrates.
  • the first wafer 100 is generally provided with scribe lines that are crisscrossed, and the scribe lines are disposed between any two adjacent first chips 110 on the first wafer 100 .
  • the first wafer 100 is diced.
  • the first wafer 100 between the first chips 110 is partially etched from the first surface to form trenches (not shown), and then the second surface is subjected to backside thinning to expose the trenches are formed to separate each of the first chips 110 .
  • the etching process has a wide process window, narrower dicing lines can be etched, thereby reducing the probability of damage to the second chip 200 and the first conductive bumps 31, and improving the performance of the first chip 110.
  • the edge chipping phenomenon reduces the probability of damage to the effective circuit inside the first chip 110 , thereby helping to obtain a complete independent stack, and further helping to improve package reliability.
  • the backside thinning process on the second surface enables lighter, thinner and smaller wafer-level chip packages.
  • laser cutting or mechanical cutting may also be used for cutting.
  • the chip module is bonded to the substrate 1 , and the substrate 1 has the circuit structure 2 therein.
  • the substrate 11 may be a printed circuit board (printed circuit board, printed circuit board).
  • the substrate 1 may also be an FPC board (flexible printed board). circuit board, flexible circuit board) or other types of substrates such as an interposer board.
  • the second surface is adhered to the substrate 1 through the adhesive layer 3 .
  • the adhesive layer 3 may be an adhesive film.
  • the bonding wire 22 is formed by a wire bonding process, and the bonding wire 22 is electrically connected to the external bonding pad 120 and the circuit structure 2 in the substrate 1 .
  • the shielding layer 150 is formed on the external pad 120 . After the first conductive bumps 31 are formed and before the first wafer 100 is cut, the shielding layer 150 needs to be removed, so that the shielding layers 150 can be removed at the same time. The shielding layer 150 on the bonding pad 120 is externally connected, thereby improving the packaging efficiency. In other embodiments, according to process requirements, the shielding layer 150 may also be removed after the second surface of the first chip 110 is bonded to the substrate 1 , thereby reducing the probability of the external pads 120 being oxidized, thereby facilitating the improvement of subsequent wire bond) process reliability. After the shielding layer 150 is removed, the bonding wire 22 is formed by a wire bonding process. The bonding wires 22 enable the external bonding pads 120 to be electrically connected to the circuit structure 2 , thereby realizing the system integration of the independent chip module composed of the first chip 110 and the second chip 200 and the substrate 1 .
  • the packaging method further includes: forming a capping layer 250 covering at least the first conductive bumps 31 and the bonding wires 22 .
  • the cover layer 250 plays a role in fixing the first chip 110 and the second chip 200 , and is used to realize package integration of the first chip 110 and the second chip 200 . Also, the capping layer 250 is used to achieve insulation, sealing and protection of the first conductive bumps 31 and the bonding wires 22 .
  • the highest point of the bonding wire 22 is lower than the surface of the second chip 200 facing away from the first chip 110 .
  • both the first conductive bumps 31 and the bonding wire 22 can be buried in the cover layer 250, and at the same time, it is easy to make the package structure The thickness is small.
  • the highest part of the bonding wire 22 may also be flush with the surface of the second chip 200 facing away from the chip.
  • the cover layer 250 also covers the surface of the second chip 200 facing away from the first chip 110 , so as to bury the second chip 200 , the first chip 110 , the first conductive bumps 31 and the bonding wires 22 . Further, it is beneficial to improve the packaging reliability. In other embodiments, the top surface of the cover layer 250 may also be flush with the surface of the second chip 200 facing away from the first chip 110 , or the cover layer 250 covers part of the sidewall of the second chip 200 .
  • the difference between this embodiment and the second embodiment is that after the second chip is bonded to the first wafer, when the first conductive bumps 31 filled in the first voids 11 are formed, the bumps are also formed. Electroplated interconnect bumps 45 out of the surface of external pads 120 .
  • the plated interconnect bumps 45 lead out the electrical properties of the first chip 110 so as to prepare for the subsequent packaging process.
  • the electrical connection of the first chip 110 to other substrates can be achieved by electroplating the interconnect bumps 45 .
  • the surface of the external bonding pads 120 is generally lower than the first surface of the first chip 110 .
  • the plated interconnect bumps 45 protrude from the surface of the external pads 120, which facilitates the subsequent wire bonding process, and the connection performance between the bonding wires and the plated interconnect bumps 45 is higher, which is conducive to improving the packaging. Reliability; in addition, while forming the electroplating first conductive bumps 31, the electroplating interconnect bumps 45 are formed, which is beneficial to improve the packaging efficiency.
  • this embodiment can improve packaging efficiency and packaging reliability while implementing wafer-level packaging.
  • the upper surfaces of the plated interconnect bumps 45 are flat surfaces, so as to ensure the reliability of subsequent wire bonding.
  • an interconnect chip 300 may also be provided, and the interconnect chip 300 may be one of the connectors.
  • the interconnection chip 300 includes an opposite third surface and a fourth surface, an interconnection structure 305 is formed in the interconnection chip 300, and a part of the interconnection structure 305 is exposed on the third surface and the fourth surface of the interconnection chip 300, respectively.
  • the connection structure 305 includes a plug, an interconnection line connected to the plug, and an interconnection pad, and the interconnection pad is the exposed part of the fourth surface of the interconnection chip 300; the interconnection chip 300 is also bonded to the first On the first surface of the wafer 100 , the second chip 200 may be arranged in parallel.
  • the fourth surface of the interconnect structure 305 faces the first wafer 100 .
  • the first wafer 100 may be provided with external bonding pads 120 at positions opposite to the interconnection pads to form the same gap as the second chip 200 .
  • Electroplated interconnect bumps 45 are formed in the gaps between the structures 305 and the first wafer 100 to interconnect with the first wafer 100 .
  • the interconnection structure 305 may also be electrically connected to the first wafer 100 in other manners, such as ball mounting. In addition, the interconnection structure 305 may not be electrically connected with the first wafer 100 but be physically connected with the first wafer 100 through the bonding layer 140 .
  • the interconnect structure 305 on the third surface can be interconnected with the back side of the second chip 200 by setting gold interconnect lines, for example, to realize the interconnection of the front and back sides of the second chip 200, and can also be used as a port for connecting with external circuits , to avoid the electrical connection from the second surface of the first wafer 100 , so as to realize the electrical connection between the second chip 200 or the first wafer 100 and the outside world.
  • the interconnecting chip 300 can lead the second chip 200 or the lead terminal (such as the I/O terminal) of the external circuit to the side of the first wafer 100 having the first bonding pad 130 and the external bonding pad 120 , which can be flexibly connected to the system level later Chips or devices or external circuits at various positions in the package reduce operations on the second chip 200 or the device wafer (eg, backside thinning or through-silicon via interconnection process), thereby reducing the need for the second chip 200 And the damage of the device wafer is beneficial to improve the packaging reliability, and the packaging method is suitable for the system integration of various wafers, and the packaging compatibility is correspondingly improved.
  • the lead terminal such as the I/O terminal
  • the difference from the first embodiment is that a cover 700 is bonded and connected to the first wafer 100 , an interconnection structure is formed in the cover 700 , and the interconnection structure includes the second pad 210 ;
  • the bonding layer 140 bonds the cap 700 to the first wafer 100 .
  • the cover 700 is a part of the to-be-integrated structure of the wafer level package, wherein an interconnect structure is formed, and the position of the first pad 130 on the wafer plane is changed while realizing the packaging of the first wafer 100 .
  • the cover 700 is fabricated by using an integrated circuit fabrication technology.
  • the second pad 210 is located on the first surface of the cover 700 , that is, the second pad 210 is exposed.
  • the cover 700 may include a substrate 710.
  • the material of the substrate refers to the first embodiment.
  • the cap 700 may not include the substrate 710 and only include the dielectric layer 730 on which the interconnect structure 305 is formed.
  • the cover 700 is obtained through the following steps: providing a substrate 710; forming a release layer 720 on the substrate 710, the release layer 720 covering the substrate 710; forming a dielectric layer 730 on the release layer 720, and forming a dielectric layer 730 on the The interconnect structure 305 is formed in it.
  • the step of forming the cap 700 may further include releasing the release layer 720 and removing the substrate 710 after the interconnect structure 305 is formed in the dielectric layer 730 . That is, the cap 700 includes only the dielectric layer 730 on which the interconnect structure 305 is formed. Substrate 710 provides support for the fabrication of interconnect structures of cap 700 . For the description of the substrate 710 of the cover 700, reference may be made to the foregoing related descriptions, and details are not repeated here.
  • the release layer 720 facilitates the removal of the substrate 710.
  • the release layer 720 is a germanium release layer; in other embodiments, the material of the release layer 720 is at least one of carbon and pyrolysis film; When 710 is a light-transmitting glass, the material of the release layer 720 can also be a photolysis film.
  • the dielectric layer 730 provides a forming space for the interconnect structure 305. As shown in FIG. 10, a dielectric material layer is first deposited on the release layer 720, and then etching and filling are performed at the corresponding positions of the dielectric material layer to form the interconnect structure. .
  • the material of the dielectric layer 730 is high-resistance silicon, and the material of the interconnect structure is copper, and the resistivity of copper is relatively low.
  • the material of the dielectric layer 730 can also be other materials with higher resistance, and the material of the interconnect structure can also be other applicable conductive materials, such as: nickel, zinc, tin, gold, tungsten, magnesium.
  • the interconnection structure further includes a third solder pad 220 that is electrically connected to the second solder pad 210 , and the third solder pad 220 and the second solder pad 210 are respectively located on two opposite sides of the cover 700 surface.
  • the third solder pad 220 and the second solder pad 210 are respectively located on two opposite sides of the cover 700 surface.
  • the cover 700 includes a substrate 710 and a release layer 720 , and the third pad 220 and the second pad 210 are respectively located on two opposite surfaces of the cover 700 , which means that the interconnect structure can be Including the second pad 210 on the first surface of the dielectric layer 730 and the third pad 220 on the second surface of the dielectric layer 730, of course, the second pad 210 and the third pad 220 may also be electrically connected.
  • the plug includes a redistribution layer (RDL) structure (not shown in the figure), and the first surface of the dielectric layer 730 is opposite to the second surface of the dielectric layer 730 .
  • RDL redistribution layer
  • the cover 700 only includes a dielectric layer on which the interconnect structure 305 is formed, then the third pads 220 and the second pads 210 are located on two opposite surfaces of the dielectric layer 730 respectively, that is, they are respectively located on the cover 700 opposite surfaces.
  • a thinning process may be performed after the processing of the interconnect structure 305 or the 100-level packaging of the first wafer is completed.
  • the release layer 720 is first formed on the substrate 710, and then the dielectric layer 730 is formed on the release layer 720.
  • the substrate 710 can provide support for the processing of the interconnect structure 305, or simultaneously provide the cover 700 and the first die.
  • the bonding of the circle 100 provides support; on the other hand, the presence of the release layer 720 can be achieved through the release of the release layer 720 after the processing of the interconnect structure 305 or the bonding of the cap 700 and the first wafer 100 is completed.
  • Removing the substrate 710 improves the convenience of removing the substrate 710, and can also achieve accurate control of the removal of the substrate 710, avoiding the device caused by the low accuracy of thickness control caused by the removal of the substrate 710 by grinding. damage and improve product yield.
  • the dielectric layer 730 may also be directly formed on the substrate 710 to form an interconnection structure.
  • a conductive block may also be formed by implanting balls on the third bonding pad 220 to achieve electrical connection with an external circuit.
  • the cap 700 may be a wafer-level cap 700 , that is, the cap 700 has a wafer size, and the number of interconnect structures of the cap 700 is the same as that of the first pads 130 of the first wafer 100 .
  • the cover 700 is the wafer-level cover 700
  • the wafer-level packaging can be realized by one-time bonding, which can simplify the processing process and improve the packaging speed.
  • the cover 700 may be a chip-level cover, and the providing the cover 700 herein includes providing a plurality of chip-level covers, and the number of the chip-level covers may be the same as that of the first chips 110 of the first wafer 100 The number is the same as the number of the first chips 110 of the first wafer 100 .
  • the number of the second pads 210 of each chip-level cap is the same as the number of the first pads 130 of each of the first chips 110 . the same number.
  • the structures of the chip-level caps may be the same, or may be different on the basis of ensuring subsequent bonding and packaging requirements; when the first wafer 100 has the same structure
  • chip-level covers with different structures can be selected to realize the transfer interconnection of different first chips 110 .
  • a plurality of discrete chip-level caps can be obtained by dicing the wafer-level caps.
  • the release layer 720 is released, and the substrate 710 is removed. After the first conductive bumps 31 are formed, conductive bumps 740 are formed on the third pads.
  • the release layer 720 is released after the bonding of the cover 700 and the first wafer 100 is completed, which can reduce the thickness requirement for the dielectric layer 730 of the cover 700 and reduce the difficulty of bonding.
  • the opening is formed first and then the release layer 720 is released, so that the etching area or the heating area of the release layer 720 can be enlarged, the removal speed of the release layer 720 can be improved, and the processing efficiency can be improved.
  • the substrate 710 is a silicon substrate, and the release layer 720 is a germanium release layer; the release layer 720 can be etched through a wet etching process to remove the release layer 720 and the substrate 710 .
  • the release layer 720 and the substrate 710 can be removed by heating, and when the material of the release layer 720 is a photolytic film, and the substrate 710 In the case of light-transmitting glass, the release layer 720 and the substrate 710 can be removed by means of light.
  • the release layer 720 and the substrate 710 may also be removed first, and then cut to form the opening.
  • the difference from the second embodiment is that the third pad 220 is provided on the second chip 200 , the third chip 400 is bonded on the second chip 200 , and the third chip 400 is subjected to an electroplating process or a ball-mounting process.
  • the third pad 220 is connected.
  • the third chip 400 shown in the figure is connected to the third pads 220 by an electroplating process, which can be performed at the same time as the electroplating process of the first chip 110 and the second chip 200, which can save manufacturing process and efficiently complete the electrical connection of the chip stack.
  • the third chip 400 can be connected to the backside of the second chip 200 through the bonding layer 140 first, and the third pad 220 of the second chip 200 is opposed to the fourth pad 410 of the third chip 400 to form a gap, and then formed later Electroplated second conductive bumps 312 .
  • the third chip 400 can also be bonded on the second chip 200 through a ball-mounting process, without the material of the bonding layer 140, as shown in the figure Not shown.
  • the fourth chip 500 is bonded to the backside of the first wafer 100 .
  • the fifth pad is formed on the backside of the first wafer 100 , including: performing an electroplating process on the fifth
  • a third conductive bump is formed on the bonding pad for electrically connecting the first wafer 100 and the fourth chip 500 .
  • the third chip 400 may be bonded on the second chip 200 on the front side of the first wafer 100
  • the fourth chip 500 may be bonded on the back side
  • the second chip 200 may be bonded on the second chip 200 .
  • a first gap 11 is formed between the pad 210 and the first bonding pad 130 on the front side of the first wafer 100
  • a second gap is formed between the second chip 200 and the first chip 110
  • the bonding pad on the backside of the fourth chip 500 is connected to the first chip 110 .
  • a third gap is formed between the pads on the backside of a wafer 100.
  • the second chip 200 on the front side and the first wafer 100, the third chip 400 and the second chip 200, and the backside are simultaneously formed.
  • Conductive bumps are formed between the fourth chip 500 and the first wafer 100 .
  • the electroplating process for forming the conductive bumps on the front side and the back side can be performed simultaneously or separately; the bonding process on the front side of the first wafer 100 can also be performed first, and then the backside electroplating process can be performed.
  • the second bonding pad 210 and the third bonding pad 220 are interconnected by TSV, but in this embodiment, it is not limited to this situation, and the second bonding pad 210 and the third bonding pad 220 may be interconnected by other
  • the electrical connection is realized by means of connection, for example, the electrical connection between the second bonding pad 210 and the corresponding third bonding pad 220 is realized by interconnecting wires and plugs.
  • Embodiments 1 to 6 of the present invention describe various specific situations, wherein various situations described in Embodiments 1 to 6 can be combined to form new embodiments as required.
  • the present invention will not describe them one by one, and those skilled in the art can obtain specific embodiments that are different from the situations listed in Embodiments 1 to 7 according to the teachings of the present invention.
  • a first wafer 100 includes a plurality of first chips 110 .
  • the first chip 110 includes a first surface and a second surface opposite to each other, and the first surface has a bare surface.
  • the second bonding pad 210 and the first bonding pad 130 are opposite up and down, and the first bonding pad 130 and the second bonding pad 210 include a facing part and a staggered part; the first conductive bumps 31 formed by the electroplating process are connected The second pad 210 and the first pad 130 .
  • a first dielectric layer 160 exposing the first bonding pads 130 is formed on the surface of the first wafer 100
  • a second chip 200 exposing the second bonding pads 210 is also formed on the surface of the second chip 200 facing the first wafer 100 .
  • the first wafer 100 is a wafer including the first chip 110 or a single chip including the first chip 110 .
  • the first chip 110 has a first surface and a second surface opposite to each other, and the first surface of the first chip 110 is bonded to the first surface.
  • the second chip 200 is combined.
  • the surface of the second chip 200 has the exposed second bonding pads 210 .
  • the positional relationship between the second bonding pads 210 and the first bonding pads 130 and other related contents refer to the foregoing embodiments in detail.
  • the related contents of the bonding pads and the first conductive bumps 31 refer to the foregoing embodiments, and are not repeated here.
  • the surface of the second chip 200 has external bonding pads 120 that are exposed and spaced apart from the first bonding pads.
  • external bonding pads 120 For the related content of the external bonding pads, refer to the foregoing.
  • a plated interconnect bump 45 is further formed, protruding from the surface of the external pad 120 , and the function and related description of the plated interconnect bump 45 are referred to above.
  • the second chip 200 is provided with a third pad 220, the second chip 200 is bonded with a third chip 400, the third chip 400 includes a fourth pad 410, and the third The second conductive bumps 312 formed by the electroplating process are electrically connected between the pads 220 and the fourth pads 410 .
  • a fifth pad is formed on the other side of the first wafer 100 opposite to the second chip 200 , and the method further includes: forming conductive bumps on the fifth pad through an electroplating process.
  • the difference between the present embodiment and the seventh embodiment is that the cover 700 is bonded and connected to the first wafer 100 in this embodiment, and an interconnection structure is formed in the cover 700 .
  • the interconnection structure The second pad 210 is included; the cover 700 is bonded to the first wafer 100 by using the bonding layer 140 .

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Abstract

本发明公开一种晶圆级系统封装方法及晶圆级系统封装结构，包括：提供第一晶圆，所述第一晶圆中形成有多个第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一芯片的第一表面具有裸露的第一焊垫；提供封盖或多个第二芯片，所述第二芯片或封盖的表面具有裸露的第二焊垫；利用键合层将所述第二芯片或封盖键合于所述第一晶圆，所述第二焊垫和第一焊垫上下相对，围成第一空隙；相对的所述第一焊垫和第二焊垫包括正对部分和错开部分；通过电镀工艺，在所述第一空隙中形成使所述第一焊垫和第二焊垫电连接的第一导电凸块。本发明在实现晶圆级系统封装的同时，提高封装效率和可靠性、降低封装成本。

Description

晶圆级系统封装方法及晶圆级系统封装结构 技术领域
本发明实施例涉及半导体封装技术领域，尤其涉及一种晶圆级系统封装方法及晶圆级系统封装结构。
 背景技术
随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小，人们对集成电路的封装技术的要求相应也不断提高。现有的封装技术包括球栅阵列封装（ball grid array，BGA）、芯片尺寸封装（chip scale package，CSP）、晶圆级封装（wafer level package，WLP）、三维封装（3D）和系统封装（system in package，SiP）。
 技术问题
目前，为了满足集成电路封装的更低成本、更可靠、更快及更高密度的目标，先进的封装方法主要采用三维立体堆叠模式的晶圆级系统封装（wafer level package system in package，WLPSIP），与传统的系统封装相比，晶圆级系统封装是在晶圆上完成封装集成制程，具有大幅减小封装结构的面积、降低制造成本、优化电性能、批次制造等优势，可明显的降低工作量与设备的需求。
在晶圆级系统封装工艺中，不仅需要将两片裸芯片键合在一起以实现物理连接，同时还需要连接其互连引线，从而实现电性连接。
 技术解决方案
本发明实施例解决的问题是提供一种晶圆级系统封装方法及晶圆级系统封装结构，在实现晶圆级封装的同时，提高封装效率和封装可靠性、降低封装成本。
为解决上述问题，一方面，本发明实施例提供一种晶圆级系统封装方法，包括：提供第一晶圆，所述第一晶圆中形成有多个第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一芯片的第一表面具有裸露的第一焊垫；提供封盖或多个第二芯片，所述第二芯片或封盖的表面具有裸露的第二焊垫；利用键合层将所述第二芯片或封盖键合于所述第一晶圆，所述第二焊垫和第一焊垫上下相对，围成第一空隙；相对的所述第一焊垫和第二焊垫包括正对部分和错开部分；通过电镀工艺，在所述第一空隙中形成使所述第一焊垫和第二焊垫电连接的第一导电凸块。
另一方面，本发明实施例还提供一种晶圆级系统封装结构，包括：第一晶圆，包含多个第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有裸露的且相间隔的第一焊垫；封盖或多个第二芯片，所述封盖或所述第二芯片的表面具有裸露的第二焊垫；键合层，将所述第二芯片或封盖键合于所述第一晶圆的第一表面上，所述第二焊垫和第一焊垫上下相对，所述第一焊垫和所述第二焊垫包括正对部分和错开部分；电镀工艺形成的第一导电凸块，连接所述第二焊垫和所述第一焊垫。
 有益效果
与现有技术相比，本发明实施例的技术方案具有以下优点：本发明实施例通过电镀工艺形成填充于第一空隙中的第一导电凸块，从而实现晶圆级封装，在实现晶圆级封装的同时，提高封装效率和封装可靠性、降低封装成本。第一焊垫与第二焊垫具有正对部分和错开部分，错开的部分可以更容易与电镀液接触，这样可以避免由于空隙小而导致电镀液不容易流入空隙而导致无法形成比较完好的第一导电凸块的问题，可以更好的实现电镀工艺，使形成的第一导电凸块尽可能完整的填充空隙内，避免形成的导电凸块与焊垫接触面积过小而导致电阻增大。
 附图说明
图1至图4是本发明晶圆级系统封装方法实施例一中各步骤对应的结构示意图。
图5-图8是本发明晶圆级系统封装方法实施例二中各步骤对应的结构示意图。
图9是本发明晶圆级系统封装方法实施例三中各步骤对应的结构示意图。
图10是本发明晶圆级系统封装方法实施例四中各步骤对应的结构示意图。
图11至图13是本发明晶圆级系统封装方法实施例五中各步骤对应的结构示意图。
图14至图16是本发明晶圆级系统封装方法实施例六中各步骤对应的结构示意图。
 本发明的实施方式
实施例一
参考图1，提供第一晶圆100，第一晶圆100中形成有多个第一芯片110，第一芯片110包括相对的第一表面和第二表面，第一芯片110的第一表面具有裸露的第一焊垫130。
第一晶圆100为完成器件制作的待封装晶圆，本实施例中，第一晶圆100为器件晶圆（CMOS Wafer），第一晶圆100的半导体衬底为硅衬底。在其他实施例中，半导体衬底还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟等其他材料，半导体衬底还能够为绝缘体上的硅衬底或者锗衬底等其他类型的衬底。半导体衬底的材料可以是适宜于工艺需要或易于集成的材料。根据实际工艺需求，第一晶圆100的厚度为10微米至100微米。
形成于第一晶圆100中的多个第一芯片110可以为同一类型或不同类型的芯片。需要说明的是，第一晶圆100可以采用集成电路制作技术所制成，例如在第一半导体衬底上通过沉积、刻蚀等工艺形成N型金属氧化物半导体（N-Metal-Oxide-Semiconductor，NMOS）器件和P型金属氧化物半导体（P-Metal-Oxide-Semiconductor，PMOS）器件等器件，在器件上形成介质层、金属互连结构以及与金属互连结电连接的焊盘等结构，从而使第一晶圆100中集成至少一个第一芯片110。
位于第一芯片110表面的第一焊垫130，用于实现第一芯片110与其他半导体器件的电性连接。具体地，第一焊垫130可以是引线焊盘（Pad）。为了后续更好的实现电镀，形成比较完好的第一导电凸块，第一焊垫130的设置也需要满足一定的要求，比如：暴露出的第一焊垫130的面积为5平方微米至200平方微米。当暴露出的第一焊垫130的面积设置在上述范围内时，在后续电镀工艺的过程中，第一焊垫130可以与电镀液较充分的接触，避免第一焊垫130与镀液不充分接触而影响第一导电凸块与第一焊垫130的接触性能，比如接触面积过小影响接触电阻，或者，无法接触造成电接触不良，而且，还可以保证接触面积不会过大而降低电镀效率，同时也不会占用过多的面积。
继续参考图1，第一晶圆100的表面形成有露出第一焊垫130的第一介质层160。第一介质层160具有一定的厚度，可以在键合步骤中为形成第一空隙11提供空间；此外，第一介质层160具有绝缘特性，还用于在第一空隙11中形成第一导电凸块后，实现第一导电凸块与其他部件的绝缘。在本实施例中，第一介质层160还用作键合层，用于实现第一晶圆100和待集成芯片之间的物理连接。本实施例中，第一介质层160为第一氧化层，第一氧化层的材料为氧化硅。氧化硅材料具有较高的工艺兼容性，且氧化硅为工艺常用、成本较低的材料，因此通过选取氧化硅材料的方式，有利于降低工艺难度和工艺成本，且有利于降低对所形成封装结构的性能影响。在其他实施例中，第一氧化层还可以为氧化铪、氧化铝或氧化镧等氧化物材料。其他实施例中，第一介质层160还可以为有机材料，有机材料包括可光刻键合材料，可光刻材料包括干膜或粘片膜（Die Attach Film，DAF）。
继续参考图1，提供多个第二芯片200，第二芯片200的表面具有裸露的第二焊垫210；利用键合层将第二芯片200键合于第一晶圆100，第二焊垫210和第一焊垫130上下相对，围成第一空隙11；相对的第一焊垫130和第二焊垫210包括正对部分和错开部分。
第二芯片200用于作为晶圆级系统封装中的待集成芯片，本实施例晶圆级系统封装方法用于实现异质集成。相应地，多个第二芯片200可以是硅晶圆制成的芯片，也可以是其他材质形成的芯片。第二芯片200采用集成电路制作技术所制成，多个第二芯片200为同功能芯片；或者，多个第二芯片200至少包括两种不同功能的芯片。第二芯片200包括裸芯片，具有覆盖层250的芯片，顶面具有屏蔽层的芯片，顶面具有电性引出端的芯片，或者第二芯片200包括逻辑芯片、存储芯片、中央处理器芯片、微处理器芯片、模数转换芯片的至少之一，或者第二芯片200包括麦克风、压力传感器、陀螺仪、速度传感器、加速度传感器中的至少一种MEMS芯片，感测传感射频信号、红外辐射信号、可见光信号、声波信号、电磁波信号其中之一的传感器芯片，芯片中有空腔或者未含空腔，或者第二芯片200包括具有CMOS、CIS、二极管、三极管至少之一的PN结器件，或者第二芯片200包括电感、电容、滤光片、MLCC、连接件至少之一的无源器件。多个第二芯片200的种类可以相同也可以不同。
传感器芯片可以是应用在5G设备中的射频模组芯片，但不限于5G射频传感器模组芯片，还可以是其他类型的射频模组芯片。接收红外辐射信号的模组芯片可以是热像仪、额温枪、其他类型中的测温或成像等利用红外辐射信号的红外传感器模组芯片。传感器模组芯片还可以是摄像头模组芯片，比如包括感光芯片以及滤光片的模组芯片，可以接收可见光用来成像。传感器模组芯片还可以是麦克风模组芯片，可以接收声波用来传递声音信号。本发明中的传感器模组芯片不限于在此列举的类型，可以为本领域可以实现一定功能的各种类型的传感器模组芯片。MEMS芯片包括麦克风、压力传感器、陀螺仪、速度传感器、加速度传感器、热电堆传感器中的至少一种。滤波器芯片包括：表面声波谐振器、体声波谐振器至少其中之一。MLCC芯片包括：NP0、C0G、Y5V、Z5U、X7R、X5R等电容器。
位于第二芯片200表面的第二焊垫210为引线焊盘（Pad），用于实现第二芯片200与其他半导体器件的电性连接。具体地，第二焊垫210可以是引线焊盘（Pad）。第二焊垫210可以是焊盘，但不限于焊盘，也可以是其他具有电连接功能的导电块。第二焊垫210的材料为导电材料。本实施例中，第二焊垫210的材料包括：铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或多种。本实施例中，基于与第一焊垫130相类似的原因，暴露出的第二焊垫210的面积为5平方微米至200平方微米。
继续参考图1，第二芯片200上形成有露出第二焊垫210的第二介质层260。第二介质层260的作用和材料与第一介质层160相同，具体请参考第一介质层160。
第二芯片200具有第二焊垫210的面为正面，与正面相背的面为背面。本实施例中，提供多个第二芯片200的步骤包括：提供第二晶圆600，多个第二芯片200的背面临时键合于第二晶圆600上。具体地，多个第二芯片200形成于第二晶圆600上，第二晶圆600作为载体晶圆，用于临时固定多个第二芯片200，第二晶圆600还用于在第二芯片200与第一晶圆100键合的过程中，为第二芯片200起到支撑作用，从而提高键合的可靠性。
本实施例中，第二晶圆600上形成有粘合层610，多个第二芯片200通过粘合层610临时键合于第二晶圆600上。具体地，粘合层610包括粘片膜（Die Attach Film，DAF）和干膜（Dry Film）中的一种或两种。其中，干膜是一种用于半导体芯片封装或印刷第一晶圆100制造时所采用的具有粘性的光致抗蚀膜，干膜的制造是将无溶剂型光致抗蚀剂涂在涤纶片基上，再覆上聚乙烯薄膜；使用时揭去聚乙烯薄膜，把无溶剂型光致抗蚀剂压于基版上，经曝光显影处理，即可在干膜内形成图形。其他实施例中，所示粘合层610还可以为UV膜或发泡胶。UV膜具有粘性，经过UV光照射进行解键合，发泡胶通过加热解键合。在其他实施例中，还可以通过静电键合的方式，使第二芯片200临时键合于第二晶圆600上。静电键合技术是不用任何粘结剂实现键合的一种方法。在键合过程中，将要键合的第二芯片200和第二晶圆600分别连接不同的电极，在电压作用下使第二芯片200和第二晶圆600表面形成电荷，且第二芯片200与第二晶圆600表面电荷电性不同，从而在第二芯片200与第二晶圆600键合过程中产生较大的静电引力，实现两者的物理连接。
在其他实施例中，可以不设置第二晶圆600，直接将第二芯片200依次键合至第一芯片110上。其他实施例中，可以不形成第一介质层160和第二介质层260，通过干膜将第二芯片200与第一芯片110键合。
将第二介质层260与第一介质层160相对设置，使第二芯片200键合于第一晶圆100，且第二芯片200与第一芯片110的位置相对应，在第一焊垫130和第二焊垫210之间形成第一空隙11。此处，第二芯片200与第一芯片110位置相对应的含义指的是，第二芯片200与第一芯片110键合时相互对准，且第二芯片200上的第二焊垫210与第一芯片110的第一焊垫130也相对设置且相互对准。由于第二介质层260和第一介质层160均具有一定的厚度，在第二介质层260与第一介质层160相对设置并相互贴合时，因为两层介质层的支撑作用，在第一介质层160露出的第一焊垫130和第二介质层260露出的第二焊垫210之间形成第一空隙11。
需要说明的是，本实施例中，第一焊垫130位于第一芯片110的端部；第二焊垫210位于第二芯片200的端部；第二介质层260在第二焊垫210的位置处并没有与第一介质层160相接触，从而使第一空隙11在第二焊垫210和第一介质层160之间形成开口。
本实施例中，第二芯片200键合于第一晶圆100的步骤包括：将第二晶圆600与第一晶圆100相对设置，使第二晶圆600上第二芯片200的正面键合于第一晶圆100。这样在将第二芯片200与第一晶圆100键合的过程中，第二晶圆600可以为第二芯片200提供较大的支撑强度，从而提高第一芯片110与第二芯片200的之间的键合可靠性。
本实施例中，第二芯片200与第一晶圆100之间通过第一氧化层和第二氧化层的熔融键合工艺实现键合。具体地，第二芯片200与第一晶圆100是通过氧化硅-氧化硅熔融键合的方式实现物理连接。熔融键合是一种主要利用界面化学力完成键合的工艺，在熔融键合工艺过程中，第一氧化层和第二氧化层的表面活性得以提高，从而使第一氧化层和第二氧化层的接触面之间形成共价键并以共价键的方式实现键合，且第一氧化层和第二氧化层之间具有较高的键合强度，进而提高晶圆级系统封装的封装成品率。需要说明的是，在其他实施例中，第二芯片200和第一晶圆100还可以通过其他方式实现键合，比如：黏着键合或玻璃介质键合。
本实施例中，第一空隙11的高度为5μm至200μm，在后续进行电镀工艺的过程中，不仅有利于使得电镀液容易进入第一空隙11内进行电镀工艺，还有利于避免第一空隙11的高度太大而导致电镀时间过长的问题，从而兼顾了电镀效率与电镀的良率。
本实施例中，为了可以更好进行电镀工艺，可以设计第一焊垫130和第二焊垫210包括正对部分、错开部分。其中，第一焊垫130和第二焊垫210包括正对部分，以保证后续形成的第一导电凸块31与第一焊垫130和第二焊垫210之间均具有良好的接触，进而保证通过第一导电凸块31，第一焊垫130和第二焊垫210之间能够具有良好的电性连接。另一方面，第一焊垫130和第二焊垫210还包括错开部分，错开的部分更容易与电镀液接触，有利于使得在第一空隙11较小的情况下，电镀液也易于流入第一空隙11内，进而有利于形成比较完好的第一导电凸块31。本实施例中，以第一焊垫130和第二焊垫210正对作为示意，二者也可以错开设置。本实施例中，第一焊垫130和第二焊垫210的正对部分的面积大于第一焊垫130或第二焊垫210面积的二分之一，可以更好的实现电镀工艺，有利于使得形成的第一导电凸块31尽可能完整地填充于第一空隙11内，从而保证第一导电凸块31与第一焊垫130、第二焊垫210之间均具有足够的接触面积，相应有利于实现较低的接触电阻。
参考图2，在形成第一空隙11之后，解键合第二晶圆600，使第二晶圆600与第二芯片200相分离；通过电镀工艺，在第一空隙11中形成使第一焊垫130和第二焊垫210电连接的第一导电凸块31。
本实施例中，第二晶圆600通过粘合层610与第二芯片200相贴合，相应地，在解键合的过程中，可以通过化学方法或机械剥离的方式使第二晶圆600与第二芯片200相分离。在其他实施例中，也可以采用其他方式使第二晶圆600与第二芯片200分离。粘合层610为UV膜时通过UV光照射进行解键合；粘合层610为发泡胶时通过加热解键合。
第一导电凸块31填充于第一空隙11中，与第一焊垫130和第二焊垫210均相接触，因此可以实现第一焊垫130和第二焊垫210的电性连接，进而实现第一芯片110和第二芯片200之间的电性连接。可以通过电镀工艺形成第一导电凸块31。通过电镀方法形成的第一导电凸块31，可在第一空隙11中实现良好的填充效果，进而提高第一焊垫130和第二焊垫210之间电性连接的可靠性。
本实施例中，电镀工艺为无电解镀。具体地，键合后的第二芯片200与第一晶圆100放置到含有金属离子的溶液（例如：化学镀银、镀镍、镀铜等溶液）中，根据氧化还原反应原理，利用强还原剂使金属离子还原成金属而沉积在第一焊垫130或第二焊垫210的表面，形成金属镀层，经过一段反应时间之后，金属镀层将第一空隙11填满，从而形成第一导电凸块31。第一导电凸块31与第一焊垫130和第二焊垫210均相接触，进而实现了第二芯片200与第一晶圆100之间的电性连接。
本发明中，电镀工艺包括化学镀。其中，化学镀采用的镀液根据实际中需要形成的第一导电凸块的材料以及第一焊垫130、第二焊垫210的材料确定。第一焊垫130、第二焊垫210的材料选自铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。第一导电凸块31的材料包括：铜、钛、铝、金、镍、铁、锡、银、锌或铬中的任意一种或它们的任意组合。可选实施例中，第一导电凸块31的高度为5-200μm，如10μm、50μm、100μm。当第一导电凸块31即第一空隙11的高度为5-200μm时，既满足了电镀液容易进入第一空隙11进行电镀，也避免了第一空隙11高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。可以选择，化学镀钯浸金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟，化学钯的时间为7-32分钟；或，化学镍金，其中化学镍的时间为30-50分钟，化学金的时间为4-40分钟。
电镀工艺选择化学镀钯浸金（ENEPIG）或化学镍金（ENIG）时，工艺参数可以参照下表1。
表1
Figure 929374dest_path_image001
在进行化学镀之前，为了更好的完成电镀工艺，可以先对焊垫的表面进行清洁，以去除焊垫表面的自然氧化层、提高焊垫的表面湿润度（wetabilities）；之后，可以进行活化工艺，促进镀层金属在待镀金属上的形核生长。
为了更好的实现电镀，形成比较完善的第一导电凸块31，形成的第一导电凸块31的横截面积大于10平方微米，既可以保证第一导电凸块31占用的面积不会太大，也可以保证第一导电凸块31与焊垫之间的结合强度。
可选方案中，第一导电凸块31的材料与第二焊垫210、第一焊垫130的材料相同，这样更容易在第一空隙11中形成第一导电凸块31。当然，第一焊垫130、第二焊垫210的材料可以与导电凸块的材料不同，为了后续更容易形成导电凸块，可以在第一焊垫130或第二焊垫210上先形成材料层，该材料层的材料与导电凸块的材料相同，形成材料层的方法可以为沉积工艺。具体地，第一导电凸块31可以为焊接连接块。
参考图3，形成覆盖第二芯片200的覆盖层250。
本实施例中，覆盖层250填充第二芯片200之间的间隙且覆盖在第一晶圆100表面的第一介质层160上，可以与第一介质层160相接触实现密封，从而更好地隔绝空气和水分，进而提高了封装效果。具体地，可以通过注塑工艺形成覆盖层250，注塑工艺的填充性能较好，可以使注塑剂较好地填充在多个第二芯片200之间，从而使第二芯片200具有良好的封装效果。在其他实施例中，还可以采用其他工艺形成覆盖层250。
在本实施例中，第二芯片200与第一晶圆100之间的间隙被键合层完全填充，因此覆盖层250无需填充在第二芯片200与第一晶圆100之间，从而可以节省塑封工艺的时间。当然，本发明中，如果第二芯片200与第一晶圆100之间如果并没有完全被键合层占据、存在间隙，则覆盖层250会进入该间隙，对第一芯片110进行更好的绝缘、密封以及保护作用。
参考图4，在第一晶圆100中形成与第一芯片110电连接的通孔互连结构101。
具体地，通过第一晶圆100的背面对第一晶圆100进行减薄处理，以减小第一晶圆100的厚度，从而改善第一晶圆100的散热效果；此外，减小第一晶圆100的厚度还有利于减小形成通孔互连结构101的难度以及减小封装后封装结构的整体厚度，进而提高封装结构的性能。本实施例中，减薄处理所采用的工艺可以为背部研磨工艺、化学机械抛光 (Chemical Mechanical Polishing，CMP)工艺和湿法刻蚀工艺中的一种或多种。为了有效控制减薄处理的停止位置，在第一晶圆100的制造工艺中，通常在第一晶圆100的半导体衬底内形成用于限定停止位置的深沟槽隔离结构，从而使减薄处理停止于深沟槽隔离结构的底部。在另一实施例中，还可以在第一晶圆100的制造工艺中，采用中性掺杂离子（例如氧离子和氮离子中的一种或两种）在第一晶圆100的半导体衬底内形成停止区，从而使减薄处理停止于停止区的底部。在其他实施例中，当第一晶圆100的半导体衬底为绝缘体上的硅衬底或者绝缘体上的锗衬底时，还可以对半导体衬底的底部衬底层进行减薄处理，从而能够较好地停止于绝缘体层的底部。
需要说明的是，在减薄处理后，第一晶圆100的厚度不宜过小，也不宜过大，如果厚度过小，则第一晶圆100的机械性能相应较差，且容易对形成于第一晶圆100内的器件等结构产生不良影响；如果厚度过大，则不利于提高封装结构的性能。为此，本实施例中，减薄之后第一晶圆100的厚度为5μm至10μm。在减薄处理后，在第一晶圆100内形成与第一芯片110电连接的通孔互连结构101。通过通孔互连结构101实现第一芯片110与其他电路的电性连接。由于第一芯片110与第二芯片200通过第一导电凸块31电性连接，因此第二芯片200通过第一导电凸块31、第一芯片110中形成的互连结构以及通孔互连结构101与其他电路电性连接。
本实施例中，第一晶圆100硅衬底，通过硅通孔技术形成通孔互连结构101。在其他实施例中，还可以通过其他工艺形成通孔互连结构101。本实施例中，通孔互连结构101的材料为铜。在其他实施例中，通孔互连结构101的材料还可以为铝、钨和钛等导电材料。
需要说明的是在上述封装方法的实施例中，第一空隙11中形成使第一焊垫130和第二焊垫210电连接的第一导电凸块31的步骤之前，解键合第二晶圆600。在其他实施例中，还可以在第一空隙11中形成使第一焊垫130和第二焊垫210电连接的第一导电凸块31的步骤之后，形成覆盖第二芯片200的覆盖层250的步骤之前，解键合第二晶圆600。
实施例二
参考图5，本实施例与实施例一的区别之处在于：第一芯片110的第一表面还具有裸露的且与第一焊垫130相间隔的外接焊垫120且第二芯片200露出外接焊垫120。
在本实施例中，第一焊垫130和外接焊垫120均为第一芯片110的互连引线焊盘（Pad），用于实现第一芯片110与其他芯片或电路结构的电连接。第一焊垫130和外接焊垫120与第一芯片110中不同的电路结构电连接。外接焊垫120用于将第一芯片110和第二芯片200构成的堆叠体的电性引出，从而实现该堆叠体与其他具有电路结构的基板的电连接。
需要说明的是，第一焊垫130和外接焊垫120露出的位置利用介质层（未标示）进行保护以防止短路，且在第一晶圆100的制作过程中，通过对介质层进行刻蚀以暴露第一焊垫130和外接焊垫120，因此，第一焊垫130和外接焊垫120的表面低于第一表面，即第一表面形成有分别露出第一焊垫130和外接焊垫120的凹槽。
参考图6，本实施例还形成覆盖外接焊垫120的遮挡层150。
遮挡层150用于保护外接焊垫120，以免外接焊垫120暴露在形成第一导电凸块31的环境中，从而避免在外接焊垫120表面形成外接互连凸块，由于第一导电凸块31具有一定的体积，这相应能避免外接互连凸块与第一导电凸块31发生连接的问题，这降低了第一焊垫130和外接焊垫120发生电连接的概率，进而提高封装可靠性。例如，当采用电镀工艺形成填充于第一空隙11中的第一导电凸块31时，在电镀工艺过程中，遮挡层150能够防止在外接焊垫120的表面进行电镀，从而避免在外接焊垫120表面形成外接互连凸块，由于电镀工艺形成的电镀体均具有一定的体积，这相应能否避免外接互连凸块与第一导电凸块31发生连接的问题。
需要说明的是，在第一焊垫130表面进行电镀，因此，为了减小遮挡层150的形成对后续电镀工艺的影响，形成遮挡层150的工艺对第一焊垫130的损伤小。而且，后续还会去除遮挡层150，相应的，去除遮挡层150的工艺对第一焊垫130的损伤小，且能够保持第一焊垫130的表面平坦度，从而保证电镀工艺的可靠性。同理，后续去除遮挡层150时，对外接焊垫120的损伤较小，且能够保持外接焊垫120的表面平坦度，从而保证后续焊线22粘结可靠性。遮挡层150的材料满足：遮挡层150与第一焊垫130的刻蚀选择比大于10:1，遮挡层150与外接焊垫120的刻蚀选择比大于10:1。
形成遮挡层150前或后，形成键合层140，以用于后续将第二芯片200键合于第一晶圆100的第一表面上。
键合层140可选为可光刻的键合材料，粘结膜，金属介质层或聚合物材料，粘结膜如DAF膜（die attach film），有双面粘性的膜状材料，可以利用刻蚀或者激光烧蚀进行图形化；还可以是介质层，如硅的氧化物或氮化物，通过熔融键合连接芯片和晶圆；或聚合物材料。还可以是这些材料的组合。本实施例采用可光刻的键合材料，可以形成在第一晶圆100的表面，也可以形成在第二芯片200的表面，还可以在第一晶圆100以及第二芯片200上均形成。可光刻的键合材料包括膜状干膜或液态干膜，也可以包括其他光敏粘合材料。液态干膜指的是膜状干膜中的成分以液态的形式存在。另外，干膜是一种永久键合膜，粘结强度较高。膜状干膜可以通过贴膜的方式形成在第一晶圆100和/或第二芯片200上，液态干膜通过旋涂工艺涂布在第一晶圆100和/或第二芯片200上，之后对液态干膜进行固化处理。应当注意，在进行固化处理之后，需要对干膜进行图形化工艺，以暴露第一晶圆100的第一焊垫130和第二芯片200上的第二焊垫，通过干膜键合第一晶圆100和第二芯片200，一方面干膜是可光刻材料，可以通过半导体工艺形成所需的图案样式，工艺简单且与半导体工艺兼容，可批量化生产。而且干膜的弹性模量比较小，在受到热应力时可以很容易变形而不至于破损，减小第一晶圆100和第二芯片200的结合应力。
可光刻键合材料的厚度为5-200μm，如15μm、30μm、80μm、150μm等。既满足了电镀液容易进入空隙进行电镀，也避免了空隙高度太高而导致电镀时间长的问题，从而兼顾了电镀效率与电镀的良率。另外，可光刻键合材料在第一晶圆100表面方向上的投影至少覆盖第二芯片面积的10%。形成较大面积的可光刻键合材料，尤其将可光刻键合材料形成在后期工艺中覆盖层不容易填充的位置。本方案的可光刻的键合材料不但起到粘合的作用，还起到了提前密封的作用，可光刻的键合材料和后续工艺中的覆盖层共同起到密封第一芯片110的作用。可选方案中，可光刻的键合材料覆盖第一芯片110的全部下表面（除第一焊垫130、第二焊垫所在的区域），这样，在后续工艺形成覆盖层时，保证第一芯片110下方没有空隙，提高结合强度，提高成品率。
为便于后续电镀时外部电镀液体流入空隙，空隙设为非封闭，可光刻键合材料留有连通空隙流体通道。如光刻键合材料包围第一焊垫130或第二焊垫210，但留有流体通道将空隙连通到芯片边缘，流体通道可以贯穿光刻键合材料，也可以不贯穿光刻键合材料；或者光刻键合材料未包围或未完全包围第一焊垫130或第二焊垫210，未包围的部分与外界连通作为流体通道。其他实施例中，空隙连通外部，也可以作为一种流体通道；可选的在第一晶圆100的相邻第一芯片110之间的可光刻键合材料中留有通道，通道连通外部，该通道延伸至第一焊垫130和第二焊垫210形成的空隙，这样使得外部镀液通过通道流至空隙，形成导电凸块。在一种可能的实现方式中，可光刻键合材料覆盖后续形成的导电凸块外围的区域，即定义导电凸块的形成位置，也就是说可光刻键合材料围成了空隙的边界，后续导电凸块不能超越该边界，方便进行电镀工艺的控制，防止形成的导电凸块横向外溢。由于，第一晶圆100与第二芯片200之间通过可光刻键合材料实现物理连接，而且可光刻键合材料覆盖导电凸块外围的区域，直接增强了整个结构的机械强度，可以省去现有技术的充填灌胶工艺。若后续还进行塑封工艺，塑封材料无需填充第一芯片110与第二芯片200之间的间隙，从而节省了塑封工艺的时间。
参考图6，形成第一导电凸块31后，去除遮挡层150。
去除遮挡层150，露出外接焊垫120，从而为后续实现外接焊垫120与其他基板、芯片或互连结构的电连接做准备。
本实施例中，根据遮挡层150的材料，去除遮挡层150的工艺包括等离子体氧化工艺和等离子体氮化工艺中的一种或两种，与刻蚀工艺相比，通过在含氧气体（例如，氧气）或含氮气体（例如，氮气）条件下的气化方式去除遮挡层150，不容易损伤外接焊垫120，能够保持外接焊垫120的表面平坦度，从而保证后续焊线粘结可靠性。本实施例中，遮挡层150的材料为含碳介质，因此，采用等离子体氧化工艺去除遮挡层150。等离子体氧化工艺采用的含氧气体（例如，氧气）能够将含碳介质氧化为二氧化碳，从而将反应副产物直接排除反应腔室，因此，对电极的损伤较小，而且，还有利于降低产生遮挡层150残留或反应副产物的概率。在其他实施例中，当遮挡层150的材料为聚酰亚胺时，则采用等离子体氧化工艺，去除遮挡层150。聚酰亚胺为有机材料，因此，聚酰亚胺层的去除工艺对第一焊垫130和外接焊垫120的损伤较小。含碳介质能够与气相刻蚀剂相反应以形成气体，去除含碳介质的工艺对第一焊垫130和外接焊垫120的损伤也较小。作为一种示例，含碳介质可以包括非晶碳。
参考图7，形成第一导电凸块31后且去除遮挡层150后，切割第一晶圆100形成芯片模块（未标示），芯片模块包括键合在一起的第二芯片200和第一芯片110。
切割第一晶圆100后，第二芯片200与相对应的第一芯片110构成独立的芯片模块，从而为后续将芯片模块固定至其他基板上做准备。第一晶圆100中通常设有纵横交错的切割道（scribe line），且该切割道设置于第一晶圆100上任意相邻的两个第一芯片110之间，因此，沿切割道对第一晶圆100进行切割。本实施例中，先从第一表面对第一芯片110之间的第一晶圆100进行部分刻蚀，形成沟槽（图未示），然后对第二表面进行背面减薄处理，以暴露出沟槽，从而将各个第一芯片110分离。由于刻蚀工艺具有范围较宽的工艺窗口，因此能够刻蚀出较窄的切割道，从而能够降低第二芯片200和第一导电凸块31受损的概率，也能够改善第一芯片110的崩边现象，降低第一芯片110内部的有效电路受损的概率，从而有利于获得完好的独立堆叠体，进而有利于提高封装可靠性。而且，对第二表面进行背面减薄处理，可实现更轻、更薄以及体积更小的晶圆级芯片封装。在其他实施例中，也可以采用激光切割的方式或者机械切割的方式进行切割。
参考图8，切割第一晶圆100后，将芯片模块粘接至基板1上，基板1中具有电路结构2。
通过将第一芯片110的第二表面粘接至基板1上，从而为后续的打线工艺做准备，以便于利用基板1中的电路结构2向由第一芯片110和第二芯片200构成的堆叠体提供电路信号，或者，利用基板1中的电路结构2实现该堆叠体与其他芯片或其他基板的电连接。本实施例中，基板11可以为PCB板（printed circuit board，印刷电路板）。在其他实施例中，基板1也可以为FPC板（flexible printed circuit board，柔性电路板）或转接（interposer）板等其他类型的基板1。本实施例中，通过粘合层3将第二表面粘接至基板1上。作为一种示例，粘合层3可以为粘片膜。
继续参考图8，利用打线（wire bond）工艺形成焊线22，焊线22电连接外接焊垫120与基板1中的电路结构2。
需要说明的是，在本实施例中，外接焊垫120形成有遮挡层150，在形成第一导电凸块31之后，切割第一晶圆100之前，需要去除遮挡层150，从而能够同时去除各个外接焊垫120上的遮挡层150，进而提高封装效率。在其他实施例中，根据工艺需求，也可以在将第一芯片110的第二表面粘接至基板1上后，去除遮挡层150，从而降低外接焊垫120被氧化的概率，进而有利于提高后续打线（wire bond）工艺的可靠性。去除遮挡层150之后，再利用打线工艺形成焊线22。焊线22使得外接焊垫120与电路结构2实现电连接，从而实现由第一芯片110和第二芯片200构成的独立芯片模块和基板1的系统集成。
继续参考图8，形成焊线22后，封装方法还包括：形成至少覆盖第一导电凸块31和焊线22的覆盖层250。
覆盖层250对第一芯片110和第二芯片200起到固定作用，用于使第一芯片110和第二芯片200实现封装集成。而且，覆盖层250用于实现对第一导电凸块31和焊线22的绝缘、密封以及保护。
本实施例中，焊线22的最高处低于第二芯片200背向第一芯片110的表面。通过使焊线22的最高处低于第二芯片200背向第一芯片110的表面，能够将第一导电凸块31和焊线22均掩埋在覆盖层250中，同时，易于使得封装结构的厚度较小。在其他实施例中，焊线22的最高处也可以和第二芯片200背向芯片的表面齐平。本实施例中，覆盖层250还覆盖第二芯片200背向第一芯片110的表面，从而将第二芯片200、第一芯片110、第一导电凸块31和焊线22均掩埋在内，进而有利于提高封装可靠性。在其他实施例中，覆盖层250的顶面也可以和第二芯片200背向第一芯片110的表面齐平，或者，覆盖层250覆盖第二芯片200的部分侧壁。
覆盖层的材料等相关内容请参考实施例一，此处不做赘述。
实施例三
参考图9，本实施例与实施例二的区别之处在于：在第二芯片与第一晶圆键合后，形成填充于第一空隙11中的第一导电凸块31时，还形成凸出于外接焊垫120表面的电镀互连凸块45。
电镀互连凸块45将第一芯片110的电性引出，从而为后续的封装制程做准备。例如，能够通过电镀互连凸块45，实现第一芯片110与其他基板（例如，电路板）的电连接。
在本实施例中，受到第一晶圆100的制造工艺的影响，外接焊垫120的表面通常低于第一芯片110的第一表面，因此，通过电镀互连凸块45将外接焊垫120的电性引出，电镀互连凸块45凸出于外接焊垫120的表面，这易于后续打线工艺的进行，焊线与电镀互连凸块45的连接性能更高，从而有利于提高封装可靠性；此外，在形成电镀第一导电凸块31的同时，形成电镀互连凸块45，这有利于提高封装效率。综上，本实施例能够在实现晶圆级封装的同时，提高封装效率和封装可靠性。本实施例中，电镀互连凸块45的上表面为平坦面，从而保证后续焊线粘结可靠性。
实施例四
参考图10，本实施例与实施例三的区别之处在于：在第一晶圆100上除了第二芯片200外，还可以设置互连芯片300，该互连芯片300可以是连接件的一种，互连芯片300包括相对的第三表面和第四表面，互连芯片300中形成有互连结构305，互连芯片300的第三表面和第四表面分别暴露部分互连结构305，互连结构305包括插塞、与插塞连接的互连线、以及互连焊垫，互连焊垫为互连芯片300的第四表面暴露的部分；将互连芯片300也键合于第一晶圆100第一表面上，可与第二芯片200平行设置。互连结构305的第四表面朝向第一晶圆100。第一晶圆100在与互连焊垫相对位置，可以设有外接焊垫120，形成与第二芯片200相同的空隙，在第一空隙11形成第一导电凸块31的同时，在互连结构305与第一晶圆100之间的空隙中形成电镀互连凸块45与第一晶圆100互连。互连结构305也可采用其他方式，如植球与第一晶圆100电连接。另外互连结构305可以不与第一晶圆100电连接，而通过键合层140与第一晶圆100物理连接。第三表面的互连结构305，可以通过设置金互连线与第二芯片200反面进行互连，例如实现将第二芯片200电性正反面的互连，还可以作为与外部电路连接的端口，避免在第一晶圆100第二表面引出电性，实现第二芯片200或者第一晶圆100与外界的电性连接。互连芯片300能够将第二芯片200或者外部电路的引出端（如I/O端）引至第一晶圆100具有第一焊垫130和外接焊垫120一侧，后续能灵活连接系统级封装中各位置处的芯片或器件或外接电路，减少对第二芯片200或者器件晶圆的操作（例如，进行背面减薄处理或者硅通孔互连工艺），从而减小对第二芯片200和器件晶圆的损伤，有利于提高封装可靠性，而且，使封装方法适用于各种晶圆的系统集成，相应提高封装兼容性。
实施例五
参考图11，与实施例一不同之处在于：与第一晶圆100键合连接的是封盖700，封盖700中形成有互连结构，互连结构包括第二焊垫210；利用键合层140将封盖700键合于第一晶圆100。
封盖700作为晶圆级封装的待集成结构的一部分，其中形成有互连结构，在实现对第一晶圆100的封装的同时改变第一焊垫130在晶圆平面的位置。封盖700采用集成电路制作技术所制成，第二焊垫210位于封盖700的第一表面，即第二焊垫210被裸露。
封盖700可以包括衬底710，本实施例中，衬底的材料参考实施例一。在其他实施例中，封盖700也可以不包括衬底710，仅包括形成有互连结构305的介质层730。本实施例中，封盖700通过以下步骤获取：提供衬底710；在衬底710上形成释放层720，释放层720覆盖衬底710；在释放层720上形成介质层730，在介质层730中形成互连结构305。在其他实施例中，形成封盖700的步骤还可以包括，在介质层730中形成互连结构305之后，释放释放层720，去除衬底710。即封盖700为仅包括形成有互连结构305的介质层730。衬底710为封盖700的互连结构的制作提供支撑。对封盖700的衬底710的描述，可结合参考前述的相关描述，在此不再赘述。释放层720为衬底710的去除提供方便，本实施例中，释放层720为锗释放层；在其他实施例中，释放层720材料为碳和热解膜中的至少一种；当衬底710为透光玻璃时，释放层720材料还可以为光解膜。介质层730提供了互连结构305的成型空间，如图10所示，首先在释放层720上沉积一层介质材料层，然后在介质材料层的对应位置进行刻蚀和填充，形成互连结构。本实施例中，介质层730的材料为高阻硅，互连结构的材料为铜，铜的电阻率较低，通过选取铜材料，有利于提高互连结构的导电性能；而且，互连结构形成于互连结构孔中，铜的填充性较好，从而提高互连结构在互连结构孔内的形成质量。在其他实施例中，介质层730的材料还可以为其他具有较高电阻的材料，而互连结构的材料也可以为其他可适用的导电材料，比如：镍、锌、锡、金、钨、镁。
容易理解的是，为实现互连，互连结构还包括与第二焊垫210电连接的第三焊垫220，第三焊垫220与第二焊垫210分别位于封盖700相对的两个表面。本实施例中，如图11所示，封盖700包括衬底710和释放层720，第三焊垫220与第二焊垫210分别位于封盖700相对的两个表面是指互连结构可以包括位于介质层730的第一表面的第二焊垫210，位于介质层730的第二表面的第三焊垫220，当然，其中还可以包括电连接第二焊垫210和第三焊垫220的插塞，包括再布线层（redistribution layer，RDL）结构（图中未示出），介质层730的第一表面与介质层730的第二表面相对。在其他实施例中，封盖700仅包括形成有互连结构305的介质层，那么第三焊垫220与第二焊垫210分别位于介质层730的两个相对的表面，即分别位于封盖700相对的两个表面。为减小第一晶圆100级封装后的封装结构的厚度，在完成互连结构305的加工或者第一晶圆100级封装后，可以进行减薄处理。而在衬底710上先形成释放层720，再在释放层720上形成介质层730，一方面，衬底710可以为互连结构305的加工提供支撑，或者同时为封盖700和第一晶圆100的键合提供支撑；另一方面，释放层720的存在，可以在完成互连结构305的加工，或者完成封盖700与第一晶圆100的键合后，通过释放层720的释放去除衬底710，提高衬底710去除的方便性，还可以实现衬底710去除的准确控制，避免由于通过磨削的方式去除衬底710时所造成的厚度控制准确度较低对器件所造成的损伤，提高产品的成品率。在其他实施例中，也可以直接在衬底710上形成介质层730，进而形成互连结构。在其他实施例中，还可以通过在第三焊垫220上植球形成导电块，用于与外部电路实现电连。
封盖700可以为晶圆级封盖700，即封盖700具有晶圆大小，则封盖700的互连结构的数量与第一晶圆100的第一焊垫130的数量相同。当封盖700为晶圆级封盖700时，通过一次键合既可以实现晶圆级的封装，可以简化处理工艺，提高封装速度。在其他实施例中，封盖700可以为芯片级封盖，则本文的提供封盖700包括提供多个芯片级封盖，芯片级封盖的数量可以与第一晶圆100的第一芯片110的数量相同，也可以与第一晶圆100的第一芯片110的数量不同，当然，每个芯片级封盖的第二焊垫210的数量与每个第一芯片110的第一焊垫130的数量相同。
当第一晶圆100的各个第一芯片110的结构相同时，各个芯片级封盖的结构可以相同，也可以在保证后续键合以及封装要求的基础上有所不同；当第一晶圆100的各个第一芯片110的结构相同时，可以选择具有不同结构的芯片级封盖，以实现不同第一芯片110的转接互连。可以通过对晶圆级封盖进行切割的方式，获得多个分立的芯片级封盖。
参考图12和图13,键合封盖700与第一晶圆100，并切割形成开口后，释放释放层720，去除衬底710。形成第一导电凸块31后，在第三焊垫上形成导电块740。在完成封盖700与第一晶圆100的键合后再释放释放层720，可以降低对于封盖700的介质层730的厚度要求，降低键合难度。首先形成开口再释放释放层720，可以扩大释放层720的刻蚀面积或者受热面积，提高释放层720去除的速度，提高加工效率。
如前，本实施例中，衬底710为硅衬底，释放层720为锗释放层；可以通过湿法刻蚀工艺，刻蚀释放层720，实现释放层720和衬底710的去除。在其他实施例中，当释放层720的材料为热解膜时，可以通过加热的方式实现释放层720和衬底710的去除，当释放层720的材料为光解膜时，且衬底710为透光的玻璃时，可以通过光照的方式实现释放层720和衬底710的去除。当然，在另一种具体实施方式中，还可以首先进行释放层720和衬底710的去除，再切割形成开口。
实施例六
参考图14，与实施例二不同之处在于，在第二芯片200上设置第三焊垫220，在第二芯片200上键合第三芯片400，第三芯片400通过电镀工艺或植球工艺连接第三焊垫220。图中所示第三芯片400是采用电镀工艺连接第三焊垫220，可以于第一芯片110第二芯片200连接的电镀工艺同时做，可以节省制程，高效完成芯片堆叠的电连接。第三芯片400可以先通过键合层140连接在第二芯片200的背面，将第二芯片200的第三焊垫220与第三芯片400的第四焊垫410相对，形成空隙，后续再形成电镀的第二导电凸块312。第三芯片400还可以在第一芯片110和第二芯片200通过第一导电凸块31电连接后，通过植球工艺键合在第二芯片200上，可以没有键合层140材料，图中未示出。   
参考图15，在另一实施例中，第一晶圆100的背面键合第四芯片500，具体地，第一晶圆100的背面形成第五焊垫，包括：通过电镀工艺，在第五焊垫上形成第三导电凸块，用于电连第一晶圆100与第四芯片500。
参考图16，在另一实施例中，可以是在第一晶圆100正面的第二芯片200上键合第三芯片400、背面键合第四芯片500，第二芯片200上的第二焊垫210与第一晶圆100正面的第一焊垫130之间形成第一空隙11，第二芯片200与第一芯片110之间形成第二空隙，背面第四芯片500上的焊垫与第一晶圆100背面的焊垫之间形成第三空隙，进行电镀工艺时，同时在正面的第二芯片200与第一晶圆100之间、第三芯片400与第二芯片200之间以及背面的第四芯片500与第一晶圆100之间形成导电凸块。正面和背面的导电凸块形成的电镀工艺可以同时进行，也可以分别进行；也可以先进行第一晶圆100正面的键合工艺，之后进行背面的电镀工艺。
其中，第二焊垫210与第三焊垫220之间通过TSV互连，但本实施例中，不限于此种情形，第二焊垫210与第三焊垫220之间可以通过其他的互连方式实现电连接，比如第二焊垫210与相应的第三焊垫220之间通过互连线和插塞实现电连接。
本发明的实施例一至实施例六阐述了各种具体的情形，其中实施例一至实施例六阐述的各种情形可以根据需要进行相应的组合形成新的实施例。在本发明中不做一一阐述，本领域技术人员根据本发明的教导可以得出不同于实施例一至实施例七所列情形的具体实施例。
实施例七
参考图2，本发明公开一种晶圆级系统封装结构，第一晶圆100，包含多个第一芯片110，第一芯片110包括相对的第一表面和第二表面，第一表面具有裸露的且相间隔的第一焊垫130；多个第二芯片200，第二芯片200的表面具有裸露的第二焊垫210；键合层将第二芯片200键合于第一晶圆100的第一表面上，第二焊垫210和第一焊垫130上下相对，第一焊垫130和第二焊垫210包括正对部分和错开部分；电镀工艺形成的第一导电凸块31，连接第二焊垫210和第一焊垫130。
具体地，第一晶圆100的表面形成有露出第一焊垫130的第一介质层160，第二芯片200朝向第一晶圆100的表面上还形成有露出第二焊垫210的第二介质层260，第一介质层160和第二介质层260的材料及作用参考前述。第一晶圆100为包含第一芯片110的晶圆或者包含第一芯片110的单颗芯片，第一芯片110有相对的第一表面和第二表面，在第一芯片110的第一表面键合第二芯片200。第二芯片200表面具有裸露的第二焊垫210，第二焊垫210和第一焊垫130的位置关系及其它相关内容具体参考前述实施例。焊垫、第一导电凸块31的相关内容参考前述实施例，这里不再赘述。
参考图6，在一实施例中，第二芯片200的表面具有裸露的且与第一焊垫相间隔的外接焊垫120，外接焊垫的相关内容参考前述。
参考图9，在一实施例中，还形成有电镀互连凸块45，凸出于外接焊垫120表面，电镀互连凸块45的作用及相关描述参考前述。
参考图14，在一实施例中，第二芯片200上设置有第三焊垫220，第二芯片200上键合有第三芯片400，第三芯片400含有第四焊垫410，第三焊垫220与第四焊垫410之间通过电镀工艺形成的第二导电凸块312电连。
参考图15，在一实施例中，第一晶圆100与第二芯片200相对的另一面形成有第五焊垫，还包括：通过电镀工艺，在第五焊垫上形成导电凸块。
本实施例的其它内容参考前述，此处不做过多赘述。
实施例八
参考图11至图13，本实施例与实施例七不同之处在于：本实施例与第一晶圆100键合连接的是封盖700，封盖700中形成有互连结构，互连结构包括第二焊垫210；利用键合层140将封盖700键合于第一晶圆100。
封盖及本实施例的其它相关内容参考实施例五，此处不做过多赘述。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (22)

  1. 一种晶圆级系统封装方法，其特征在于，包括：提供第一晶圆，所述第一晶圆中形成有多个第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一芯片的第一表面具有裸露的第一焊垫；提供封盖或多个第二芯片，所述第二芯片或封盖的表面具有裸露的第二焊垫；利用键合层将所述第二芯片或封盖键合于所述第一晶圆，所述第二焊垫和第一焊垫上下相对，围成第一空隙；相对的所述第一焊垫和第二焊垫包括正对部分和错开部分；通过电镀工艺，在所述第一空隙中形成使所述第一焊垫和第二焊垫电连接的第一导电凸块。
  2. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，该封装方法还包括：所述第一芯片的第一表面还具有裸露的且与所述第一焊垫相间隔的外接焊垫；所述正对部分的面积大于所述第一焊垫面积或所述第二焊垫面积的二分之一，且所述第二芯片露出所述外接焊垫。
  3. 根据权利要求2所述的晶圆级系统封装方法，其特征在于，该封装方法还包括：形成覆盖所述外接焊垫的遮挡层；形成所述第一导电凸块后，去除所述遮挡层。
  4. 根据权利要求2所述的晶圆级系统封装方法，其特征在于，在形成第一导电凸块时，还形成凸出于所述外接焊垫表面的电镀互连凸块。
  5. 根据权利要求4所述的晶圆级系统封装方法，其特征在于，形成所述电镀第一导电凸块和电镀互连凸块后，所述晶圆级封装方法还包括：切割所述第一晶圆形成芯片模块，所述芯片模块包括键合在一起的所述第二芯片和所述第一芯片；切割所述第一晶圆后，所述晶圆级封装方法还包括：将所述第一芯片的第二表面粘接至基板上，所述基板中具有电路结构；利用打线工艺形成焊线，所述焊线电连接所述电镀互连凸块与所述基板中的电路结构。
  6. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，该封装方法还包括：
    所述封盖中形成有互连结构，所述互连结构包括所述第二焊垫；所述互连结构还包括与所述第二焊垫电连接的第三焊垫，所述第三焊垫与所述第二焊垫分别位于所述封盖相对的两个表面，所述第三焊垫通过电镀工艺或植球工艺形成第二导电凸块。
  7. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，所述封盖包括晶圆级封盖或芯片级封盖；所述封盖的形成步骤包括：提供衬底；在所述衬底上形成释放层，所述释放层覆盖所述衬底；在所述释放层上形成介质层，在所述介质层中形成互连结构；在所述介质层中形成所述互连结构的步骤之后，还包括：释放所述释放层，去除所述衬底。
  8. 根据权利要求4所述的晶圆级系统封装方法，其特征在于，提供多个互连芯片，所述互连芯片包括相对的第三表面和第四表面，所述互连芯片中形成有互连结构，所述互连芯片的第三表面暴露部分所述互连结构；将所述第二芯片和所述互连芯片键合于所述第一芯片的第一表面上。
  9. 根据权利要求8所述的晶圆级系统封装方法，其特征在于，该封装方法还包括：所述互连结构包括插塞，所述插塞为所述互连芯片的第三表面暴露的部分；或者，所述互连结构包括插塞、与所述插塞连接的互连线、以及互连焊垫；所述互连芯片通过所述电镀互连块与所述第一芯片电连接。
  10. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，通过熔融键合、干膜键合、黏着键合或玻璃介质键合，使所述第二芯片或所述封盖键合于所述第一晶圆。
  11. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，所述键合层的材料为可光刻的键合材料、粘结膜、金属，介质层或聚合物材料的一种或组合。
  12. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，所述第一空隙的高度为5um-200um；所述第一焊垫或所述第二焊垫的暴露出面积为5-200平方微米；和/或，所述第一导电凸块的横截面积大于10平方微米。
  13. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，对焊垫的表面进行清洁，去除焊垫表面的自然氧化层，和/或进行活化工艺。
  14. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，所述第二芯片于第一晶圆相对的的另一面形成有第三焊垫，所述方法还包括：在所述第二芯片上键合第三芯片，所述第三芯片含有第四焊垫，所述第三焊垫与所述第四焊垫之间形成第二空隙；通过电镀工艺在所述第二空隙形成第二导电凸块；或者，所述第一晶圆与第二芯片相对的另一面形成有第五焊垫，所述方法还包括：通过电镀工艺，在所述第五焊垫上形成第三导电凸块。
  15. 根据权利1所述的晶圆级系统封装方法，其特征在于，通过可光刻键合层实现第二芯片或封盖和第一晶圆的键合，所述可光刻键合材料避开焊垫设置；所述可光刻键合材料覆盖所述第一导电凸块外围的区域；所述可光刻键合材料的厚度为5-200μm，所述可光刻键合材料至少覆盖所述第二芯片面积的10%。
  16. 根据权利要求1所述的晶圆级系统封装方法，其特征在于，对焊垫的表面进行清洁，去除焊垫表面的自然氧化层，和/或进行活化工艺。
  17. 一种晶圆级系统封装结构，其特征在于，包括：第一晶圆，包含多个第一芯片，所述第一芯片包括相对的第一表面和第二表面，所述第一表面具有裸露的且相间隔的第一焊垫；封盖或多个第二芯片，所述封盖或所述第二芯片的表面具有裸露的第二焊垫；键合层，将所述第二芯片或封盖键合于所述第一晶圆的第一表面上，所述第二焊垫和第一焊垫上下相对，所述第一焊垫和所述第二焊垫包括正对部分和错开部分；电镀工艺形成的第一导电凸块，连接所述第二焊垫和所述第一焊垫。
  18. 根据权利要求17所述的晶圆级系统封装结构，其特征在于，还包括：所述第一芯片的第一表面还具有裸露的且与所述第一焊垫相间隔的外接焊垫；所述正对部分的面积大于所述第一焊垫面积或所述第二焊垫面积的二分之一，且所述第二芯片露出所述外接焊垫。
  19. 根据权利要求18所述的晶圆级系统封装结构，其特征在于，还包括：电镀互连凸块，凸出于所述外接焊垫表面。
  20. 根据权利要求17所述的晶圆级系统封装结构，其特征在于，封盖中形成有互连结构，所述互连结构包括所述第二焊垫。
  21. 根据权利要求17所述的晶圆级系统封装结构，其特征在于，所述第二芯片于第一晶圆相对的的另一面形成有第三焊垫，还包括：在所述第二芯片上键合第三芯片，所述第三芯片含有第四焊垫，所述第三焊垫与所述第四焊垫之间通过电镀工艺形成的第二导电凸块电连接；或者，所述第一晶圆与第二芯片相对的另一面形成有第五焊垫，还包括：通过电镀工艺，在所述第五焊垫上形成第三导电凸块。
  22. 根据权利要求17所述的晶圆级系统封装结构，其特征在于，所述键合层包括可光刻键合材料，所述可光刻键合材料的厚度为5-200μm，所述可光刻键合材料至少覆盖所述第二芯片面积的10%；所述第一导电凸块的横截面积大于10平方微米。
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