CN110060935B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN110060935B CN110060935B CN201810937666.8A CN201810937666A CN110060935B CN 110060935 B CN110060935 B CN 110060935B CN 201810937666 A CN201810937666 A CN 201810937666A CN 110060935 B CN110060935 B CN 110060935B
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Abstract
本发明的实施例提供了半导体器件和制造方法,从而将中介片和第一半导体器件放置在载体衬底上并且被密封。中介片包括第一部分和远离第一部分延伸的导电柱。位于密封剂的第一侧上的再分布层将导电柱电连接至第一半导体器件。
Description
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及半导体器件及其制造方法。
背景技术
由于各个电组件(例如,晶体管、二极管、电阻器、电容器等)的集成度的持续改进,半导体工业已经经历了快速增长。在很大程度上,这种集成度的改进来自于最小特征尺寸的连续减小(例如,朝着亚20nm节点缩小半导体工艺节点),这允许更多的组件集成到给定的区域。随着最近对小型化、更高的速度和更大的带宽以及更低的功耗和延迟的需求增长,对半导体管芯的更小和更具创造性的封装技术的需求也增长。
随着半导体技术进一步发展,堆叠和接合的半导体器件作为有效可选方式出现以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中,各有源电路(诸如逻辑、存储器、处理器电路等)至少部分地在不同的衬底上制造,并且之后将这些有源电路物理和电接合在一起以形成功能器件。这种接合工艺利用复杂的技术,并且期望改进。
发明内容
根据本发明的一个方面,提供了一种制造半导体器件的方法,所述方法包括:将粘合层放置在载体上方;将第一半导体器件放置在所述载体上,所述第一半导体器件具有第一厚度;将第一衬底放置在所述载体上,所述第一衬底具有小于所述第一厚度的第二厚度,其中,导电柱与所述第一衬底物理接触;以及将密封剂与所述第一衬底、所述导电柱和所述第一半导体器件的每个均物理接触。
根据本发明的另一个方面,提供了一种制造半导体器件的方法,所述方法包括:形成具有导电布线的中介片;将导电柱镀至所述中介片上并且与所述导电布线电连接;去除所述中介片的部分以形成环件;将所述环件放置在第一载体衬底上;将第一半导体器件放置在所述第一载体衬底上,其中,在放置所述环件并且放置所述第一半导体器件之后,自顶向下看,所述环件围绕所述第一半导体器件;用密封剂填充所述第一半导体器件和所述环件之间的间隔,其中,在填充所述间隔之后,所述密封剂覆盖所述导电柱的侧壁;在所述密封剂的第一侧上方形成再分布层,其中,所述再分布层与所述导电柱和所述第一半导体器件的外部连接件物理接触;以及将第一封装件附接至所述密封剂的与所述第一侧相对的第二侧。
根据本发明的又一方面,提供了一种半导体器件,包括:半导体器件,嵌入在密封剂内;中介片,嵌入在所述密封剂内,其中,所述中介片具有第一部分和远离所述第一部分延伸的导电柱,所述导电柱具有倒锥形形状,所述第一部分具有小于所述半导体器件的第二厚度的第一厚度,所述中介片围绕所述半导体器件;再分布层,位于所述密封剂的第一侧上方,所述再分布层将所述导电柱电连接至所述半导体器件;以及第一封装件,位于所述密封剂中与所述再分布层相对的侧上,所述第一封装件通过所述中介片的第一部分和所述导电柱连接至所述半导体器件。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的载体上的粘合层和管芯附接膜的放置。
图2示出了根据一些实施例的第一半导体器件。
图3A至图3E示出了根据一些实施例的环件的形成。
图4示出了根据一些实施例的第一半导体器件和环件在载体上的放置。
图5示出了根据一些实施例的半导体器件和环件的密封。
图6示出了根据一些实施例的密封剂的平坦化。
图7示出了根据一些实施例的再分布层的形成。
图8示出了根据一些实施例的外部连接件的形成。
图9示出了根据一些实施例的载体的去除。
图10示出了根据一些实施例的粘合层的图案化。
图11示出了根据一些实施例的第一封装件的接合。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“且,为便于描述,在此可”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
将参照沿着背侧再分布层具有嵌入式通孔中介片的异质扇出结构来描述实施例。然而,实施例不限于特定描述的实施例,并且可以用于一系列实施例。
现在参照图1,图1示出了第一载体衬底101,其中,粘合层103和管芯附接膜105位于第一载体衬底101上方。第一载体衬底101包括例如诸如玻璃或氧化硅的硅基材料或诸如氧化铝的其它材料、任何这些材料的组合等。第一载体衬底101是平坦的以适应诸如第一半导体器件201和环件301(也称为中介片,未在图1中示出,但下面参照图2至图3D示出和讨论)的半导体器件的附接。
粘合层103置于第一载体衬底101上以帮助上面的结构(例如,第一管芯附接膜105)的粘合。在实施例中,粘合层103可以包括光热转换(LTHC)材料或紫外胶,但是也可以使用其它类型的粘合剂,诸如压敏粘合剂、辐射可固化粘合剂、环氧树脂、这些的组合等。粘合层103可以以半液体或凝胶形式置于第一载体衬底101上,这在压力下容易变形。
第一管芯附接膜105可以置于粘合层103上以帮助第一半导体器件201和环件301附接至粘合层103。在实施例中,第一管芯附接膜105是环氧树脂、酚醛树脂、丙烯酸橡胶、硅胶填料或它们的组合,并且使用层压技术来施加。然而,可选择利用任何合适的可选的材料和形成方法。
图2示出了将附接至第一管芯附接膜105的第一半导体器件201。在实施例中,第一半导体器件201是包括逻辑区域和具有例如非易失性存储器(NVM)单元的存储区域的片上系统。逻辑区域可以包括电路,诸如晶体管,以处理从非易失性存储器单元接收的信息并且控制NVM单元的读取和写入功能。在一些实施例中,NVM单元可以是电阻式随机存取存储器(RRAM)单元、相变随机存取存储器(PCRAM)单元、磁阻式随机存取存储器(MRAM)单元或基于晶体管的随机存取存储器(诸如闪存或静态随机存取存储器(SRAM))。NVM单元可以用于保存二进制数据片或数据位。根据存储器单元的类型,每个NVM单元均可以包括一对金属绝缘体金属(MiM)结构。每个MiM结构均可以包括底电极和顶电极,其中,介电层夹置在两个电极之间。
第一半导体器件201也包括浅沟槽隔离(STI)部件以及多个金属化层和通孔。在实施例中,第一半导体器件201使用五个金属化层以及五个金属化通孔或互连层来制造。其它实施例可以包含更多或更少的金属化层以及对应的更多或更少数量的通孔。逻辑区包括完整的金属化堆叠件,其中包括每个金属化层中通过互连件连接的部分,同时一些通孔将堆叠件连接至逻辑晶体管的源极/漏极接触件。NVM单元包括将MiM结构连接至存储器单元晶体管的完整的金属化堆叠件。也包括在第一半导体器件201中的是多个金属间介电(IMD)层。额外的IMD层可以跨越逻辑区和存储器单元区。IMD层可以在许多制造工艺步骤期间为第一半导体器件201的各个部件提供电绝缘以及结构支撑,其中的一些工艺步骤将在本文中讨论。
在实施例中,第一半导体器件201可以使用沉积工艺、蚀刻工艺、平坦化工艺、这些的组合等来形成,并且可以形成为具有适合于第一半导体器件201的预期用途的第一高度H1。例如,在第一半导体器件201将要用于移动应用(诸如用于蜂窝手机)的实施例中,第一高度H1可以介于约50μm和约600μm之间,诸如约150μm。然而,可以利用任何合适的尺寸。
图2也示出了第一外部连接件203,第一外部连接件203可以形成为提供用于金属化层和例如再分布层(RDL)701(未在图2中示出但下面参照图7示出和描述)之间的接触件的导电区域。在实施例中,第一外部连接件203可以是导电柱,并且可以通过首先形成厚度介于约5μm至约20μm之间(诸如约10μm)的光刻胶(未示出)来形成。光刻胶可以在导电柱将延伸的地方被图案化。一旦图案化,则之后光刻胶可以用作掩模,并且可以在光刻胶的开口内形成第一外部连接件203。第一外部连接件203可以由诸如铜的导电材料形成,但是也可以使用诸如诸如镍、金、焊料、金属合金、这些的组合等的其它导电材料。此外,可以使用诸如电镀的工艺形成第一外部连接件203,通过诸如电镀的工艺,电流流经金属化层的期望形成第一外部连接件203的导电部分或单独的晶种层(未在图2中单独示出),并且金属化层或晶种层浸没在溶液中。溶液和电流将例如铜沉积在开口内,以填充和/或过填充光刻胶的开口,从而形成第一外部连接件203。之后,可以使用例如灰化工艺、化学机械抛光(CMP)工艺、这些的组合等来去除开口外的过量的导电材料和光刻胶。
然而,本领域普通技术人员将意识到,用于形成第一外部连接件203的上述工艺仅仅是一种描述,而不旨在将该实施例限制于该具体工艺。而且,所描述的工艺仅仅旨在说明,并且可以可选地利用用于形成第一外部连接件203的任何合适的工艺。所有合适的工艺均完全地旨在包括在本实施例的范围内。
可选地,一旦已经形成第一外部连接件203,则可以在第一外部连接件203上方形成第一保护层205,以提供支撑和保护。在实施例中,第一保护层205可以是保护材料,诸如聚苯并恶唑(PBO)或聚酰亚胺(PI)、氧化硅、氮化硅、氮氧化硅、苯并环丁烯(BCB),或任何其它合适的的保护材料。第一保护层205可以使用诸如旋涂工艺、沉积工艺(例如,化学汽相沉积)或基于所选材料的其它合适工艺的方法来形成,并且可以形成为厚度介于约1μm和约100μm之间,诸如约20μm。
此外,虽然第一半导体器件201示出为单个片上系统,但这仅仅旨在说明,并不旨在限制实施例。例如,第一半导体器件201也可以包括任何合适的半导体器件,诸如单个半导体管芯或多个半导体管芯的组合。任何合适的器件均可以用于第一半导体器件201,并且所有这种实施例均完全地旨在包括在实施例的范围内。
图3A至图3C示出了也将附接至第一管芯附接膜105的环件301的形成。在实施例中,可以通过在第二载体衬底305上形成聚合物层303来开始该工艺。聚合物层303置于可选粘合层(未单独示出)上方并且用于为上面的各层提供保护。在实施例中,聚合物层303可以是聚苯并恶唑(PBO),但是也可以利用诸如聚酰亚胺或聚酰亚胺衍生物、预浸料(PP)材料(诸如玻璃纤维、树脂和填料)、味之素积层膜(ABF)、这些的组合等的任何合适的材料。可以使用例如旋涂工艺将聚合物层303置为介于约0.5μm和约10μm之间的厚度,诸如约5μm,但是可以可选地使用任何合适的方法和厚度。
在聚合物层303上方形成晶种层(未单独示出)。在实施例中,晶种层是导电材料的薄层,它有助于在随后工艺步骤期间形成较厚的层。晶种层可以包括约厚的钛层以及随后的约/>厚的铜层。取决于期望的材料,可使用诸如物理汽相沉积、蒸发或PECVD工艺或金属箔层压工艺等来形成晶种层。晶种层可以形成为具有介于约0.3μm和约1μm之间(诸如约0.5μm)的厚度。
一旦已经形成晶种层,可以在晶种层上方放置并且图案化诸如干膜光刻胶的光刻胶。在实施例中,可以使用例如层压工艺或旋涂技术在晶种层上放置光刻胶至约80μm的高度。一旦位于适当的位置,则之后可以通过将光刻胶暴露于图案化的能量源(例如,图案化的光源)以引发化学反应,从而引发在光刻胶的暴露于图案化的光源的那些部分中的物理变化来图案化光刻胶。之后将显影剂施加至曝光的光刻胶以利用物理变化并且取决于期望的图案而选择性地去除光刻胶的曝光部分或者光刻胶的未曝光部分。在实施例中,形成为光刻胶的图案是用于第一金属化层307的图案。然而,可以可选地利用用于该图案的任何合适的布置。
在光刻胶内形成第一金属化层307。在实施例中,第一金属化层307包括诸如铜、钨、其它导电材料等的一种或多种导电材料,并且可以例如通过电镀、化学镀等形成。在实施例中,使用电镀工艺,其中,晶种层和光刻胶被淹没或浸没在电镀溶液中。晶种层表面电连接至外部DC电源的负极侧,从而使得晶种层在电镀工艺中用作阴极。诸如铜阳极的固体导电阳极也浸没在溶液中并且被附接至电源的正极侧。来自阳极的原子溶解在溶液中,而例如晶种层的阴极又从溶液中获取溶解的原子,从而对晶种层在光刻胶的开口内的暴露的导电区域进行镀敷。
一旦已经使用光刻胶和晶种层形成第一金属化层307,则可以使用合适的去除工艺去除光刻胶。在实施例中,可以使用等离子灰化工艺去除光刻胶,从而可以增加光刻胶的温度直至光刻胶经历热分解并且可以被去除。然而,可以可选地利用诸如湿剥离的任何其它适当的工艺。光刻胶的去除可以暴露下面的晶种层的部分。
一旦暴露,则可以实施晶种层的暴露部分的去除。在实施例中,可以通过例如湿蚀刻或干蚀刻工艺来去除晶种层的暴露部分(例如,未由第一金属化层307覆盖的那些部分)。例如,在干蚀刻工艺中,可以使用第一金属化层307作为掩模,将反应剂导向晶种层。在另一实施例中,蚀刻剂可以喷涂或以其它方式与晶种层接触以去除晶种层的暴露部分。
一旦已经形成第一金属化层307,则放置第一介电层309以帮助隔离第一金属化层307。在实施例中,第一介电层309可以是味之素积层膜(ABF),但是可以可选地利用诸如聚苯并恶唑(PBO)、聚酰亚胺、聚酰亚胺衍生物等的任何合适的材料。可以使用例如层压工艺或旋涂工艺(至少部分取决于所选材料)放置第一介电层309,但是可以可选地使用任何合适的方法。一旦位于适当的位置,则可以使用例如CMP工艺平坦化第一介电层309,以暴露第一金属化层307并且将厚度减小至约35μm。
图3B示出了第一通孔311、第二介电层315、第二金属化层313和第三介电层317的形成。在实施例中,第一通孔311、第二介电层315、第二金属化层313和第三介电层317每个均可以与上面参照第一金属化层307和第一介电层309描述的类似的方式形成。例如,第一通孔311和第二金属化层313的形成均可以:通过形成晶种层;置放和图案化光刻胶并且在光刻胶的开口内镀敷以形成第一通孔311和第二金属化层313。一旦已经形成第一通孔311和第二金属化层313,则它们可以分别由第二介电层315和第三介电层317覆盖。
在另一实施例中,第二介电层315和第三介电层317可以组合成一次施加的单个材料层。一旦施加,则可以实施先通孔双镶嵌工艺和后通孔双镶嵌工艺,从而使用例如光刻掩模和蚀刻工艺形成用于第一通孔311和第二金属化层313的开口,并且之后,导电材料填充进开口并且被平坦化以形成第一通孔311和第二金属化层313。
在形成第一通孔311的又一实施例中,可以将铜箔层压至第一介电层309上,并且之后可以将铜箔图案化成期望的设计。一旦已经图案化铜箔,则将第二介电层315放置在图案化的铜箔上方,并且使用例如激光钻孔工艺或光刻掩模和蚀刻工艺形成穿过第二介电层315开口,以暴露下面的铜箔。在可选的清洗工艺之后,可以使用化学镀工艺来填充开口并且将铜图案镀至第二介电层315上。之后可以施加并且平坦化第三介电层317。
此外,虽然已经描述了用于制造第一通孔311、第二介电层315、第二金属化层313和第三介电层317的多个实施例,但是这些实施例仅仅旨在说明并且不旨在限制。而且,可以利用用于形成第一通孔311、第二介电层315、第二金属化层313和第三介电层317的任何合适的方法,并且所有这些方法均旨在完全地包括在实施例的范围内。
图3C示出了在第三介电层317上方形成导电柱319和第四介电层321。在实施例中,第四介电层321可以与第三介电层317类似并且可以以类似的方式施加。例如,在实施例中,第四介电层321可以是使用层压工艺或旋涂工艺施加的诸如ABF或PBO的材料。然而,可以利用任何合适的材料或工艺。
一旦已经形成和/或放置第四介电层321,则可以在第四介电层321上方放置光刻胶(未在图3C中单独示出)。一旦位于适当的位置,则曝光并且显影光刻胶以形成穿过光刻胶的开口,其中,该开口为导电柱319的期望的形状。此外,在成像和显影以形成穿过光刻胶的开口期间,开口的侧壁可以形成为使得该侧壁不与下面的第四介电层321垂直。而且,该侧壁形成为与下面的第四介电层321成一定角度,从而使得开口延伸穿过光刻胶时,开口的形状为倒锥形形状。
一旦已经图案化光刻胶以将开口形成为导电柱319的期望的形状,则光刻胶可以用作掩模以去除第四介电层321的暴露部分并且暴露下面的第二金属化层313。在实施例中,使用例如将光刻胶用作掩模的各向异性蚀刻工艺(诸如反应离子蚀刻)实施第四介电层321的去除。然而,可以利用去除第四介电层321的暴露部分的任何合适的方法。
一旦已经暴露第二金属化层313,则在光刻胶内形成导电柱319。在实施例中,导电柱319包括诸如铜、钨、其它导电材料等的一种或多种导电材料,并且可以例如通过电镀、化学镀等形成。在实施例中,使用电镀工艺,其中,光刻胶被淹没或浸没在电镀溶液中。第二金属化层313或可选地沉积的晶种层(未单独示出,但在光刻胶的放置之前沉积)电连接至外部DC电源的负极侧,从而使得第二金属化层313或晶种层在电镀工艺中用作阴极。诸如铜阳极的固体导电阳极也浸没在溶液中并且被附接至电源的正极侧。来自阳极的原子溶解在溶液中,例如第二金属化层313或晶种层的阴极又从溶液中获取溶解的原子,从而对第二金属化层或晶种层在光刻胶的开口内的暴露的导电区进行镀敷。
一旦已经使用光刻胶和第二金属化层313或晶种层形成导电柱319,则可使用合适的去除工艺去除光刻胶。在实施例中,可以使用等离子灰化工艺去除光刻胶,从而可以增加光刻胶的温度直至光刻胶经历热分解并且可以被去除。然而,可以可选地利用诸如湿剥离的任何其它适当的工艺。光刻胶的去除可以暴露下面的晶种层的部分(如果存在)。
如果晶种层存在,一旦已经暴露晶种层,则可以去除晶种层的暴露部分。在实施例中,可以通过例如湿或干蚀刻工艺去除晶种层的暴露部分(例如,未由导电柱319覆盖的那些部分)。例如,在干蚀刻工艺中,使用导电柱319作为掩模,将反应剂导向晶种层。在另一实施例中,蚀刻剂可以用喷涂或其它方式与晶种层接触以去除晶种层的暴露部分。
此外,通过在导电柱319的形成期间利用穿过光刻胶的开口作为掩模,导电柱319将呈现穿过光刻胶的开口的形状。例如,在穿过光刻胶的开口具有倒锥形形状的实施例中,导电柱319也将呈现倒锥形的开口形状。因此,导电柱319可以在导电柱319的顶部处具有介于约50μm和约300μm之间(诸如约150μm)的第一柱宽度WP1,并且还可以在导电柱319的底部处具有小于第一柱宽度WP1的第二柱宽度WP2,诸如,介于约50μm和约300μm之间,诸如约100μm。此外,各导电柱319可以间隔开介于约160μm和约400μm之间(诸如约270μm)的第一节距P1。然而,可以利用任何合适的尺寸。
此外,一旦完成环件301的制造,则环件301可以形成为具有第二高度H2的第一部分(没有导电柱319),其中,第二高度H2小于第一半导体器件201的第一高度H1(见图2)。在实施例中,第二高度H2可以介于约50μm和约300μm之间,诸如约100μm,而导电柱319可以形成为具有介于约10μm和约200μm之间(诸如约10μm)的第三高度H3(在第四介电层321之上)。然而,可以利用任何合适的尺寸。
图3D示出了图3C的结构的顶视图,其中,图3C示出了图3D的沿着截线C-C’的截面图。如图3D示出的,一旦已经形成图3C的结构,则可以去除环件301的部分(诸如环件301的内部部分323),以将结构形成为期望的“环形”形状。在实施例中,环件301中将要去除的部分(包括环件301的内部部分323)可以通过以下步骤去除:在结构上方施加光刻胶,以保护不期望被去除的那些部分(例如,包括导电柱319的那些部分);之后曝光和显影光刻胶以暴露期望被去除的部分,诸如环件301的内部部分323。一旦已经显影光刻胶,可以使用一次或多次各向异性蚀刻工艺去除将要被去除的部分(包括内部部分323),但是可以利用任何合适的去除工艺。
在实施例中,在去除内部部分323之后,环件301可以具有介于约3mm和约30mm之间(诸如约12.6mm)的总环宽度WRO,以及介于约3mm和约30mm之间(诸如约12.6mm)的总环长度LRO。此外,环件301可以具有介于约0.6mm和约2.5mm之间(诸如约1.8mm)的环宽度WR(从外表面至先前内部部分323所在的位置)。因此,内部部分323的去除可以留下具有介于约1.4mm和约27.5mm之间(诸如约9mm)的内部宽度W1以及介于约1.4mm和约27.5mm之间(诸如约11mm)的内部长度L1的开口。然而,可以使用任何合适的尺寸。
在另一实施例中,可以使用诸如硅衬底或玻璃衬底的衬底来开始环件301的形成,而不是先后使用沉积、蚀刻和平坦化工艺来构建环件301。例如,在该实施例中,具有约100μm厚度的硅或玻璃芯的两侧可以层压有铜箔。之后可以使用例如激光钻孔工艺形成穿过芯的开口,但是也可以利用任何其它合适的工艺,诸如光刻掩模和具有一个或多个蚀刻剂的蚀刻工艺。在清洗工艺之后,化学镀工艺用诸如铜的导电材料对开口的侧壁进行镀敷,但是不会完全地填充开口。之后,可以层压、曝光和显影干膜光刻胶,之后在随后的镀工艺中使用该干膜光刻胶作为掩模以填充开口并且形成导电图案。施加、曝光和显影另一光刻胶,以暴露开口内的导电材料,并且利用化学镀镍化学镀钯浸金(ENEPIG)工艺将导电材料涂覆在开口内并且形成延伸穿过芯的衬底通孔(TSV)。
一旦已经形成穿过芯的TSV,则导电柱319可以与TSV形成电连接。在实施例中,导电柱319如上面参照图3C的描述形成。例如,施加光刻胶并且使光刻胶按照导电柱319期望的形状(例如,倒锥形形状)显影,并且在光刻胶内镀成导电柱319。然而,可以利用形成导电柱319的任何合适的方法。
此外,在导电柱319的形成之后,可以去除内部部分323以将芯形成为环形。在实施例中,如以上描述的,诸如通过使用光刻掩模和蚀刻工艺去除内部部分323。然而,也可以利用任何合适的去除方法。
在环件301利用硅衬底作为芯的实施例中,环件301的厚度(例如,第二高度H2)可以与第一半导体器件201实现更好的热性能。例如,在移动应用(例如,手机内)内利用环件301的实施例中,硅的包含可以创建用于从第一半导体器件201(例如,SOC)驱除热量的另一路径。例如,由第一半导体器件201产生的热量不仅可以通过例如第一半导体器件201的第一侧(例如,通过外部连接件)和第一半导体器件201的第二侧(例如,通过硅膏),而且也可以通过环件301去除,从而允许从第一半导体器件201去除整体更大的热量。
图3E示出了另一实施例,其中,形成延伸穿过第四介电层321并且将导电柱319连接至第二金属化层313的顶部通孔325,而不是形成穿过第四介电层321的导电柱319。在实施例中,可以在第四介电层321的放置之前通过镀诸如铜的导电材料层,并且之后图案化该导电材料层以形成顶部通孔325来形成顶部通孔325。一旦已经形成顶部通孔325,则可以在顶部通孔325上方形成或放置第四介电层321并且之后平坦化第四介电层321。
然而,通过分开形成顶部通孔325与导电柱319,在第四介电层321的顶部处,顶部通孔325可以具有与导电柱不同的宽度。例如,在特定实施例中,顶部通孔325可以具有小于第二柱宽度WP2的通孔宽度WV,诸如具有介于约5μm和约50μm之间(诸如约30μm)的通孔宽度WV。此外,在一些实施例中,顶部通孔325可以具有锥形形状,从而使得当顶部通孔325可以在顶部通孔325的顶部具有通孔宽度WV时,顶部通孔325也可以具有介于约10μm和约100μm之间(诸如约50μm)的底部通孔宽度WVB。然而,可以利用任何合适的尺寸。
图4示出了将第一半导体器件201和环件301放置在第一管芯附接膜105上。在实施例中,可以使用例如贴装(pick and place)工艺,以面朝上的方向将第一半导体器件201和环件301放置在第一管芯附接膜105上。然而,也可以利用将第一半导体器件201和环件301放置在第一管芯附接膜105上的任何合适的方法。
在实施例中,第一半导体器件201和环件301可以放置在第一载体衬底101上,其中,在第一半导体器件201和环件301之间具有允许用于密封剂的足够的空间,但同时仍足够接近以允许在第一半导体器件201的操作期间热量通过密封剂至环件301而有效传递。在特定实施例中,第一半导体器件201和环件301可以彼此间隔开介于约50μm和约400μm之间(诸如约100μm)的第一距离D1。然而,可以利用任何合适的距离。
通过一起利用环件301以及第一半导体器件201,可以在第一管芯附接膜105上方利用单个步骤(例如,用于放置环件301和第一半导体器件201的贴装工艺)来提供从第一半导体器件201的一侧至另一侧的连接。第一管芯附接膜105上方的这种单个步骤可以减少使用的步骤的数量,允许更短的制造时间和更大的产量。此外,通过使用具有内部导电结构的环件301,可以实现诸如小于约2的较低扇出率,同时也减少或消除了随后的模塑工艺期间的通孔塌陷问题。
图5示出了第一半导体器件201和环件301的密封。可以在模制器件(未在图5中单独示出)实施密封,模制器件可以包括顶部模制部分和与顶部模制部分分隔开的底部模制部分。当顶部模制部分降低至与底部模塑部分邻近时,可以形成用于第一载体衬底101、第一半导体器件201和环件301的模制空腔。
在密封工艺期间,可以将顶部模制部分放置为邻近底部模制部分,从而将第一载体衬底101、第一半导体器件201和环件301封闭在模制空腔内。一旦封闭,顶部模制部分和底部模制部分可以形成气密密封以控制气体流入模制空腔和从模制空腔流出。一旦密封,则可以将密封剂501放置在模制空腔内。密封剂501可以是模塑料树脂,诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。可以在顶部模制部分和底部模制部分的对准之前,将密封剂501放置在模制空腔内,或者可以通过注入口将密封剂501注入至模制空腔。
一旦已经将密封剂501放置在模制空腔内使得密封剂501密封第一载体衬底101、第一半导体器件201和环件301,则可以固化密封剂501以使密封剂501硬化,以用于最佳保护。虽然精确的固化工艺至少部分地取决于选择用于密封剂501的特定材料,在选择模塑料作为密封剂501的实施例中,可以通过诸如将密封剂501加热至介于约100℃和约130℃之间(诸如约125℃)持续约60秒至约3600秒(诸如约600秒)的工艺发生固化。此外,引发剂和/或催化剂可以包括在密封剂501内以更好地控制该固化工艺。
然而,本领域普通技术人员将意识到,上述固化工艺仅仅是示例性工艺并且不意味着限制当前的实施例。可以可选地使用诸如辐射或者甚至允许密封剂501在室温下硬化的其它固化工艺。可以使用任何合适的固化工艺,并且所有这些工艺均旨在完全地包括在本文讨论的实施例的范围内。
此外,通过利用环件301而不是简单地使用没有环件301的其它部分的通孔,环件301将占据比单独的通孔可以占据的更多的空间。因此,在密封工艺期间可以利用较少材料的密封剂501来密封相同的空间量,从而节约材料成本。环件301的使用也提供了额外的结构支撑,有助于减少或防止在随后的工艺期间发生过度的翘曲。
图6示出了密封剂501的减薄,以暴露第一半导体器件201和环件301以用于进一步处理。可以例如使用机械研磨或化学机械抛光(CMP)工艺来实施减薄,从而利用化学蚀刻剂和研磨剂以反应和研磨掉密封剂501、第一半导体器件201和环件301,直至已经暴露导电柱319(位于环件301上)和第一外部连接件203(位于第一半导体器件201上)。因此,第一半导体器件201和环件301可以具有也与密封剂501齐平的平坦表面。
在利用聚合物层205的另一实施例中,可以使用CMP工艺平坦化密封剂501与聚合物层205。在该实施例中,导电柱319将与聚合物层205齐平,同时聚合物层205仍覆盖下面的第一外部连接件203(位于第一半导体器件201上)。此外,聚合物层205和导电柱319与密封剂501齐平。
然而,虽然上述CMP工艺呈现为一个示例性实施例,但是不旨在限制该实施例。可以使用任何其它合适的去除工艺来减薄密封剂510、第一半导体器件201和环件301。例如,可以利用一系列化学蚀刻。可以利用该工艺和任何其它合适的工艺减薄密封剂501、第一半导体器件201和环件301,并且所有这些工艺均旨在完全地包括在实施例的范围内。
图7示出了RDL 701的形成以互连第一半导体器件201、环件301和第二外部连接件801。在实施例中,第一介电层(未在图7中单独示出)形成为覆盖密封剂501、第一半导体器件201和环件301。之后,使用例如光刻掩模和蚀刻工艺来图案化第一介电层以暴露下面的第一半导体器件201和环件301的导电元件。在存在聚合物层205的实施例中,之后第一介电层可以用作掩模以图案化聚合物层205并且暴露第一外部连接件203。
一旦已经暴露第一外部连接件203和导电柱319,则可以首先通过诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成RDL 701。之后,可以形成覆盖晶种层的光刻胶(也未示出)并且之后可以图案化光刻胶以暴露晶种层中期望形成的RDL 701所在的那些部分。
一旦已经形成并且图案化光刻胶,可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。该导电材料可以形成为具有介于约1μm和约10μm之间(诸如约5μm)的厚度。然而,虽然讨论的材料和方法适合于形成导电材料,但是这些材料仅仅是示例性的。可以使用诸如AlCu或Au的任何其它合适的材料和诸如CVD或PVD的任何其它合适的形成工艺来形成RDL 701。
一旦已经形成导电材料,则可以通过诸如灰化的合适的去除工艺来去除光刻胶。此外,在光刻胶的去除之后,则例如可以将导电材料用作掩模通过合适的蚀刻工艺来去除晶种层的由光刻胶覆盖的那些部分。
图7也示出了RDL 701上方的第一钝化层703的形成,以为RDL 701和其它下面的结构提供保护和隔离。在实施例中,第一钝化层703可以是聚苯并恶唑(PBO)、ABF膜,但是可以利用诸如聚酰亚胺或聚酰亚胺衍生物的其它合适的材料。在另一特定实施例中,第一钝化层703可以由与密封剂501相同的材料形成。可以使用例如旋涂工艺或膜层压工艺将第一钝化层703放置至介于约5μm和约25μm之间(诸如约7μm)的厚度,但是可以可选地使用任何合适的方法和厚度。
一旦已经形成RDL 701和第一钝化层703,可以重复该工艺以形成另一RDL 701和另一第一钝化层703。该工艺可以根据需求重复多次以形成任何合适数量的导电层和钝化层,诸如三个RDL 701层。然而,可以利用任何合适数量的层。
在实施例中,RDL 701形成为具有适合于整体设计的高度。在第一半导体器件201将要用于移动应用的实施例中,RDL 701可以形成为具有介于约10μm和约50μm之间(诸如约25μm)的第四高度H4。然而,可以利用任何合适的高度。
通过使用RDL 701互连第一半导体器件201和环件301,可以根据需求修改至下面的环件301和第一半导体器件201的电连接件的位置。此外,通过利用环件301和第一半导体器件201,器件的总引脚数可以增加,诸如大于1000。然而,可以利用任何合适的引脚数,不管是大于还是小于1000。
图8示出了与RDL 701形成电接触的第二外部连接件801的形成。在实施例中,顶部钝化层(未在图8中单独示出)放置在RDL 701上,并且可以与第一钝化层703类似。在已经形成顶部钝化层之后,可以通过去除顶部钝化层的部分来制成穿过顶部钝化层的开口以暴露下面的RDL 701的至少部分。该开口允许RDL 701和第二外部连接件801之间的接触。可以使用合适的光刻掩模和蚀刻工艺形成开口,但是可以使用暴露RDL 701的部分的任何合适的工艺。
在实施例中,第二外部连接件801可以穿过顶部钝化层被放置在RDL701上,并且可以是包括诸如焊料的共晶材料的球栅阵列(BGA),但是可以可选地使用任何合适的材料。可选地,可以在第二外部连接件801和RDL 701之间利用凸块下金属。在第二外部连接件801是焊料凸块的实施例中,可以使用球落(ball drop)方法(诸如直接球落工艺)来形成第二外部连接件801。可选地,可以首先通过诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成锡层,并且之后实施回流以将材料成形为期望的凸块形状来形成焊料凸块。一旦已经形成第二外部连接件801,则可以实施测试以确保该结构适合于进一步处理。
图9示出了第一载体衬底101与第一半导体器件201和环件301的脱离。在实施例中,第二外部连接件801以及因此包括第一半导体器件201和环件301的结构,可以附接至环结构(未单独示出)。环结构可以是旨在脱离工艺期间和之后为结构提供支撑和稳定性的金属环。在实施例中,使用例如紫外线胶带将第二外部连接件801、第一半导体器件201和环件301附接至环结构,但是可以可选地使用任何其它合适的粘合或附接。
一旦将第二外部连接件801以及因此包括第一半导体器件201和环件301的结构附接至环结构,则可以使用例如热处理来改变粘合层103的粘合性能而使第一载体衬底101从包括第一半导体器件201和环件301的结构处脱粘。在特定实施例中,利用诸如紫外线(UV)激光器、二氧化碳(CO2)激光器或红外(IR)激光的能量源照射并加热粘合层103,直至粘合层103失去它的至少一些粘合性能。一旦实施,则可以从包括第二外部连接件801、第一半导体器件201和环件301的结构处物理分离并且去除第一载体衬底101和粘合层103。
图10示出了焊盘的显露,这包括图案化第一管芯附接膜105以形成第一开口1001并且暴露第一金属化层307。在实施例中,可以使用例如干蚀刻工艺或激光钻孔方法来图案化第一管芯附接膜105。此外,一旦已经图案化第一管芯附接膜105,则可以继续蚀刻工艺(或单独的蚀刻工艺)以去除聚合物层303的部分并且暴露第一金属化层307。然而,可以利用任何合适的工艺来暴露第一金属化层307。
可选地,在已经去除第一管芯附接膜105之后,可以放置背侧球焊盘1003或其它凸块下金属。在实施例中,背侧球焊盘1003可以包括诸如焊膏(solder on paste)或有机保焊剂(OSP)的导电材料,但是可以可选地利用任何合适的材料。在实施例中,可以使用模板来施加背侧球焊盘1003,但是可以可选地利用任何合适的施加方法,并且之后回流以形成凸块形状。
图11示出与第一金属化层307物理接触的第三外部连接件1101的放置(在不存在背侧球焊盘1003的实施例中)。在实施例中,可以形成第三外部连接件1101以提供第一金属化层307和例如第一封装件1100之间的外部连接。第三外部连接件1101可以是诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块,并且可以包括诸如锡的材料或或诸如焊膏、银或铜的其它合适的材料。在第三外部连接件1101是锡焊料凸块的实施例中,可以首先通过诸如蒸发、电镀、印刷、焊料转移、球植等的任何合适的方法形成锡层来形成厚度为例如约100μm的锡层来形成第三外部连接件1101。一旦已经在衬底上形成锡层,则实施回流以将材料成形为期望的凸块性状。
图11也示出了第三外部连接件1101与第一封装件1100的接合。在实施例中,第一封装件1100可以包括封装衬底1103、第二半导体器件1105、第三半导体器件1107(接合至第二半导体器件1105)、接触焊盘(用于电连接至第三外部连接件1101)和第二密封剂1111。在实施例中,封装衬底1103可以是例如包括内部互连件(例如,衬底通孔)的封装衬底以将第二半导体器件1105和第三半导体器件1107连接至第三外部连接件1101。
可选地,封装衬底1103可以是用作中间衬底以将第二半导体器件1105和第三半导体器件1107连接至第三外部连接件1101的中介片。在该实施例中,封装衬底1103可以是,例如,掺杂或未掺杂的硅衬底或绝缘体上硅(SOI)衬底的有源层。然而,封装衬底1103可以可选地是玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其它衬底。这些和任何其它合适的材料可以可选地用于封装衬底1103。
第二半导体器件1105可以是设计为用于预期目的的半导体器件,诸如为存储器管芯(例如,DRAM管芯)、逻辑管芯、中央处理单元(CPU)管芯、无源集成器件、射频模块、这些的组合等。在一个实施例中,根据对特定功能的需求,第二半导体器件1105包括集成电路器件,诸如晶体管、电容器、电感器、电阻器、第一金属化层(未示出)等。在实施例中,第二半导体器件1105被设计和制造为与第一半导体器件201协同或同时工作。
第三半导体器件1107可以与第二半导体器件1105类似。例如,第三半导体器件1107可以是设计为用于预期目并且包括期望功能的集成电路器件的半导体器件(例如,DRAM管芯)。在实施例中,第三半导体器件1107被设计为与第一半导体器件201和/或第二半导体器件1105协同或同时工作。
可以将第三半导体器件1107接合至第二半导体器件1105。在实施例中,诸如通过使用粘合剂使第三半导体器件1107仅与第二半导体器件1105物理接合。在该实施例中,可以使用例如引线接合(wire bond)(未单独示出)将第三半导体器件1107和第二半导体器件1105电连接至封装衬底1103,但是可以利用任何合适的电接合。
在另一实施例中,第三半导体器件1107可以物理和电接合至第二半导体器件1105。在该实施例中,第三半导体器件1107可以包括与第二半导体器件1105上的外部连接件(也未在图11中单独示出)连接的外部连接件(未在图11中单独示出),以将第三半导体器件1107与第二半导体器件1105互连。
可以在封装衬底1103上以形成接触焊盘以形成第二半导体器件1105和例如第三外部连接件1101之间的电连接。在实施例中,接触焊盘可以形成在封装衬底1103内的电布线上方并且与封装衬底1103内的电布线(诸如衬底通孔)电接触。接触焊盘可以包括铝,但是可以可选地使用诸如铜的其它材料。形成接触焊盘可以通过以下步骤:使用诸如溅射的沉积工艺来形成材料层(未示出),并且之后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除该材料层的部分以形成接触焊盘。然而,可以利用任何其它合适的工艺来形成接触焊盘。
第二密封剂1111可以用于封装和保护第二半导体器件1105、第三半导体器件1107和封装衬底1103。在实施例中,第二密封剂1111可以是模塑料并且可以使用模制器件(未在图11中示出)放置。例如,封装衬底1103、第二半导体器件1105和第三半导体器件1107可以放置在模制器件的腔体内,并且该腔体可以是气密密封的。第二密封剂1111可以在腔体气密密封之前放置在腔内,或者可以通过注入口注入至腔体内。在实施例中,第二密封剂1111可以是模塑料树脂,诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。
一旦已经将第二密封剂1111放置在腔体内使得第二密封剂1111密封封装衬底1103、第二半导体器件1105和第三半导体器件1107周围的区域,则可以固化第二密封剂1111以使第二密封剂1111硬化,以用于最佳保护。虽然精确的固化工艺至少部分地取决于选择用于第二密封剂1111的特定材料,在选择模塑料作为第二密封剂1111的实施例中,可以通过诸如将第二密封剂1111加热至介于约100℃和约130℃之间(诸如约125℃)持续约60秒至约3000秒(诸如约600秒)的工艺发生固化。此外,引发剂和/或催化剂可以包括在第二密封剂1111内以更好地控制该固化工艺。
然而,本领域普通技术人员将意识到,上述固化工艺仅仅是示例性工艺并且不意味着限制当前的实施例。可以可选地使用诸如辐射或者甚至允许第二密封剂1111在室温下硬化的其它固化工艺。可以使用任何合适的固化工艺,并且所有这些工艺均旨在完全地包括在本文讨论的实施例的范围内。
一旦已经形成第三外部连接件1101,则第三外部连接件1101与接触焊盘对准并且被放置为与接触焊盘物理接触,并且实施接合。例如,在第三外部连接件1101是焊料凸块的实施例中,接合工艺可以包括回流工艺,从而将第三外部连接件1101的温度升高至将使第三外部连接件1101液化并流动的点,从而一旦第三外部连接件1101重新固化,则将第一封装件1100接合至第三外部连接件1101。可选地,可以将底部填充材料或焊膏放置在第一封装件1100和密封剂501之间
图11也示出了将第一半导体器件201与放置在第一载体衬底101上的其它半导体器件分离的分割工艺。在实施例中,可以通过使用锯片(未单独示出)切割穿过密封剂501来实施分割。但是,本领域普通技术人员将意识到,利用锯片进行分割仅仅是一个示例性实施例,而不旨在限制。可以利用用于实施分割的任何方法,诸如利用一个或多个蚀刻。这些方法和任何其它合适的方法均可以用于分割第一半导体器件201。
在实施例中,制造半导体器件的方法包括:将粘合层放置在载体上方;将第一半导体器件放置在载体上,第一半导体器件具有第一厚度;将第一衬底放置在载体上,第一衬底具有与第一半导体器件齐平的第一表面并且具有小于第一厚度的第二厚度,其中,导电柱与第一衬底物理接触;以及将密封剂与第一衬底、导电柱和第一半导体器件的每个均物理接触。在实施例中,该方法还包括形成将导电柱与第一半导体器件的外部连接件连接的第一再分布层。在实施例中,第一再分布层具有介于约10μm至约50μm之间的厚度。在实施例中,第一衬底是环绕第一半导体器件的环件。在实施例中,导电柱远离第一衬底延伸介于约10μm和约200μm之间的距离。在实施例中,第一衬底具有介于约50μm和约300μm之间的厚度。在实施例中,第一半导体器件是片上系统半导体器件。
在另一实施例中,制造半导体器件的方法包括:形成具有导电布线的中介片;将导电柱镀至中介片上并且与导电布线电连接;去除中介片的部分以形成环件;将该环件放置在第一载体衬底上;将第一半导体器件放置在第一载体衬底上,其中,在放置环件并且放置第一半导体器件之后,该环件在俯视图中围绕第一半导体器件;用密封剂填充第一半导体器件和环件之间的间隔,其中,在填充间隔之后,密封剂覆盖导电柱的侧壁;在密封剂的第一侧上方形成再分布层,其中,再分布层与第一半导体器件的导电柱和外部连接件物理接触;以及将第一封装件附接至密封剂的与第一侧相对的第二侧。在实施例中,第一封装件是存储器封装件。在实施例中,形成中介片包括在与第一载体衬底不同的第二载体衬底上依次构建导电层和介电材料层。在实施例中,形成中介片包括形成完全穿过硅衬底的开口。在实施例中,形成中介片包括形成完全穿过玻璃衬底的开口。在实施例中,镀导电柱还包括将光刻胶放置在中介片上;图案化光刻胶以暴露导电布线的部分;以及通过光刻胶将导电材料镀至导电布线上。在实施例中,镀导电柱形成倒锥形形状。
在另一实施例中,半导体器件包括:嵌入在密封剂内的半导体器件;嵌入在密封剂内的中介片,其中,中介片具有第一部分和远离第一部分延伸的导电柱,导电柱具有倒锥形形状,第一部分的第一厚度小于半导体器件的第二厚度,中介片围绕半导体器件;位于密封剂的第一侧上方的再分布层,再分布层将导电柱电连接至半导体器件;以及位于密封剂中与再分布层相对的一侧上的第一封装件,第一封装件通过中介片的第一部分和导电柱连接至半导体器件。实施例中,导电柱具有介于约10μm和约200μm之间的高度。在实施例中,中介片的第一部分的第一高度小于半导体器件的第二高度。在实施例中,第一部分包括硅芯。在实施例中,第一部分包括玻璃。在实施例中,半导体器件具有与中介片的第一部分的第二表面齐平的第一表面,并且其中,半导体器件具有与导电柱的第四表面齐平的第三表面,第一表面与第三表面相对。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (20)
1.一种制造半导体器件的方法,所述方法包括:
将粘合层放置在载体上方;
将第一半导体器件放置在所述载体上,所述第一半导体器件具有第一厚度;
将第一衬底放置在所述载体上,所述第一衬底具有小于所述第一厚度的第二厚度,其中,导电柱与所述第一衬底物理接触;以及
将密封剂与所述第一衬底、所述导电柱和所述第一半导体器件的每个均物理接触,所述导电柱的最顶表面与所述密封剂的最顶表面齐平、所述导电柱的所述最顶表面和所述密封剂的所述最顶表面远离所述载体。
2.根据权利要求1所述的方法,还包括:形成将所述导电柱与所述第一半导体器件的外部连接件连接的第一再分布层。
3.根据权利要求2所述的方法,其中,所述第一再分布层具有介于10μm至50μm之间的厚度。
4.根据权利要求1所述的方法,其中,所述第一衬底是环绕所述第一半导体器件的环件。
5.根据权利要求1所述的方法,其中,所述导电柱远离所述第一衬底延伸了介于10μm和200μm之间的距离。
6.根据权利要求1所述的方法,其中,所述第一衬底具有介于50μm和300μm之间的厚度。
7.根据权利要求1所述的方法,其中,所述第一半导体器件是片上系统半导体器件。
8.一种制造半导体器件的方法,所述方法包括:
形成具有导电布线的中介片;
将导电柱镀至所述中介片上并且与所述导电布线电连接;
去除所述中介片的部分以形成环件;
将所述环件放置在第一载体衬底上;
将第一半导体器件放置在所述第一载体衬底上,其中,在放置所述环件并且放置所述第一半导体器件之后,自顶向下看,所述环件围绕所述第一半导体器件;
用密封剂填充所述第一半导体器件和所述环件之间的间隔,其中,在填充所述间隔之后,所述密封剂覆盖所述导电柱的侧壁;
在所述密封剂的第一侧上方形成再分布层,其中,所述再分布层与所述导电柱和所述第一半导体器件的外部连接件物理接触;以及
将第一封装件附接至所述密封剂的与所述第一侧相对的第二侧。
9.根据权利要求8所述的方法,其中,所述第一封装件是存储封装件。
10.根据权利要求8所述的方法,其中,形成所述中介片包括在与所述第一载体衬底不同的第二载体衬底上依次累积导电层和介电材料层。
11.根据权利要求8所述的方法,其中,形成所述中介片包括形成完全穿过硅衬底的开口。
12.根据权利要求8所述的方法,其中,形成所述中介片包括形成完全穿过玻璃衬底的开口。
13.根据权利要求8所述的方法,其中,镀所述导电柱还包括:
将光刻胶放置在所述中介片上;
图案化所述光刻胶以暴露所述导电布线的部分;以及
穿过所述光刻胶将导电材料镀至所述导电布线上。
14.根据权利要求8所述的方法,其中,镀所述导电柱形成倒锥形形状。
15.一种半导体器件,包括:
半导体器件,嵌入在密封剂内;
中介片,嵌入在所述密封剂内,其中,所述中介片具有第一部分和远离所述第一部分延伸的导电柱,所述导电柱具有倒锥形形状,所述第一部分具有小于所述半导体器件的第二厚度的第一厚度,所述中介片围绕所述半导体器件;
再分布层,位于所述密封剂的第一侧上方,所述再分布层与所述导电柱物理接触,所述再分布层将所述导电柱电连接至所述半导体器件;以及
第一封装件,位于所述密封剂中与所述再分布层相对的侧上,所述第一封装件通过所述中介片的第一部分和所述导电柱连接至所述半导体器件。
16.根据权利要求15所述的半导体器件,其中,所述导电柱具有介于10μm和200μm之间的高度。
17.根据权利要求15所述的半导体器件,其中,所述中介片的第一部分的第一高度小于所述半导体器件的第二高度。
18.根据权利要求15所述的半导体器件,其中,所述第一部分包括硅芯。
19.根据权利要求15所述的半导体器件,其中,所述第一部分包括玻璃。
20.根据权利要求15所述的半导体器件,其中,所述半导体器件具有与所述中介片的第一部分的第二表面齐平的第一表面,并且其中,所述半导体器件具有与所述导电柱的第四表面齐平的第三表面,所述第一表面与所述第三表面相对。
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Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10269682B2 (en) * | 2015-10-09 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices |
CN114121895A (zh) | 2016-02-10 | 2022-03-01 | 超极存储器股份有限公司 | 半导体装置 |
US10757800B1 (en) | 2017-06-22 | 2020-08-25 | Flex Ltd. | Stripline transmission lines with cross-hatched pattern return plane, where the striplines do not overlap any intersections in the cross-hatched pattern |
US11224117B1 (en) | 2018-07-05 | 2022-01-11 | Flex Ltd. | Heat transfer in the printed circuit board of an SMPS by an integrated heat exchanger |
US10636756B2 (en) * | 2018-07-05 | 2020-04-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protrusion E-bar for 3D SIP |
KR102499039B1 (ko) * | 2018-11-08 | 2023-02-13 | 삼성전자주식회사 | 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법 |
US10964660B1 (en) | 2018-11-20 | 2021-03-30 | Flex Ltd. | Use of adhesive films for 3D pick and place assembly of electronic components |
US11088095B2 (en) * | 2018-12-07 | 2021-08-10 | Nanya Technology Corporation | Package structure |
US10896877B1 (en) * | 2018-12-14 | 2021-01-19 | Flex Ltd. | System in package with double side mounted board |
US11557541B2 (en) * | 2018-12-28 | 2023-01-17 | Intel Corporation | Interconnect architecture with silicon interposer and EMIB |
US10770433B1 (en) * | 2019-02-27 | 2020-09-08 | Apple Inc. | High bandwidth die to die interconnect with package area reduction |
CN111883506B (zh) * | 2019-05-03 | 2022-09-06 | 矽品精密工业股份有限公司 | 电子封装件及其承载基板与制法 |
IT201900006736A1 (it) * | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di fabbricazione di package |
IT201900006740A1 (it) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | Procedimenti di strutturazione di substrati |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
US11171127B2 (en) * | 2019-08-02 | 2021-11-09 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and method of manufacturing semiconductor device |
TW202109800A (zh) * | 2019-08-15 | 2021-03-01 | 力成科技股份有限公司 | 具有微細間距矽穿孔封裝的扇出型封裝晶片結構以及扇出型封裝單元 |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
WO2021127970A1 (en) * | 2019-12-24 | 2021-07-01 | Yangtze Memory Technologies Co., Ltd. | Megnetoresistive random access memory |
KR102664267B1 (ko) * | 2020-02-20 | 2024-05-09 | 삼성전자주식회사 | 반도체 패키지 |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
DE102021100338A1 (de) * | 2020-05-20 | 2021-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiterbauelement und herstellungsverfahren |
US11508633B2 (en) * | 2020-05-28 | 2022-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having taper-shaped conductive pillar and method of forming thereof |
KR20220000273A (ko) | 2020-06-25 | 2022-01-03 | 삼성전자주식회사 | 반도체 패키지 |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11764179B2 (en) * | 2020-08-14 | 2023-09-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
KR20220042705A (ko) * | 2020-09-28 | 2022-04-05 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
TWI776710B (zh) * | 2021-10-18 | 2022-09-01 | 創意電子股份有限公司 | 中介層及半導體封裝 |
US20230147337A1 (en) * | 2021-11-06 | 2023-05-11 | Onano Industrial Corp. | Three-dimensional ltcc package structure |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103681613A (zh) * | 2012-09-10 | 2014-03-26 | 台湾积体电路制造股份有限公司 | 具有离散块的半导体器件 |
TW201501223A (zh) * | 2013-06-28 | 2015-01-01 | Stats Chippac Ltd | 形成低輪廓三維扇出封裝的半導體裝置和方法 |
CN105280579A (zh) * | 2014-07-01 | 2016-01-27 | 台湾积体电路制造股份有限公司 | 半导体封装件和方法 |
CN106206529A (zh) * | 2015-01-23 | 2016-12-07 | 台湾积体电路制造股份有限公司 | 半导体器件和制造方法 |
CN106672888A (zh) * | 2015-11-11 | 2017-05-17 | 飞思卡尔半导体公司 | 封装集成电路管芯的方法和器件 |
CN106711094A (zh) * | 2015-11-17 | 2017-05-24 | Nepes株式会社 | 半导体封装件及其制造方法 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5240043A (en) | 1975-09-25 | 1977-03-28 | Shimada Phys & Chem Ind Co Ltd | Waveguide-type directional coupler |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
FR2944865B1 (fr) * | 2009-04-27 | 2011-06-24 | Commissariat Energie Atomique | Capteur de contrainte et son procede de realisation. |
JP5617846B2 (ja) | 2009-11-12 | 2014-11-05 | 日本電気株式会社 | 機能素子内蔵基板、機能素子内蔵基板の製造方法、及び、配線基板 |
US9985150B2 (en) | 2010-04-07 | 2018-05-29 | Shimadzu Corporation | Radiation detector and method of manufacturing the same |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US8384227B2 (en) * | 2010-11-16 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die |
US8648470B2 (en) * | 2011-01-21 | 2014-02-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming FO-WLCSP with multiple encapsulants |
DE102011001591A1 (de) * | 2011-03-28 | 2012-10-04 | Zf Lenksysteme Gmbh | Vorrichtung zum Freigeben einer Öffnung in einem Gehäuseteil eines Lenkgetriebes |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
US8810024B2 (en) * | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US9385006B2 (en) | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US20140012494A1 (en) * | 2012-07-06 | 2014-01-09 | International Business Machines Corporation | Collaborative gps tracking |
US9559039B2 (en) * | 2012-09-17 | 2017-01-31 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package |
KR101419597B1 (ko) * | 2012-11-06 | 2014-07-14 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9378982B2 (en) * | 2013-01-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9087832B2 (en) * | 2013-03-08 | 2015-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Warpage reduction and adhesion improvement of semiconductor die package |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US10971476B2 (en) * | 2014-02-18 | 2021-04-06 | Qualcomm Incorporated | Bottom package with metal post interconnections |
US9735134B2 (en) * | 2014-03-12 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with through-vias having tapered ends |
US10453785B2 (en) | 2014-08-07 | 2019-10-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming double-sided fan-out wafer level package |
US9870997B2 (en) | 2016-05-24 | 2018-01-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
US10276543B1 (en) * | 2017-10-27 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semicondcutor device package and method of forming semicondcutor device package |
EP4181196A3 (en) * | 2017-12-29 | 2023-09-13 | INTEL Corporation | Microelectronic assemblies with communication networks |
-
2018
- 2018-01-19 US US15/875,124 patent/US10468339B2/en active Active
- 2018-04-27 TW TW107114496A patent/TWI659517B/zh active
- 2018-08-17 CN CN201810937666.8A patent/CN110060935B/zh active Active
-
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- 2019-10-04 US US16/593,347 patent/US11018081B2/en active Active
-
2021
- 2021-05-14 US US17/320,858 patent/US11646256B2/en active Active
-
2023
- 2023-04-18 US US18/302,112 patent/US20230253301A1/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103681613A (zh) * | 2012-09-10 | 2014-03-26 | 台湾积体电路制造股份有限公司 | 具有离散块的半导体器件 |
TW201501223A (zh) * | 2013-06-28 | 2015-01-01 | Stats Chippac Ltd | 形成低輪廓三維扇出封裝的半導體裝置和方法 |
CN105280579A (zh) * | 2014-07-01 | 2016-01-27 | 台湾积体电路制造股份有限公司 | 半导体封装件和方法 |
CN106206529A (zh) * | 2015-01-23 | 2016-12-07 | 台湾积体电路制造股份有限公司 | 半导体器件和制造方法 |
CN106672888A (zh) * | 2015-11-11 | 2017-05-17 | 飞思卡尔半导体公司 | 封装集成电路管芯的方法和器件 |
CN106711094A (zh) * | 2015-11-17 | 2017-05-24 | Nepes株式会社 | 半导体封装件及其制造方法 |
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