CN106206529A - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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Publication number
CN106206529A
CN106206529A CN201510221086.5A CN201510221086A CN106206529A CN 106206529 A CN106206529 A CN 106206529A CN 201510221086 A CN201510221086 A CN 201510221086A CN 106206529 A CN106206529 A CN 106206529A
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Prior art keywords
semiconductor device
layer
hole
protective layer
reflowable
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CN201510221086.5A
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CN106206529B (zh
Inventor
林俊成
蔡柏豪
郑礼辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体器件和制造方法。放置与所述通孔电连接的可回流材料，其中，通孔延伸穿过密封剂。在可回流材料上方形成保护层。在实施例中，在保护层内形成开口以暴露可回流材料。在另一实施例中，形成保护层从而使得可回流材料延伸为远离保护层。本发明涉及半导体器件和制造方法。

Description

半导体器件和制造方法
技术领域
本发明涉及半导体器件和制造方法。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度不断提高，半导体产业经历了快速的发展。在大多数情况下，这种集成度的提高源自最小部件尺寸的不断减小(例如，将半导体工艺节点朝着亚20nm节点缩减)，这允许更多的部件集成在给定的区域内。随着近来对微型化、更高速度、更大带宽以及更低功耗和延迟的要求提高，也产生了对于半导体管芯的更小和更具创造性的封装技术的需要。
随着半导体技术的进一步发展，堆叠和接合的半导体器件作为有效替代物出现从而进一步减小半导体器件的物理尺寸。在堆叠式半导体器件中，至少部分地在不同的半导体衬底上制造有源电路(诸如逻辑、存储器、处理器电路等)，和然后将这些有源电路物理和电接合在一起以形成功能器件。这样的接合工艺利用复杂的技术，并且期望改进。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：第一半导体管芯，通过密封剂封装；通孔，延伸穿过所述密封剂并且与所述第一半导体管芯横向分隔开；第一可回流导电材料，与所述通孔电连接；以及保护层，至少部分地位于所述第一可回流导电材料和所述第一半导体管芯上方，其中，所述保护层具有暴露所述第一可回流导电材料的开口。
在上述半导体器件中，还包括：重分布层，位于所述通孔和所述第一可回流导电材料之间。
在上述半导体器件中，所述开口的侧壁具有至少75°的角。
在上述半导体器件中，还包括：聚合物层，位于所述第一半导体管芯和所述保护层之间。
在上述半导体器件中，还包括：第二可回流导电材料，延伸穿过所述开口并且与所述第一可回流导电材料物理接触。
在上述半导体器件中，所述保护层是阻焊剂(SR)、层压复合(LC)胶带、味之素构建膜(ABF)、非导电膏(NCP)、非导电膜(NCF)、图案化的底部填充物(PUF)或翘曲改进粘合剂(WIA)。
在上述半导体器件中，所述保护层与邻近所述第一半导体管芯的管芯附接膜物理接触。
根据本发明的另一方面，还提供了一种半导体器件，包括：第一通孔，延伸穿过密封剂；第一半导体管芯，延伸穿过所述密封剂，所述密封剂的至少一部分位于所述第一通孔和所述第一半导体管芯之间；保护层，位于所述第一通孔和所述第一半导体管芯上方，所述保护层具有垂直于所述第一半导体管芯的主要表面的第一高度；以及第一可回流材料，延伸穿过所述保护层，所述第一可回流材料具有垂直于所述第一半导体管芯的主要表面的第二高度，所述第二高度大于所述第一高度。
在上述半导体器件中，还包括：聚合物层，位于所述保护层和所述第一半导体管芯之间。
在上述半导体器件中，还包括：第一封装件，接合至所述第一可回流材料。
在上述半导体器件中，所述保护层与所述密封剂物理接触。
在上述半导体器件中，还包括：重分布层，位于所述保护层和所述第一通孔之间。
在上述半导体器件中，还包括：第二可回流材料，与所述第一可回流材料物理连接，其中，所述保护层在所述第一可回流材料的一部分和所述第二可回流材料的一部分之间延伸。
在上述半导体器件中，还包括：第一DRAM封装件，与所述第一通孔电连接。
根据本发明的又一方面，还提供了一种制造半导体器件的方法，所述方法包括：将第一半导体管芯和通孔封装在密封剂内，其中，所述封装将所述密封剂的至少一部分放置在所述第一半导体管芯和所述通孔之间；放置与所述通孔电接触的第一可回流材料；以及在放置所述第一可回流材料之后，通过形成保护层来密封所述第一可回流材料的至少一部分，其中，所述第一可回流材料通过所述保护层暴露。
在上述方法中，形成所述保护层还包括：用所述保护层覆盖所述第一可回流材料；以及在所述保护层内形成开口以暴露所述第一可回流材料。
在上述方法中，还包括：通过将导电材料放置在所述开口内并且与所述第一可回流材料物理接触来接合第一封装件。
在上述方法中，形成所述开口还包括激光钻孔工艺。
在上述方法中，形成所述开口还包括光刻掩蔽和蚀刻工艺。
在上述方法中，形成所述保护层还包括：将所述保护层施加至具有比所述第一可回流材料更小的厚度。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的通孔的形成。
图2示出了根据一些实施例的第一半导体器件的实施例。
图3示出了根据一些实施例的将第一半导体器件放置于通孔之间。
图4示出了根据一些实施例的第一半导体器件和通孔的封装。
图5示出了根据一些实施例的重分布层和外部连接件的形成。
图6A至图6B示出了根据一些实施例的载体晶圆的脱粘。
图7A至图7B示出了根据一些实施例的通孔的暴露。
图8示出了根据一些实施例的可回流材料的放置。
图9示出了根据一些实施例的保护层的放置。
图10示出了根据一些实施例的另一封装件的接合。
图11示出了根据一些实施例的半导体衬底的分割。
图12至图13B示出了根据一些实施例的其中可回流材料从保护层延伸的实施例。
图14至图15示出了根据一些实施例的不具有聚合物层的实施例。
图16至图18示出了根据一些实施例的利用重分布层的实施例。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
现在参考图1，其中，示出了第一载体衬底101，和位于第一载体衬底101上方的粘合层103、聚合物层105和第一晶种层107。例如，第一载体衬底101包括诸如玻璃或氧化硅的硅基材料、或诸如氧化铝的其他材料、这些材料的任何组合等。第一载体衬底101是平坦的以适合于诸如第一半导体器件201和第二半导体器件301(在图1中没有示出，但是下文中结合图2A至图3示出并且进行了论述)的半导体器件的附接。
粘合层103放置在第一载体衬底101上以帮助粘合上面的结构(例如，聚合物层105)。在实施例中，粘合层103可以包括紫外胶，当其暴露于紫外线光时，紫外胶失去其粘接性能。然而，也可以使用其他类型的粘合剂，诸如压敏粘合剂、辐射可固化粘合剂、环氧树脂、这些的组合等。粘合层103可以以半液体或凝胶的形式放置到第一载体衬底101上，其在压力下容易变形。
例如，聚合物层105放置在粘合层103上方并且被利用以向第一半导体器件201和第二半导体器件301(一旦已附接第一半导体器件201和第二半导体器件301)提供保护。在实施例中，聚合物层105可以是聚苯并恶唑(PBO)，但是可以可选地利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何适合的材料。可以使用例如旋涂工艺将聚合物层105放置成具有介于约0.5μm和约10μm之间(诸如5μ诸)的厚度，但是可以可选地利用任何合适的方法和厚度。
第一晶种层107形成在聚合物层105上方。在实施例中，第一晶种层107是帮助在随后处理步骤期间形成更厚层的导电材料的薄层。第一晶种层107可以包括约厚的钛层以及紧随的约厚的铜层。取决于所期望的材料，可使用诸如溅射、蒸发或PECVD工艺的工艺生成第一晶种层107。第一晶种层107可以形成为具有介于约0.3μm和约1μm之间的厚度，诸如约0.5μm。
图1也示出了在第一晶种层107上方的光刻胶109的放置和图案化。在实施例中，可以使用例如旋涂技术在第一晶种层107上将光刻胶109放置成具有介于约50μm和约250μm之间的高度，诸如约120μm。一旦被放置于合适的地方，则可以通过将光刻胶109暴露于图案化的能量源(例如，图案化的光源)以便引发化学反应，从而引发暴露于图案化的光源的光刻胶109的那些部分中的物理变化而图案化光刻胶109。然后，对曝光的光刻胶109应用显影剂以利用该物理变化并且取决于所期望的图案而选择性地去除光刻胶109的曝光部分或光刻胶109的未曝光部分。
在实施例中，在光刻胶109内形成的图案是用于通孔111的图案。以使得通孔111将位于随后附接的器件(诸如第一半导体器件201和第二半导体器件301)的不同侧上的布置来形成通孔111。然而，可以可选地利用通孔111的图案的任何合适的布置，诸如通孔111的图案定位为使得第一半导体器件201和第二半导体器件301被放置于通孔111的相对两侧上。
在实施例中，在光刻胶109内形成通孔111。在实施例中，通孔111包括诸如铜、钨、其他导电金属等的一种或多种导电材料，并且可以例如通过电镀、化学镀等形成。在实施例中，使用电镀工艺，其中，第一晶种层107和光刻胶109被淹没或浸没在电镀液中。第一晶种层107表面电连接至外部DC电源的负极侧，从而使得第一晶种层107在电镀工艺中用作阴极。诸如铜阳极的固体导电阳极也浸没在溶液中并且被附接至电源的正极侧。来自阳极的原子溶解在溶液中，例如第一晶种层107的阴极从溶液中获取溶解的原子，从而对光刻胶109的开口内的第一晶种层107的暴露导电区域进行镀工艺。
一旦已经使用光刻胶109和第一晶种层107形成通孔111，则可以使用合适的去除工艺去除光刻胶109(在图1中没有示出，但在下面的图3中可见)。在实施例中，等离子灰化工艺可以用于去除光刻胶109，由此，光刻胶109的温度可以增大直到光刻胶109经历热分解并且可以被去除。然而，可以可选地利用任何其他合适的工艺，诸如湿剥离。光刻胶109的去除可以暴露出下面的第一晶种层107的部分。
一旦暴露，可以实施第一晶种层107的暴露部分的去除(在图1中没有示出，但在下面的图3中可见)。在实施例中，第一晶种层107的暴露部分(例如，未被通孔111覆盖的那些部分)可以通过例如湿或干蚀刻工艺去除。例如，在干蚀刻工艺中，将通孔111用作掩模，可以将反应剂导向第一晶种层107。在另一实施例中，蚀刻剂可以喷涂或以其他方式放置为与第一晶种层107接触以去除第一晶种层107的暴露部分。在已经蚀刻掉第一晶种层107的暴露部分之后，聚合物层105的部分暴露在通孔111之间。
图2示出了将附接至通孔111(在图2中未示出，但是结合图3在下文中示出和描述)内的聚合物层105的第一半导体器件201。在实施例中，第一半导体器件201包括第一衬底203、第一有源器件(未单独示出)、第一金属化层205、第一接触焊盘207、第一钝化层211和第一外部连接件209。第一衬底203可以包括掺杂或未掺杂的块状硅或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括诸如硅、锗、锗硅、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料的层。可以使用的其他衬底包括多层衬底、梯度衬底或混合取向衬底。
包括各种有源器件的第一有源器件和诸如电容器、电阻器、电感器等的无源器件可以用于产生用于第一半导体器件201的设计的期望的结构和功能需求。可以在第一衬底203内或上使用任何合适的方法形成第一有源器件。
第一金属化层205形成在第一衬底203和第一有源器件上方并且被设计为连接各个有源器件以形成功能电路。在实施例中，第一金属化层205由介电材料和导电材料的交替层形成并且可以通过任何适合的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在实施例中，可能存在通过至少一个层间介电层(ILD)与第一衬底203分离的四个金属化层，但是第一金属化层205的精确数目取决于第一半导体器件201的设计。
第一接触焊盘207可以形成在第一金属化层205上方并且与第一金属化层205电接触。第一接触焊盘207可以包括铝，但是可以可选地使用诸如铜的其他材料。第一接触焊盘207的形成方法如下：可以使用诸如溅射的沉积工艺以形成材料层(未示出)和然后可以通过合适的工艺(诸如光刻掩蔽和蚀刻)去除材料层的部分以形成第一接触焊盘207。然而，可以利用任何其他合适的工艺以形成第一接触焊盘207。第一接触焊盘可以形成为具有介于约0.5μm和约4μm之间的厚度，诸如约1.45μm。
可以在第一衬底203上的第一金属层205和第一接触焊盘207上方形成第一钝化层211。第一钝化层211可以由一种或多种合适的介电材料制成，介电材料诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、这些的组合等。第一钝化层211可以通过诸如化学汽相沉积(CVD)的工艺形成，但是可以利用任何合适的工艺，并且第一钝化层211可以具有介于约0.5μm和约5μm之间的厚度，诸如约
可以形成第一外部连接件209以在第一接触焊盘207和例如重分布层501(在图2中未示出，但是结合图5在下文中示出和描述)之间提供接触的导电区。在实施例中，第一外部连接件209可以是导电柱并且可以通过首先在第一钝化层211上方形成具有介于约5μm和约20μm之间的厚度(诸如约10μm)的光刻胶(未示出)来形成。可以图案化光刻胶以暴露第一钝化层211的部分，导电柱将延伸穿过第一钝化层211的暴露部分。一旦被图案化，然后可以将光刻胶用作掩模以去除第一钝化层211的期望部分，从而暴露下面的将与第一外部连接件209接触的第一接触焊盘207的那些部分。
第一外部连接件209可以形成在第一钝化层211和光刻胶的开口内。第一外部连接件209可以由诸如铜的导电材料形成，但是也可以使用诸如镍、金、或金属合金、这些的组合等的其他导电材料。此外，可以使用诸如电镀的工艺形成第一外部连接件209，通过诸如电镀的工艺，电流流经第一接触焊盘207的导电部分，期望第一外部连接件209形成至第一接触焊盘207的导电部分，并且第一接触焊盘207浸没在溶液中。例如，溶液和电流将铜沉积在开口内以填充和/或过填充光刻胶和第一钝化层211的开口，从而形成第一外部连接件209。然后，可以使用例如灰化工艺、化学机械抛光(CMP)工艺、这些的组合等去除位于第一钝化层211的开口的外侧的过量的导电材料和光刻胶。
然而，本领域普通技术人员应当认识到，用于形成第一外部连接件209的上述工艺仅仅是一个这样的描述，而不旨在将该实施例限制于该具体工艺。相反，所描述的工艺预期仅是说明性的，并且可以可选地利用用于形成第一外部连接件209的任何合适的工艺。所有合适的工艺旨在完全包括在本发明的范围内。
管芯附接膜(DAF)217可以放置在第一衬底203的相对侧上以帮助将第一半导体器件201附接至聚合物层105。在实施例中，管芯附接膜217是环氧树脂、酚醛树脂、丙烯酸橡胶、硅胶填料或它们的组合，并且使用层压技术来施加。然而，可以可选地使用任何其他合适的替代材料及其形成方法。
图3示出了将第一半导体器件201放置于聚合物层105上以及第二半导体器件301的放置。在实施例中，第二半导体器件301可以包括第二衬底303、第二有源器件(未单独示出)、第二金属化层305、第二接触焊盘307、第二钝化层311、和第二外部连接件309。在实施例中，第二衬底303、第二有源器件、第二金属化层305、第二接触焊盘307、第二钝化层311、和第二外部连接件309可以类似于第一衬底203、第一有源器件、第一金属化层205、第一接触焊盘207、第一钝化层211、和第一外部连接件209，虽然它们也可能不同。
在实施例中，可以使用例如拾取和放置工艺将第一半导体器件201和第二半导体器件301放置到聚合物层105上。然而，也可以利用放置第一半导体器件201和第二半导体器件301的任何其他方法。
图4示出了通孔111、第一半导体器件201和第二半导体器件301的封装。可以在模制器件(没有在图4中单独示出)中实施该封装，模制器件可以包括顶部模制部分和与顶部模制部分分隔开的底部模制部分。当顶部模制部分降低至邻近底部模制部分时，可以形成用于第一载体衬底101、通孔111、第一半导体器件201和第二半导体器件301的模腔。
在封装工艺期间，可以将顶部模制部分放置为邻近底部模制部分，从而将第一载体衬底101、通孔111、第一半导体器件201和第二半导体器件301封闭在模腔内。一旦封闭，顶部模制部分和底部模制部分可以形成气密密封以控制气体从模腔的流入和流出。一旦密封，密封剂401可以放置在模腔内。密封剂401可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂，这些的组合等。可以在对准顶部模制部分和底部模制部分之前，将密封剂401放置于模腔内，或者可以通过注入端口将密封剂401注入模腔。
一旦已经将密封剂401放置于模腔内，从而使得密封剂401密封第一载体衬底101、通孔111、第一半导体器件201和第二半导体器件301，则可以固化密封剂401以硬化密封剂401，从而用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于密封剂401的特定材料，在将模塑料选择作为密封剂401的实施例中，可以通过诸如将密封剂401加热至介于约100℃和约130℃之间的温度，诸如约125℃，并且持续约60秒至约3000秒，诸如约600秒的工艺进行这种固化。此外，引发剂和/或催化剂可以包括在密封剂401内以更好地控制该固化工艺。
然而，本领域普通技术人员应当意识到，上述固化工艺仅仅是示例性工艺并且不打算限制于当前的实施例。可以可选地使用诸如照射或甚至允许密封剂401在环境温度下固化的其他固化工艺。可以使用任何合适的固化工艺，并且所有这些工艺预期完全包括在本文所讨论的实施例的范围内。
图4也示出了密封剂401的减薄以暴露通孔111、第一半导体器件201和第二半导体器件301以用于进一步处理。例如，可以使用机械研磨或化学机械抛光(CMP)工艺来实施减薄，从而利用化学蚀刻剂和研磨剂以反应和研磨掉密封剂401、第一半导体器件201和第二半导体器件301，直到通孔111、第一外部连接件209(在第一半导体器件201上)和第二外部连接件309(在第二半导体器件301上)已经暴露出来。因此，第一半导体器件201、第二半导体器件301和通孔111可以具有平坦的表面，该平坦的表面也平坦于密封剂401。
然而，虽然上述的CMP工艺表现为一个示例性实施例，但是其不旨在限制于该实施例。可以可选地使用任何其他合适的去除工艺以减薄密封剂401、第一半导体器件201和第二半导体器件301并且暴露通孔111。例如，可以利用一系列的化学蚀刻。该工艺和任何其他合适的工艺可以可选地用于减薄密封剂401、第一半导体器件201和第二半导体器件301，并且所有这些工艺预期完全包括在实施例的范围内。
图5示出了重分布层(RDL)501的形成以使第一半导体器件201、第二半导体器件301、通孔111和第三外部连接件505互连。通过使用RDL 501以互连第一半导体器件201和第二半导体器件301，第一半导体器件201和第二半导体器件301可以具有大于1000的引脚数。
在实施例中，可以通过首先由诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成RDL 501。然后可以形成光刻胶(也未示出)以覆盖晶种层，和然后可以图案化该光刻胶以暴露晶种层的期望RDL 501定位在该位置的那些部分。
一旦已形成和图案化光刻胶，可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。可以形成导电材料以具有介于约1μm和约10μm之间的厚度，诸如约5μm。然而，虽然所论述的材料和方法适合于形成导电材料，这些材料仅仅是示例性的。诸如AlCu或Au的任何其他合适的材料和诸如CVD或PVD的任何其他合适的形成工艺可以用于形成RDL 501。
一旦已经形成导电材料，可以通过诸如灰化的合适的去除工艺去除光刻胶。此外，在去除光刻胶之后，例如，可以通过将导电材料用作掩模的合适的蚀刻工艺去除晶种层的被光刻胶覆盖的那些部分。
图5还示出了在RDL 501上方形成第三钝化层503以向RDL 501和下面的其他结构提供保护和隔离。在实施例中，第三钝化层503可以是聚苯并恶唑(PBO)，但是可以可选地利用诸如聚酰亚胺和聚酰亚胺的衍生物的任何适合的材料。可以使用例如旋涂工艺将第三钝化层503放置为具有介于约5μm和约25μm之间的厚度，诸如约7μm，但是可以可选地使用任何合适的方法和厚度。
在实施例中，从第三钝化层503到聚合物层105的结构的厚度可以小于或等于约200μm。通过使这一厚度尽可能小，整个结构可以用于各种小尺寸应用中，诸如手机等，同时仍然保持期望的功能。然而，本领域普通技术人员将认识到，该结构的精确的厚度可以至少部分地取决于单元的整体设计，因此，可以可选地利用任何合适的厚度。
此外，虽然在图5中仅示出了单个RDL 501，这旨在用于清楚的目的并且不旨在限制实施例。相反，任何合适数量的导电层和钝化层(诸如三个RDL 501层)可以通过重复用于形成RDL 501的以上描述的工艺来形成。可以利用任何合适数量的层。
图5进一步示出了形成第三外部连接件505以制造与RDL 501的电接触。在实施例中，在已经形成第三钝化层503之后，可以通过去除第三钝化层503的部分以暴露下面的RDL501的至少一部分来制造穿过第三钝化层503的开口。开口允许RDL 501和第三外部连接件505之间的接触。可以使用合适的光刻掩模和蚀刻工艺来形成开口，但是可以使用用于暴露RDL 501的部分的任何合适的工艺。
在实施例中，第三外部连接件505可以通过第三钝化层503而放置于RDL 501上并且可以是包括诸如焊料的共晶材料的球栅阵列(BGA)，但是可以可选地使用任何合适的材料。任选地，可以在第三外部连接件505和RDL 501之间利用凸块下金属。在其中第三外部连接件505是焊球的实施例中，可以使用球落方法(诸如直接球落工艺)来形成第三外部连接件505。可选地，可以通过首先通过诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成薄层，和然后实施回流以将材料成形为期望的凸块形状来形成焊球。一旦已经形成第三外部连接件505，可以实施测试以确保该结构适合于进一步处理。
图6A示出了将第一载体衬底101从第一半导体器件201和第二半导体器件301脱粘。在实施例中，第三外部连接件505并且因此，包括第一半导体器件201和第二半导体器件301的结构可以附接至环结构601。环结构601可以是在脱粘工艺期间和之后旨在为该结构提供支撑和稳定性的金属环。在实施例中，例如，使用紫外线胶带603将第三外部连接件505、第一半导体器件201和第二半导体器件301附接至环结构，但是可以可选地使用任何其他合适的粘合剂或附接件。
一旦第三外部连接件505并且因此，包括第一半导体器件201和第二半导体器件301的结构附接至环结构601，可以使用例如热处理以改变粘合层103的粘合性能来将第一载体衬底101与包括第一半导体器件201和第二半导体器件301的结构脱粘。在特定实施例中，利用诸如紫外线(UV)激光、二氧化碳(CO2)激光或红外线(IR)激光的能量源来照射和加热粘合层103，直到粘合层103失去它的至少一些粘合性能。一旦实施，则第一载体衬底101和粘合层103可以物理分离并且从包括第三外部连接件505、第一半导体器件201和第二半导体器件301的结构去除。
图6B示出了用于将第一载体衬底101从第一半导体器件201和第二半导体器件301脱粘的另一实施例。在本实施例中，例如，使用第一胶607可以将第三外部连接件505附接至第二载体衬底605。在实施例中，第二载体衬底605类似于第一载体衬底101，但是其也可以是不同的。一旦附接，可照射粘合层103并且可以物理地去除粘合层103和第一载体衬底101。
返回其中利用环结构601的实施例，图7A示出了图案化聚合物层105以暴露通孔111(连同相关的第一晶种层107)。在实施例中，例如，可以使用激光钻孔方法图案化聚合物层105。在这种方法中，首先在聚合物层105上方沉积诸如光热转换(LTHC)层或水溶性保护膜(hogomax)层(在图7A中未单独示出)的保护层。一旦保护，将激光导向聚合物层105的期望被去除的部分以暴露下面的通孔111。在激光钻孔工艺期间，钻孔能量可以在从0.1mJ至约30mJ的范围内，以及相对于聚合物层105的法线的约0度(垂直于聚合物层105)至约85度的钻孔角。在实施例中，可以实施图案化以在通孔111上方形成第一开口703，第一开口703具有介于约100μm和约300μm之间的第一宽度，诸如约200μm。
在另一个实施例中，可以通过首先对聚合物层105施加光刻胶(未单独在图7A中示出)和然后将光刻胶暴露于图案化的能量源(例如，图案化的光源)以引发化学反应，从而引发光刻胶的暴露于图案化的光源的那些部分中的物理变化来图案化聚合物层105。然后对曝光的光刻胶施加显影剂以利用物理变化并且取决于所期望的图案而选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分，并且例如，通过干蚀刻工艺去除下面的聚合物层105的暴露部分。然而，可以利用用于图案化聚合物层105的任何其他合适的方法。
图7B示出了可以用于暴露通孔111以用于进一步连接的另一实施例。在本实施例中，去除整个聚合物层105以暴露通孔111(和相关联的第一晶种层107)。在实施例中，聚合物层105的去除可以使用例如回蚀刻工艺来实施，由此，蚀刻剂用于去除聚合物层105直到已经暴露出通孔111。例如，在其中聚合物层105是PBO的实施例中，蚀刻剂可以用于湿蚀刻工艺中以去除聚合物层105。
然而，本领域普通技术人员应当认识到，上述的湿蚀刻工艺旨在是说明性的并且不旨在限制实施例。相反，可以使用诸如化学机械抛光或低脱粘能量工艺(这可能导致LTHC层的一部分保留在聚合物层105上)、无水溶性保护膜(hogomax)工艺的任何合适的去除工艺以节约与保护层相关的成本。所有这些工艺预期完全包括在该实施例的范围内。
现在回到参考图7A论述的实施例，图8示出了将背侧球焊盘801放置于第一开口703内以保护现在暴露的通孔111。在实施例中，背侧球焊盘801可以包括诸如膏上焊料或氧焊料保护(OSP)的导电材料，但是可以可选地利用任何合适的材料。在实施例中，可以使用模板来施加背侧球焊盘801，但是可以可选地利用任何合适的施加方法，和然后回流以形成凸块形状。
图8还示出了可以对背侧球焊盘801实施的任选的平齐或压印工艺。在实施例中，例如，可以使用放置在每个背侧球焊盘801周围的模板和施加压力的按压使背侧球焊盘801的部分物理变形和使背侧球焊盘801的顶面平坦来物理成形背侧球焊盘801。
图9示出了在背侧球焊盘801上方的背侧保护层901的放置和图案化，背侧保护层901有效地密封背侧球焊盘801和通孔111之间的接合点免受湿气的侵入。在实施例中，背侧保护层901可以是诸如PBO、阻焊剂(SR)、层压复合(LC)胶带、味之素构建膜(ABF)、非导电膏(NCP)、非导电膜(NCF)、图案化的底部填充物(PUF)、翘曲改进粘合剂(WIA)、液体模塑料V9、这些的组合等的保护材料。然而，也可以使用任何适合的材料。可以使用诸如丝网印刷、层压、旋涂等的工艺施加具有约1μm至约200μm之间的厚度的背侧保护层901。
图9也示出了一旦已经放置背侧保护层901，可以图案化背侧保护层901以暴露背侧球焊盘801。在实施例中，例如，可以使用激光钻孔方法图案化背侧保护层901，通过激光钻孔方法，将激光导向背侧保护层901的期望被去除以暴露背侧球焊盘801的那些部分。在激光钻孔工艺期间，钻孔能量可以在从0.1mJ至约30mJ的范围内，以及相对于背侧保护层901的法线的约0度(垂直于背侧保护层901)至约85度的钻孔角。在实施例中，可以实施图案化以在背侧球焊盘801上方形成第二开口903，并且第二开口903可以形成为具有介于约30μm和约300μm之间的直径，诸如约150μm。
在另一个实施例中，可以通过首先对背侧保护层901施加光刻胶(未单独在图9中示出)和然后将光刻胶暴露于图案化的能量源(例如，图案化的光源)以引发化学反应，从而引发光刻胶的暴露于图案化的光源的那些部分中的物理变化来图案化背侧保护层901。然后对曝光的光刻胶施加显影剂以利用物理变化并且取决于所期望的图案而选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分，并且例如，通过干蚀刻工艺去除下面的背侧保护层901的暴露部分。然而，可以利用用于图案化背侧保护层901的任何其他合适的方法。
通过利用光刻工艺以图案化背侧保护层901，可以控制第二开口903的形状。例如，通过使用光刻工艺，可以控制在形成第二开口903期间形成的侧壁以具有大于75°的第一角α1。这允许背侧保护层901保持有效密封背侧球焊盘801，同时仍然允许背侧球焊盘801与其他结构之间的有效连接。
图10示出了背侧球焊盘801至第一封装件1000的接合。在实施例中，第一封装件1000可以包括第三衬底1003、第三半导体器件1005、第四半导体器件1007(接合至第三半导体器件1005)、第三接触焊盘1009、第二密封剂1011以及第四外部连接件1013。在实施例中，第三衬底1003可以是例如封装衬底，封装衬底包括内部互连件(例如，衬底通孔1015)以将第三半导体器件1005和第四半导体器件1007连接至背侧球焊盘801。
可选地，第三衬底1003可以是用作中间衬底的中介板以将第三半导体器件1005和第四半导体器件1007连接至背侧球焊盘801。在这个实施例中，第三衬底1003可以是例如掺杂或未掺杂的硅衬底，或者绝缘体上硅(SOI)衬底的有源层。然而，第三衬底1003可以可选地为玻璃衬底、陶瓷衬底、聚合物衬底、或可以提供合适的保护和/或互连功能的任何其他衬底。这些和任何其他适用的材料可以可选地用于第三衬底1003。
第三半导体器件1005可以是设计为用于预期目的的半导体器件，诸如为逻辑管芯、中央处理单元(CPU)管芯、存储管芯、(例如，DRAM管芯)、这些的组合等。在实施例中，第三半导体器件1005包括根据期望用于特定功能的集成电路器件，诸如晶体管、电容器、电感器、电阻器、第一金属化层(未示出)等。在实施例中，第三半导体器件1005被设计和制造为与第一半导体器件201一起或同时工作。
第四半导体器件1007可以类似于第三半导体器件1005。例如，第四半导体器件1007可以是设计为用于预期目的(例如，DRAM管芯)并且包括集成电路器件的半导体器件以用于期望功能。在实施例中，第四半导体器件1007被设计为与第一半导体器件201和/或第三半导体器件1005一起或同时工作。
第四半导体器件1007可以接合至第三半导体器件1005。在实施例中，第四半导体器件1007与第三半导体器件1005仅物理接合，诸如通过使用粘合剂。在这个实施例中，第四半导体器件1007和第三半导体器件1005可以使用例如引线接合件1017电连接至第三衬底1003，但是可以可选地利用任何合适的电接合。
可选地，第四半导体器件1007可以物理和电接合至第三半导体器件1005。在这个实施例中，第四半导体器件1007可以包括与第三半导体器件1005上的第五外部连接件(未在图10中单独示出)连接的第四外部连接件(也未在图10中单独示出)以将第四半导体器件1007与第三半导体器件1005互连。
第三接触焊盘1009可以形成在第三衬底1003上以在第三半导体器件1005和例如第四外部连接件1013之间形成电连接。在实施例中，第三接触焊盘1009可以形成在第三衬底1003内的电气布线(诸如衬底通孔1015)上方并且与电气布线电接触。第三接触焊盘1009可以包括铝，但是可以可选地使用诸如铜的其他材料。第三接触焊盘1009的形成可以包括：可以使用诸如溅射的沉积工艺以形成材料(未示出)层和然后通过合适的工艺(诸如光刻掩蔽和蚀刻)去除材料层的部分以形成第三接触焊盘1009。然而，可以利用任何其他合适的工艺以形成第三接触焊盘1009。第三接触焊盘1009可以形成为具有介于约0.5μm和约4μm之间的厚度，诸如约1.45μm。
第二密封剂1011可以用于封装和保护第三半导体器件1005、第四半导体器件1007和第三衬底1003。在实施例中，第二密封剂1011可以是模塑料并且可以使用模制器件(未在图10中示出)来布置。例如，可以将第三衬底1003、第三半导体器件1005和第四半导体器件1007放置在模制器件的腔体内，并且腔体可以气密地密封。可以在气密地密封腔体之前将第二密封剂1011放置在腔体内或者可以通过注入端口将第二密封剂1011注入腔体内。在实施例中，第二密封剂1011可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。
一旦第二密封剂1011已被放置在腔体内，从而使得第二密封剂1011封装第三衬底1003、第三半导体器件1005和第四半导体器件1007周围的区域，则可以固化第二密封剂1011以硬化第二密封剂1011以用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于第二密封剂1011的特定材料，在将模塑料选择作为第二密封剂1011的实施例中，可以通过诸如将第二密封剂1011加热至介于约100℃和约130℃之间的温度，诸如约125℃，并且持续约60秒至约3000秒，诸如约600秒的工艺进行这种固化。此外，引发剂和/或催化剂可以包括在第二密封剂1011内以更好地控制该固化工艺。
然而，本领域普通技术人员应当意识到，上述固化工艺仅仅是示例性工艺并且不打算限制于当前的实施例。可以可选地使用诸如照射或甚至允许第二密封剂1011在环境温度下硬化的其他固化工艺。可以使用任何合适的固化工艺，并且所有这些工艺预期完全包括在本文所讨论的实施例的范围内。
在实施例中，可以形成第四外部连接件1013以提供第三衬底1003和例如背侧球焊盘801之间的外部连接。第四外部连接件1013可以是诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块并且可以包括诸如锡的材料、或者诸如银或铜的其他合适的材料。在第四外部连接件1013是锡焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球放置等的任何合适的方法来形成例如厚度为约100μm的薄层来形成第四外部连接件1013。一旦已经在结构上形成薄层，实施回流以将材料成形为期望的凸块形状。
一旦已经形成第四外部连接件1013，第四外部连接件1013与背侧球焊盘801对准且放置为与背侧球焊盘801物理接触，并且实施接合。例如，在第四外部连接件1013是焊料凸块的实施例中，接合工艺可以包括回流工艺，从而第四外部连接件1013的温度升高至第四外部连接件1013将液化并且流动的点，从而当第四外部连接件1013重新固化时，将第一封装件1000接合至背侧球焊盘801。
图10还示出了将第二封装件1019接合至背侧球焊盘801。在实施例中，第二封装件1019可以类似于第一封装件1000，并且可以利用类似的工艺接合至背侧球焊盘801。然而，第二封装件1019也可以与第一封装件1000不同。
图11示出了第三外部连接件505从环结构601的脱粘和结构的分割以形成第一集成扇出叠层封装(InFO-POP)结构。在实施例中，可以通过首先使用例如第二紫外线胶带将第一封装件1000和第二封装件1019接合至第二环结构，来将第三外部连接件505从环结构601脱粘。一旦接合，可以利用紫外线辐射来照射紫外线胶带603，一旦紫外线胶带603失去其粘合性能，第三外部连接件505可以与环结构601物理分离。
一旦脱粘，实施结构的分割以形成第一InFO-POP结构1100。在实施例中，可以通过使用锯片(未示出)来切割穿通孔111之间的密封剂401和聚合物层105来实施分割，从而将将一部分与另一部分分离以形成具有第一半导体器件201的第一InFO-POP结构1100。然而，本领域普通技术人员应当认识到，利用锯片以分割第一InFO-POP结构1100仅仅是一个示例性实施例，并且不旨在限制。可以可选地利用诸如利用一次或多次蚀刻以分离第一InFO-POP结构1100的用于分割第一InFO-POP结构1100的可选方法。可以可选地利用这些方法和任何其他合适的方法以分割第一InFO-POP结构1100。
如上所述，通过在背侧球焊盘801上方形成背侧保护层901和然后开口背侧保护层901，可以降低或消除渗透至背侧球焊盘801和下面的结构(例如，通孔111)之间的界面内的湿气。特别地，可以消除由使用激光钻孔以形成大开口和然后试图以球接头(ball joint)填充该开口引发的问题。因此，也可以减少或消除由背侧连接引起的分层和可靠性故障。此外，也可以避免由于水渗透引起的通孔111的铜氧化。
所有这些都允许可以避免其他保护结构。在特定实施例中，通过防止水渗透和其他可靠性故障，为了保护该结构，不一定需要诸如底部填充物的结构。不需要底部填充物，可以避免底部填充物，从而也允许可以避免高成本的底部填充材料和分配。这导致了更有效的工艺和更廉价的整个器件。
图12示出了其中背侧球焊盘801从背侧保护层901延伸的另一实施例。在这个实施例中，在聚合物层105的图案化(以上结合图7A进行描述)之后，在聚合物层105的第一开口703中放置和回流背侧球焊盘801。如结合图8的以上描述，可以形成背侧球焊盘801。然而，在这个实施例中，背侧球焊盘801形成为具有介于约10μm和约100μm之间的第一高度H1，诸如约20μm。
一旦已经形成背侧球焊盘801，背侧保护层901可以形成在聚合物层105上方以及背侧球焊盘801之间，并且至少部分地形成在背侧球焊盘801的一部分上方。在实施例中，如结合图9的以上描述，可以形成背侧保护层901。然而，在这个实施例中，背侧保护层901可以形成为具有低于背侧球焊盘801的顶面。例如，在背侧球焊盘801具有约20μm的第一高度H1的实施例中，背侧保护层901可以具有介于约10μm和约80μm之间的第二高度H2，诸如约40μm。
图13A示出了在这一实施例中的用于形成第一InFO-POP结构1100的剩余工艺。特别地，第一封装件1000的第四外部连接件1013与背侧球焊盘801对准并且接合至背侧球焊盘801，并且从剩余的结构分割第一InFO-POP结构1100。在实施例中，如结合图10至图11的以上描述，实施接合和分割，但是可以利用任何合适的方法。
图13B示出了在图13A示出的实施例中的背侧球焊盘801和第四外部连接件1013之间的实际接合的放大图。考虑到在放置背侧球焊盘801之后，形成背侧保护层901，背侧保护层901将实际上形成在背侧球焊盘801和第四外部连接件1013之间延伸的颈部(在图13B中通过圆形虚线1305标注)。
通过利用其中背侧球焊盘801从背侧保护层901延伸的实施例，不需要形成穿过背侧保护层901的第二开口903的激光钻孔工艺或光刻工艺。因此，可以避免这些工艺。
图14示出了其中背侧球焊盘801从背侧保护层901延伸，但是不存在聚合物层105的另一个实施例。在这个实施例中，如结合图7B的以上描述，在去除聚合物层105之后，如结合图12的以上描述，可以形成背侧球焊盘801并且背侧球焊盘801与通孔111(包括第一晶种层107)直接接触。此外，背侧球焊盘801形成为具有介于约10μm和约100μm之间的第一高度H1，诸如约20μm。
一旦已经形成背侧球焊盘801，可以形成与密封剂401(因为聚合物层105已被去除)直接接触的背侧保护层901。在实施例中，如结合图12的以上描述，可以形成背侧保护层901，背侧保护层901形成为具有低于背侧球焊盘801的顶面，诸如通过具有第二高度H2。
图15示出了在这个实施例中的用于形成第一InFO-POP结构1100的剩余工艺。特别地，第一封装件1000的第四外部连接件1013与背侧球焊盘801对准并且接合至背侧球焊盘801，并且从剩余的结构分割第一InFO-POP结构1100。在实施例中，如结合图10至图11的以上描述，实施接合和分割，但是可以利用任何合适的方法。
通过在形成背侧球焊盘801之前去除聚合物层105，在其他实施例中利用的激光钻孔工艺是不必须的。因此，可以避免激光钻孔工艺的成本和复杂性，并且可以实现由激光钻孔工艺引起的损坏的减少。
图16示出了其中利用一个或多个背侧重分布层(RDL)1601的另一个实施例。在这个实施例中，在已经去除密封剂401以暴露通孔111之后，背侧RDL 1601可以形成为与现在暴露的通孔111电连接并且形成在第一半导体器件201上方。在实施例中，可以通过首先由诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成背侧RDL 1601。然后可以形成光刻胶(也未示出)以覆盖晶种层，并且然后可以图案化该光刻胶以暴露晶种层的位于期望背侧RDL 1601定位的位置的那些部分。
一旦已形成并且图案化光刻胶，可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有介于约1μm和约10μm之间的厚度，诸如约5μm。然而，所论述的材料和方法适合于形成导电材料，这些材料仅仅是示例性的。可以可选地使用诸如AlCu或Au的任何其他合适的材料，以及诸如CVD或PVD的任何其他合适的形成工艺以形成背侧RDL 1601。
一旦已经形成导电材料，可以通过诸如灰化的合适的去除工艺去除光刻胶。此外，在去除光刻胶之后，例如，可以通过将导电材料用作掩模的合适的蚀刻工艺去除晶种层的被光刻胶覆盖的那些部分。
图16也示出了在背侧RDL 1601上方形成第四钝化层1603以为背侧RDL 1601和下面的其他结构提供保护和隔离。在实施例中，第四钝化层1603可以是聚苯并恶唑(PBO)，但是可以可选地利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何合适的材料。可以使用例如旋涂工艺将第四钝化层1603放置为具有约5μm和约25μm之间的厚度，诸如约7μm，但是可以可选地使用任何合适的方法和厚度。
通过利用背侧RDL 1601，背侧球焊盘801的精确放置不需要直接位于通孔111上方。相反，可以根据整体设计的期望设置背侧球焊盘801。因此，可以实现更有效和更小的器件。此外，通过利用本文中描述的实施例，通过密封接合点来防止湿气的入侵，可以减少或消除背侧RDL 1601的分层。
图17A示出了另一个实施例，其中，利用上文结合图13A描述的实施例以及背侧RDL 1601。此外，图17B示出了背侧球焊盘801和第四外部连接件1013之间的接合的放大图。如上文结合图13B论述的实施例，因为在放置背侧保护层901之前形成背侧球焊盘801，背侧保护层901将实际上在背侧球焊盘801和第四外部连接件1013之间延伸以形成第二颈部(在图17B中示出，位于圆形虚线标记1701内)。该颈部帮助密封背侧球焊盘801，从而使得湿气不能渗透。此外，虽然在图17A的实施例内描述该颈部，也可以在形成背侧球焊盘801之后形成背侧保护层901的其他实施例中发现该颈部。
图18示出了另一个实施例，其中，在已经去除聚合物层105之后形成背侧RDL 1601。在这个实施例中，在已经去除聚合物层105之后(如结合图7B的以上描述)，可以在形成背侧球焊盘801和背侧保护层901之前形成背侧RDL 1601。通过形成背侧RDL 1601，背侧球焊盘801可以放置在任何期望的位置。
根据一个实施例，提供了一种半导体器件，该半导体器件包括：通过密封剂封装的第一半导体管芯。通孔延伸穿过密封剂并且与第一半导体管芯横向分隔开。第一可回流导电材料与通孔电连接；以及保护层至少部分地位于第一可回流导电材料和第一半导体管芯上方，其中，保护层具有暴露第一可回流导电材料的开口。
根据另一个实施例，提供了一种半导体器件，该半导体器件包括：延伸穿过密封剂的第一通孔和延伸穿过密封剂的第一半导体管芯，其中，密封剂的至少一部分位于第一通孔和第一半导体管芯之间。保护层位于第一通孔和第一半导体管芯上方，保护层具有垂直于第一半导体管芯的主要表面的第一高度。第一可回流材料延伸穿过保护层，第一可回流材料具有垂直于第一半导体管芯的主要表面的第二高度，第二高度大于第一高度。
根据又一个实施例，提供了一种制造半导体器件的方法，该方法包括：将第一半导体管芯和通孔封装在密封剂内，其中，封装将密封剂的至少一部分放置在第一半导体管芯和通孔之间。放置与通孔电接触的第一可回流材料；以及在放置第一可回流材料之后，通过形成保护层来密封第一可回流材料的至少一部分，其中，第一可回流材料通过保护层暴露。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
第一半导体管芯，通过密封剂封装；
通孔，延伸穿过所述密封剂并且与所述第一半导体管芯横向分隔开；
第一可回流导电材料，与所述通孔电连接；以及
保护层，至少部分地位于所述第一可回流导电材料和所述第一半导体管芯上方，其中，所述保护层具有暴露所述第一可回流导电材料的开口。
2.根据权利要求1所述的半导体器件，还包括：
重分布层，位于所述通孔和所述第一可回流导电材料之间。
3.根据权利要求1所述的半导体器件，其中，所述开口的侧壁具有至少75°的角。
4.根据权利要求1所述的半导体器件，还包括：
聚合物层，位于所述第一半导体管芯和所述保护层之间。
5.根据权利要求1所述的半导体器件，还包括：
第二可回流导电材料，延伸穿过所述开口并且与所述第一可回流导电材料物理接触。
6.根据权利要求1所述的半导体器件，其中，所述保护层是阻焊剂(SR)、层压复合(LC)胶带、味之素构建膜(ABF)、非导电膏(NCP)、非导电膜(NCF)、图案化的底部填充物(PUF)或翘曲改进粘合剂(WIA)。
7.根据权利要求1所述的半导体器件，其中，所述保护层与邻近所述第一半导体管芯的管芯附接膜物理接触。
8.一种半导体器件，包括：
第一通孔，延伸穿过密封剂；
第一半导体管芯，延伸穿过所述密封剂，所述密封剂的至少一部分位于所述第一通孔和所述第一半导体管芯之间；
保护层，位于所述第一通孔和所述第一半导体管芯上方，所述保护层具有垂直于所述第一半导体管芯的主要表面的第一高度；以及
第一可回流材料，延伸穿过所述保护层，所述第一可回流材料具有垂直于所述第一半导体管芯的主要表面的第二高度，所述第二高度大于所述第一高度。
9.根据权利要求8所述的半导体器件，还包括：
聚合物层，位于所述保护层和所述第一半导体管芯之间。
10.一种制造半导体器件的方法，所述方法包括：
将第一半导体管芯和通孔封装在密封剂内，其中，所述封装将所述密封剂的至少一部分放置在所述第一半导体管芯和所述通孔之间；
放置与所述通孔电接触的第一可回流材料；以及
在放置所述第一可回流材料之后，通过形成保护层来密封所述第一可回流材料的至少一部分，其中，所述第一可回流材料通过所述保护层暴露。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110060935A (zh) * 2018-01-19 2019-07-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN110660725A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 具有可控间隙的扇出封装件

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9633934B2 (en) 2014-11-26 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semicondutor device and method of manufacture
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
US9553036B1 (en) * 2015-07-09 2017-01-24 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
CN113257766A (zh) * 2015-08-21 2021-08-13 意法半导体有限公司 半导体装置及其制造方法
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10553542B2 (en) 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
KR20180117238A (ko) * 2017-04-18 2018-10-29 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017126028B4 (de) 2017-06-30 2020-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gehäuse und Herstellungsverfahren mit einem Trennfilm als Isolierfilm
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10504865B2 (en) * 2017-09-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10515901B2 (en) * 2017-09-29 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. InFO-POP structures with TIVs having cavities
DE102018111389A1 (de) 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung und Herstellungsverfahren
US10586763B2 (en) * 2017-11-15 2020-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
KR102633142B1 (ko) 2019-08-26 2024-02-02 삼성전자주식회사 반도체 패키지
US11830821B2 (en) * 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
KR20220164112A (ko) 2021-06-03 2022-12-13 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1738017A (zh) * 2004-08-17 2006-02-22 三星电子株式会社 半导体器件的电极结构及其制造方法
CN101308803A (zh) * 2007-05-16 2008-11-19 英飞凌科技股份有限公司 半导体器件
US20120208319A1 (en) * 2010-03-31 2012-08-16 Infineon Technologies Ag Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
CN104051383A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5634268A (en) * 1995-06-07 1997-06-03 International Business Machines Corporation Method for making direct chip attach circuit card
TW434848B (en) 2000-01-14 2001-05-16 Chen I Ming Semiconductor chip device and the packaging method
KR20080031522A (ko) * 2000-02-25 2008-04-08 이비덴 가부시키가이샤 다층프린트배선판 및 다층프린트배선판의 제조방법
CN1163960C (zh) 2000-12-13 2004-08-25 矽品精密工业股份有限公司 具有高散热性的超薄封装件及其制造方法
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US8349276B2 (en) 2002-09-24 2013-01-08 Duke University Apparatuses and methods for manipulating droplets on a printed circuit board
TWI278048B (en) 2003-11-10 2007-04-01 Casio Computer Co Ltd Semiconductor device and its manufacturing method
JP4303563B2 (ja) 2003-11-12 2009-07-29 大日本印刷株式会社 電子装置および電子装置の製造方法
US7176152B2 (en) 2004-06-09 2007-02-13 Ferro Corporation Lead-free and cadmium-free conductive copper thick film pastes
DE102005040213A1 (de) 2004-08-17 2006-03-09 Samsung Electronics Co., Ltd., Suwon Halbleiterbauelement mit Elektrode und Herstellungsverfahren
DE102005043557B4 (de) 2005-09-12 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite
US8072059B2 (en) 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7518229B2 (en) 2006-08-03 2009-04-14 International Business Machines Corporation Versatile Si-based packaging with integrated passive components for mmWave applications
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
DE102006062473A1 (de) 2006-12-28 2008-07-03 Qimonda Ag Halbleiterbauelement mit auf einem Substrat montiertem Chip
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
KR101348748B1 (ko) 2007-08-24 2014-01-08 삼성전자주식회사 재배선 기판을 이용한 반도체 패키지 제조방법
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US7863755B2 (en) 2008-03-19 2011-01-04 Stats Chippac Ltd. Package-on-package system with via Z-interconnections
JPWO2009147936A1 (ja) * 2008-06-02 2011-10-27 イビデン株式会社 多層プリント配線板の製造方法
US8039303B2 (en) 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
EP2487710B1 (en) 2009-10-09 2015-11-25 Toyota Jidosha Kabushiki Kaisha Semiconductor device manufacturing method
US8058102B2 (en) 2009-11-10 2011-11-15 Advanced Chip Engineering Technology Inc. Package structure and manufacturing method thereof
CN101930990B (zh) 2010-03-09 2013-08-07 电子科技大学 一种有源驱动有机电致发光器件及其制备方法
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
KR101390628B1 (ko) 2010-11-15 2014-04-29 유나이티드 테스트 엔드 어셈블리 센터 엘티디 반도체 패키지 및 반도체 소자 패키징 방법
KR101715761B1 (ko) 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR20120091691A (ko) 2011-02-09 2012-08-20 삼성전자주식회사 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법
KR101207882B1 (ko) 2011-03-07 2012-12-04 (주)윈팩 패키지 모듈
JP2012199494A (ja) 2011-03-23 2012-10-18 Teramikros Inc 半導体装置の製造方法及び半導体装置の実装構造の製造方法
US8530277B2 (en) 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US8569884B2 (en) 2011-08-15 2013-10-29 Tessera, Inc. Multiple die in a face down package
KR101257218B1 (ko) 2011-09-30 2013-04-29 에스티에스반도체통신 주식회사 패키지 온 패키지 및 이의 제조방법
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
KR101411741B1 (ko) 2011-11-11 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9412689B2 (en) 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
US8928128B2 (en) 2012-02-27 2015-01-06 Broadcom Corporation Semiconductor package with integrated electromagnetic shielding
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US20130297981A1 (en) 2012-05-01 2013-11-07 Qualcomm Incorporated Low cost high throughput tsv/microbump probe
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
JP5903337B2 (ja) * 2012-06-08 2016-04-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8866285B2 (en) 2012-09-05 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package comprising bulk metal
US8889484B2 (en) 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US8952521B2 (en) 2012-10-19 2015-02-10 Infineon Technologies Ag Semiconductor packages with integrated antenna and method of forming thereof
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9633934B2 (en) 2014-11-26 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semicondutor device and method of manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1738017A (zh) * 2004-08-17 2006-02-22 三星电子株式会社 半导体器件的电极结构及其制造方法
CN101308803A (zh) * 2007-05-16 2008-11-19 英飞凌科技股份有限公司 半导体器件
US20120208319A1 (en) * 2010-03-31 2012-08-16 Infineon Technologies Ag Packaged Semiconductor Device with Encapsulant Embedding Semiconductor Chip that Includes Contact Pads
CN103972191A (zh) * 2013-01-31 2014-08-06 台湾积体电路制造股份有限公司 具有环绕封装通孔端部的开口的管芯封装件及层叠封装件
CN104051383A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 封装的半导体器件、封装半导体器件的方法以及PoP器件

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110060935A (zh) * 2018-01-19 2019-07-26 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US11646256B2 (en) 2018-01-19 2023-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
CN110060935B (zh) * 2018-01-19 2023-08-18 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN110660725A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 具有可控间隙的扇出封装件
US11075151B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
CN110660725B (zh) * 2018-06-29 2022-04-01 台湾积体电路制造股份有限公司 具有可控间隙的扇出封装件
US11854955B2 (en) 2018-06-29 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff

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US20160218049A1 (en) 2016-07-28
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US9583420B2 (en) 2017-02-28
TW201639112A (zh) 2016-11-01
US10103132B2 (en) 2018-10-16
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KR20160091211A (ko) 2016-08-02
TWI593082B (zh) 2017-07-21

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