CN101308803A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101308803A
CN101308803A CNA2008100981399A CN200810098139A CN101308803A CN 101308803 A CN101308803 A CN 101308803A CN A2008100981399 A CNA2008100981399 A CN A2008100981399A CN 200810098139 A CN200810098139 A CN 200810098139A CN 101308803 A CN101308803 A CN 101308803A
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Prior art keywords
semiconductor
hole
semiconductor chip
carrier
molding bed
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CNA2008100981399A
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CN101308803B (zh
Inventor
马库斯·布伦鲍尔
延斯·波赫
赖纳·施泰纳
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from DE102007022959A external-priority patent/DE102007022959B4/de
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明公开了一种半导体器件及其制造方法。在一个实施例中，该方法包括将第一半导体放置在导电载体上。第一半导体被模塑料覆盖。通孔在模塑料中形成。将第一材料沉积在通孔中。

Description

半导体器件
技术领域
本发明涉及半导体器件及半导体器件的制造方法。
背景技术
对于复杂的系统集成，将集成电路、传感器、微机械器件或其他器件层叠在彼此顶部是有用的。为了能够电连接所层叠的器件，对于至少某些层叠器件而言，设置从其顶面至其底面的导电的穿通(feedthrough)是有用的。
由于这些以及其他原因，本发明是有必要的。
发明内容
根据本发明的一个方面提供了一种制造半导体器件的方法，包括：将第一半导体放置在导电载体上；用模塑料覆盖第一半导体；在模塑料上形成通孔；以及在通孔中沉积第一材料。
根据本发明的另一方面提供了一种器件，包括：半导体芯片；模塑料层，支撑半导体芯片；导电层，被施加至模塑料层；通孔，设置在模塑料层中；以及第一导电材料，布置在所述通孔中并且与所述模塑料层接触。
根据本发明的又一方面提供了一种布置，包括：半导体，该半导体包括第一半导体芯片、支撑半导体芯片的模塑料层、施加至模塑料层的导电层、设置在模塑料层中的通孔、以及布置在通孔中并且与模塑料层接触的第一导电材料；以及第二半导体芯片，其中本器件与第二半导体芯片叠放在彼此上。
附图说明
附图被包括以提供对本发明进一步理解并且并入本说明书且构成本说明书的一部分。附图示出本发明的实施例，并与说明结合在一起以用作解释本发明的原理。本发明的其他实施方式以及许多本发明的预期的优势当通过参照以下的详细描述而变得较容易理解时就会被容易地理解。附图中的元件并不需要相对于彼此按比例绘制。相似的参考标号指出对应的相似部件。
图1A到1D示意性地示出了制造作为示例性实施例的器件的方法。
图2A到2I示意性地示出了制造作为又一示例性实施例的器件的方法。
图3A到3F示意性地示出了制造作为另一示例性实施例的器件的方法。
图4示意性示出了层叠在作为示例性实施例的器件的顶部上的器件。
具体实施方式
在以下的详细说明中，将参照构成附图，附图构成说明的一部分，并且在附图中本发明可以在其中实施的具体实施例通过图解的方式示出。在此，参照图中被描述的方位，使用诸如“顶部”、“底部”、“前面”、“背面”、“前列的”、“尾随的”等的方向术语。由于本发明实施例的组件可以沿多个不同的方位放置，因此方向术语是为了解释而不是限定的目的而使用。应该理解，在不背离本发明范围的前提下，可以采用其他实施方式并且可以进行结构或者逻辑变化。因此，以下的详细描述并不是限制性的，且本发明的范围通过所附权利要求来限定。
以下将描述具有嵌入模塑料(molding compound)中的半导体芯片的器件。半导体芯片可以是非常不同的类型且可以包括例如集成电子电路或集成光电电路。半导体芯片可以被设置成MEMS(微电机系统)并且可以包括微机械结构，诸如电桥、膜片或舌片(tongue)结构。半导体芯片可以被设置成传感器或致动器，例如压力传感器、加速度传感器、转动传感器、麦克风等。其中嵌入了这些功能元件半导体芯片一般包括用作驱动功能元件或进一步处理由功能元件产生的信号的电子电路。半导体芯片不需要用特殊的半导体材料制造，而且可以包括并非半导体的无机和/或有机材料，诸如绝缘体，塑料或金属。此外，半导体芯片即可以封装也可以不封装。
半导体芯片具有接触盘(contact)，该接触盘允许与半导体芯片的电接触。接触盘可以由所需的导电性材料制成，例如金属(诸如铝、金或铜)、金属合金或导电有机材料。接触盘可定位于半导体芯片的活性表面上或在半导体芯片的其他表面上。
可以将一个或多个布线层(wiring layer)应用于半导体芯片。布线层可以用来从器件的外侧与半导体芯片电接触。布线层可以以任何所需的几何形状以及任何所需的材料组分来制造。布线层可以例如由线性导体轨道构成，但也可以是由覆盖一区域的层的形式。可以用任何所需导电性材料作为制造材料，诸如金属(例如铝、金或铜)、金属合金或导电有机物。布线层不需是同质的或由仅仅一种材料制造，即，包含在布线层中的材料的各种组成与集成都是可能的。另外，布线层可以布置在电介质层之上或之下或之间。
以下描述的器件包括覆盖至少一部分半导体芯片的模塑料。模塑料可以是任何适合的热塑性或热硬性材料。可采用多种技术利用模塑料覆盖半导体芯片，例如压缩模塑法或喷射模塑法。
图1A到1D示意性地示出了一种制造器件100的方法，图1D中示出了该器件100的横截面。如图1A所示，将第一半导体芯片1放置在导电载体2之上。用模塑料3覆盖第一半导体芯片1(图1B示出)。在模塑料3中形成通孔4(图1C示出)，且在通孔4中沉积第一材料5(图1D示出)。第一材料5例如可以是金属且可以电(galvanically)沉积在通孔4中。在电沉积第一材料5的过程中，导电载体2可作为电极。第一材料5可以完全或部分地填充通孔4。
图2A到2I示意性地示出了一种器件200的制造方法，图2I中示出了该器件200的横截面。图2A到2I中所示的方法是对图1A到1D中所示方法的改进。因此下述制造方法的详细说明同样可应用于图1A到1D中的方法。
如图2A所示，将第一半导体芯片1和第二半导体芯片6以及可能的其他半导体芯片放置在导电载体2之上。载体2可以是由金属制成的板，例如镍、钢或不锈钢。半导体芯片1和6可以在由半导体材料所制的晶片上制造。在划分晶片从而分开单个的半导体芯片1和6之后，当半导体芯片1和6处于片结合状态时，以更大的间隔将它们重新放置在载体2上。半导体芯片1和6可以在相同的晶片上制造，但可选择地，也可以在不同的晶片上制造。此外，半导体芯片1和6可以是物理上相同的，但也可以包括不同的集成电路。半导体芯片1和6各自具有活性主表面7和8，并且可以以它们的活性表面7和8面向载体2的方式而布置在在载体2上。
在将半导体芯片1和6放置在载体2上之前，可以将胶带9(例如双面胶带)覆盖在载体2上。可以将半导体芯片1和6固定在胶带9上。为了将半导体芯片1和6贴到载体2上，可以选用其他种类的粘贴材料。
在将半导体芯片1和6安装在载体2上以后，通过使用热塑性或热硬性模塑料10的模塑来封装半导体芯片1和6(图2B示出)。在半导体芯片1和6之间的间隙也用模塑料10填充。模塑料层10的厚度可以在100至300μm的范围内，但也可以厚于300μm。
如图2C所示，通孔4在模塑料层10中形成。通孔4从模塑料层10的顶部表面向下到达载体2的表面。通孔4延伸穿过胶带9。可以使用激光束、机械钻孔、蚀刻方法或任何其他适当的方法来钻出通孔4。当使用激光束时，该激光束可呈圆锥形。因此，模塑料层10的顶部表面与通孔4的侧壁之间的角度可偏离90°。通孔4的纵横比(即其宽度与其长度的比率)可在从1∶1至1∶5的范围内，尤其地，是在从1∶2至1∶3的范围中。通孔4可以以从400至500μm的范围内的间距而相互隔开，但其他间距也是可能的。
在通孔4中沉积焊料(solder material)层11或任何其他适当的材料(图2D示出)。焊料11可以由如下材料组成的金属合金形成，例如：SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu及SnBi。例如，可以通过电镀(galvanic plating)将焊料层11施加到载体2上。
沉积焊料11之后，用第一导电材料5填充通孔4，该第一导电材料5可以是金属(诸如铜、铝、或金)或金属合金(诸如SnAg或SnAu)。第一材料5可以直接与模塑料10接触。用第一材料5填充通孔4可以通过使用电偶法(galvanic method)或任何其他适当的沉积方法来实施。当电沉积第一材料5时，可以将载体2和半导体芯片1和6以及模塑料层10浸入包含第一材料5的电解质溶液中，或者可选择地，可以将该电解溶液浇注在模塑料层10的顶部表面上。此外，在导电载体2与放置在电解质溶液中至少一个另外的电极之间施加适当的电压。设置载体2与另一电极之间的电压，以使第一材料5沉淀在通孔4的底部。在这种情况下，导电载体2用作用于第一材料5的电沉积的电极。在本实施例中，一旦通孔4被第一材料5完全填满则电沉积的过程停止(图2E示出)。沉积第一材料5之后，导电第一材料5在模塑料层10中形成了通路(via)。
将被模塑料10覆盖的半导体芯片1和6从载体2上移除，且将胶带9从半导体芯片1和6以及从模塑料层10上剥离(pealed)(图2F所示)。胶带9具有热释放特性，这允许在热处理过程中移除胶带9。将胶带9从载体2上移除在适当的温度下执行，该温度取决于胶带9的热释放特性且通常高于150℃，具体地，大约200℃。此外，从载体2移除胶带9时，焊料层11限定破坏点(breakingpoints)，在破坏点处穿过模塑料层10的通道从载体2分开。为了方便焊料11从载体2上移除，可以将载体2加热到焊料11的熔化温度。
在载体2和胶带9移除后，半导体芯片1的活性表面7和半导体芯片6的活性表面8以及模塑料层10的底表面形成了共用的平面。如图2G所示，将再分配(redistribution)层12施加到该共用平面上。随后，如图2H所示，将外部接触元件13施加至再分配层12。
为了说明再分配层12的结构和功能，再分配层12的一部分在图2H中放大了。在本实施例中，重新分配层12包括三个绝缘层14、15和16以及两个布线层形式的导电层17和18。绝缘层14沉积在由半导体芯片1的主表面7和半导体芯片6的主表面8以及模塑料层10形成的共用平面上。布线层17施加至绝缘层14，在嵌入活性主表面7的接触盘19与布线层17之间的一个点处形成电接触，且在由第一材料5形成的通道与布线层17之间的另一个点处形成另一个电接触。为了形成这些接触，绝缘层14具有多个开口。
随后将绝缘层15、布线层18以及绝缘层16施加至布线层17。为了允许嵌入活性主表面7的接触盘20与布线层18之间的电接触，绝缘层14和15具有多个开口。绝缘层16在布置了外部接触元件13的区域中开口。取代两个布线层，也能够仅使用一个布线层，或者可选择地，如果需要的话，使用两个以上布线层。
绝缘层14至16可由各种方法制成。例如，绝缘层14至16可以由气相或由溶液沉积，或可层压至半导体芯片1和6上。此外，薄膜技术方法也可以用于绝缘层14至16的施加。绝缘层14至16的每一个均可以达到10μm的厚度。为了与布线层17与18实现电接触，绝缘层14到16可以采用例如光刻的方法和/或蚀刻方法开口。布线层17和18例如可以采用镀金属随后对镀金属层结构化而制成。
外部接触元件13可以具有焊沉积物的形式。焊料可以由如下材料组成的金属合金形成，例如：SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu以及SnBi。可以通过“焊球置放(ball placement)”将焊沉积13施加至再分配层12，其中由焊料组成的预成型的球13被施加至布线层18中的露出的接触盘上。作为的“焊球置放”的可替换方式，例如，可以通过使用利用焊锡膏的模板印刷，以及随后的热处理程序来施加焊料球13，或者通过电镀以及随后的可选热处理程序来施加焊料球13。
模塑料层10允许再分配层12延伸超越半导体芯片1和6。因此外部接触元件13无需设置在半导体芯片1和6的区域内，而是能分布在更大的区域上。由于模塑料10而增加的区域(对于外部接触元件13的设置该区域是可获得的)意味着外部接触元件13不仅能够相互离开较大间距地被放置，而且与当所有外部接触元件13都放置在半导体芯片1的主表面7和半导体芯片6的主表面8的区域内时相比，可放置的外部接触元件13的最大数量具有同样地增加。
如图2I所示，通过模塑料层10的分离两个半导体芯片1和6相互分开，模塑料层10的分离例如通过锯开而实现。
图3A至3F示意性地示出了器件300的一种制造方法，图3F中示出了该器件300的横截面。图3A至3F所示方法是图2A至2I所示方法的改进。在图3A至3F所示的实施例中，通孔4未完全被第一材料5填满。例如，在通孔4的剩余部分的1∶1或更高的纵横比时，第一材料5的电沉积可以停止(图3A示出)。
载体2和胶带9的分离(图3B示出)、再分配层12的形成(图3C示出)以及外部接触元件13的放置(图3D示出)图2F至2H中示出的器件200的制造相同。
如图3E所示，用第二材料21填充通孔4的尚未被第一材料5填充的部分，第二材料21可以是焊料，具体的是焊锡膏。焊料21例如可以被印刷至模塑料层10上，或者可以在压力作用下被注射到通孔4中。焊料21可以由如下材料组成的金属合金形成，例如：SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu以及SnBi。焊料21可能比第一材料5更廉价。
如图3F所示，通过模塑料层10的分离，两个半导体芯片1和6相互分开，模塑料层10的分离例如通过锯开实现。
图4示意性地示出了器件200在器件300的顶部叠放。布置器件200的外部接触元件13以使接触元件13与器件300顶部表面的焊料21相接触。在彼此顶部的叠放器件导致更复杂的系统集成。模塑料层10上的导电通道允许在叠放在彼此顶部上的器件之间形成短的电连接。在图4中所示的叠放器件200和300仅仅旨在是示例性实施例，并且多种变化都是可能的，这对于本领域技术人员是显而易见。例如，不是器件200的其他器件可以叠放在器件300的顶部上和/或其他器件可以叠放在器件200的顶部上。
另外，尽管可能已经参照若干个实施方式中的仅一个公开了本发明的实施例的具体特征或方面，但是这种特征或方面可以与其他实施方式(对于给定的或特定的应用是需要的)的一个和多个其他特征或方面相结合。此外，就在详细描述或权利要求中所使用的术语“包括”、“具有”、“有”或它们的其他变化而言，以类似于术语“包括”的方式，这些术语旨在是包括性的。可以使用术语“接合”和“连接”以及衍生词。应该理解，可以使用这些术语来表示两个元件共同操作或彼此相互作用，无论它们是直接物理接触或电接触，或者它们彼此未直接接触。此外，应该理解，本发明的实施例可以在分立电路、局部集成电路或完整集成电路、或编程器件中实施。而且，术语“示例性”仅意味作为实例，而不是表示最好的或最佳的。此外还应该认识到，这里所述的特征和/或元件相对于彼此以具体尺寸示出，这仅是为了简化和易于理解的目的，而实际尺寸可以明显不同于这里所示的尺寸。
尽管已经在此示出和描述了特定的实施例，本领域的普通技术人员应该理解，在不背离本发明的范围的前提下，各种可选的和/或等同的实施方式可以替换所示和所述的具体实施例。本申请旨在覆盖在此描述的具体实施例的修改和变化。因此，本发明的范围只由权利要求及其等同物来限定。

Claims (29)

1.一种制造半导体器件的方法，包括：
将第一半导体放置在导电载体上；
用模塑料覆盖所述第一半导体；
在所述模塑料中形成通孔；以及
在所述通孔中沉积第一材料。
2.根据权利要求1所述的方法，包括在所述通孔中沉积所述第一材料的同时载体被用作电极。
3.根据权利要求1所述的方法，包括，其中所述第一半导体具有接触盘以及以所述接触盘面向所述载体的方式将第一半导体放置在所述载体上。
4.根据权利要求1所述的方法，包括在将所述第一材料沉积到所述通孔中之后，移除所述载体。
5.根据权利要求1所述的方法，包括，其中所述第一材料是导电的。
6.根据权利要求1所述的方法，包括将第二半导体放置在所述载体上以及用所述模塑料覆盖所述第二半导体。
7.根据权利要求6所述的方法，包括通过分开所述模塑料而将所述第一半导体和所述第二半导体分离。
8.根据权利要求1所述的方法，包括在晶片上制造所述第一半导体和/或第二半导体，以及在将所述第一半导体和/或所述第二半导体放置到所述载体上之前，将所述晶片分成至少两个半导体。
9.根据权利要求1所述的方法，包括通过激光束形成通孔。
10.根据权利要求1所述的方法，包括在所述通孔中电沉积所述第一材料。
11.根据权利要求1所述的方法，包括在沉积所述第一材料之后在所述通孔中沉积第二材料。
12.根据权利要求11所述的方法，包括，其中所述第二材料是焊料。
13.根据权利要求1所述的方法，包括在沉积所述第一材料之后在所述通孔中沉积第三材料。
14.根据权利要求13所述的方法，包括，其中所述第三材料是焊料。
15.根据权利要求4所述的方法，包括去除所述载体之后，将导电层施加至所述第一半导体和/或所述第二半导体。
16.根据权利要求15所述的方法，包括还将所述导电层施加至所述模塑料。
17.根据权利要求15所述的方法，包括将焊料沉积物施加至所述导电层。
18.根据权利要求1所述的方法，包括，其中所述通孔的纵横比在1∶1至1∶5的范围内。
19.根据权利要求1所述的方法，包括限定所述第一半导体为半导体芯片。
20.一种器件，包括：
半导体芯片；
模塑料层，支撑所述半导体芯片；
导电层，被施加至所述模塑料层；以及
通孔，设置在所述模塑料层中；以及
第一导电材料，布置在所述通孔中并且与所述模塑料层接触。
21.根据权利要求20所述的器件，包括，其中所述导电层覆盖所述通孔的开口。
22.根据权利要求20所述的器件，包括，其中所述第一材料电连接至所述导电层。
23.根据权利要求20所述的器件，包括，其中在所述通孔中布置第二导电材料。
24.根据权利要求20所述的器件，包括，其中所述通孔的纵横比在1∶1至1∶5的范围内。
25.根据权利要求20所述的器件，包括，其中所述通孔基本上垂直地对齐所述半导体芯片的活性表面。
26.根据权利要求20所述的器件，包括，其中所述导电层布置在所述半导体芯片的活性表面上。
27.根据权利要求20所述的器件，包括，其中所述半导体芯片的与活性表面相对的表面以及所述半导体芯片的侧表面被所述模塑料环绕。
28.一种布置，包括：
半导体，所述半导体包括第一半导体芯片、支撑所述半导体芯片的模塑料层、施加至所述模塑料层的导电层、设置在所述模塑料层中的通孔、以及布置在所述通孔中并且与所述模塑料层接触的第一导电材料；以及
第二半导体芯片，其中所述器件与所述第二半导体芯片叠放在彼此之上。
29.根据权利要求28所述的布置，包括，其中所述第一半导体芯片通过布置在所述器件的所述通孔中的第一导电材料电连接至所述第二半导体芯片。
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