CN101393873B - 包括堆叠半导体芯片的器件及其制造方法 - Google Patents

包括堆叠半导体芯片的器件及其制造方法 Download PDF

Info

Publication number
CN101393873B
CN101393873B CN2008102115470A CN200810211547A CN101393873B CN 101393873 B CN101393873 B CN 101393873B CN 2008102115470 A CN2008102115470 A CN 2008102115470A CN 200810211547 A CN200810211547 A CN 200810211547A CN 101393873 B CN101393873 B CN 101393873B
Authority
CN
China
Prior art keywords
semiconductor chip
moulding material
array
chips according
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008102115470A
Other languages
English (en)
Other versions
CN101393873A (zh
Inventor
克劳斯·普雷塞尔
戈特弗里德·比尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN101393873A publication Critical patent/CN101393873A/zh
Application granted granted Critical
Publication of CN101393873B publication Critical patent/CN101393873B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82103—Forming a build-up interconnect by additive methods, e.g. direct writing using laser direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

本发明公开了一种堆叠半导体芯片。一个实施例提供了第一半导体芯片的阵列，利用模制材料覆盖第一半导体芯片的阵列，以及在第一半导体芯片的阵列上设置第二半导体芯片的阵列。减小第二半导体芯片的厚度。通过分离模制材料使第一半导体芯片的阵列独立。

Description

包括堆叠半导体芯片的器件及其制造方法
技术领域
本发明涉及包括堆叠半导体芯片的器件，以及用于制造包括堆叠半导体芯片的器件的方法。 
背景技术
为了实现高的系统集成，将集成电路、传感器、微机械设备和其他模块堆叠到彼此之上是有用的。堆叠到彼此之上的模块越多，则堆叠厚度增加的越多。在一些应用中，将限制堆叠的最大厚度。 
为了这些和其他原因，需要本发明。 
发明内容
为了解决堆叠的最大厚度受到限制的问题，本发明提出这样一种方法，其包括：提供第一半导体芯片的阵列；利用模制材料覆盖所述第一半导体芯片的所述阵列；在所述第一半导体芯片的所述阵列上方设置第二半导体芯片的阵列；减小所述第二半导体芯片的厚度；以及通过分离所述模制材料使所述第一半导体芯片的所述阵列独立。 
另外，本发明还提供这样一种器件，其包括：第一半导体芯片；模制材料的第一层，保持所述第一半导体芯片；第二半导体芯片，被施加在所述模制材料的第一层上方；以及模制材料的第二层，保持所述第二半导体芯片，其中，背向所述第一半导体芯片的所述第二 半导体芯片的第一主表面与所述模制材料的第二层的第一表面齐平。 
附图说明
所包括的附图提供了对实施例的进一步理解，并被结合构成本说明书的一部分。附图示出了实施例，并与描述一起用于解释实施例的原则。其他实施例和实施例的多个期望优点将被认为通过参考下列详细描述变得更好理解。附图的元件不必彼此成比例。相同的参考标号表示对应的相似元件。 
图1A至图1F示例性示出了作为示例性实施例的制造器件100的方法。 
图2A至图2N示例性示出了作为另一示例性实施例的制造器件200的方法。 
图3A至图3N示例性示出了作为另一示例性实施例的制造器件300的方法。 
具体实施方式
在以下的详细描述中，参考构成本文一部分的附图，其中，通过可以实现本发明的示例性具体实施例示出了附图。对此，参考所描述图的方向使用方向术语(例如，“顶部”、“底部”、“正面”、“背面”、“前端”、“尾部”等)。由于本发明实施例中的元件可以定位于许多不同的方向，因此，方向术语是用来说明而不是用来限制的。可以理解，可利用其它实施例，并且在不背离本发明范围的情况下，可对结构或逻辑进行改变。因此，以下详细的描述不是用来限制本发明的，本发明的范围由所附权利要求限定。
应当理解，文中描述的各种示例性实施例的特征可以彼此结合，除非另外特别注明。 
下面将描述具有嵌入到模制材料中的半导体芯片的器件。半导体芯片可以是完全不同的类型，可以由不同技术制造，并且可以包括例如集成电路或光电路、或者无源元件。例如，集成电路可被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、电源集成电路、存储电路、或集成无源元件。此外，半导体芯片可被配置为MEMS(微机电系统)，并且可以包括诸如桥、膜或榫结构的微机械结构。半导体芯片可以被配置为传感器或执行机构，例如，压力传感器、加速度传感器、旋转传感器、麦克风等。半导体芯片可以被配置为天线和/或间隔的无源元件和/或芯片堆叠。半导体芯片还可以包括天线和/或间隔的无源元件。嵌入这种功能元件的半导体芯片通常包括用于驱动功能元件或者进一步处理由该功能元件生成的信号的电路。半导体芯片不需要由特殊半导体材料制造，此外其可以包括不是半导体的无机和/或有机材料，例如，分立的无源元件、天线、绝缘体、塑胶或金属。此外，半导体芯片可以被封装或不被封装。 
半导体芯片具有能与半导体芯片进行电接触的接触垫。接触垫可由任何期望的导电材料构成，例如，诸如铝、镍、钯、金、或铜的金属，金属合金，或者导电有机材料。接触垫可以位于半导体芯片的有源主表面或者半导体芯片的其他表面上。 
一个或多个导电层将被涂覆至半导体芯片。导电层可用作布线层，以与器件外部的半导体芯片进行电接触，或者与包括在器件内的其他半导体芯片和/或组件电接触。可以将导电层制造成具有任何期望的几何形状和任何期望的材料成分。例如，导电层可以由导线(conductor track)构成，但也可以呈覆盖区域的层的形式。任何期望的导电材料(例如，诸如铝、镍、钯、银、锡、金或铜的金属， 金属合金，或者有机导体)可以被用作该材料。导电层不必是同质的或者不必仅由一种材料制造，也就是说导电层中包含的材料的各种成分和浓度都是允许的。此外，导电层可以被布置在介电层之上或之下，或者两个介电层之间。 
以下描述的器件包括覆盖半导体芯片的至少一部分的模制材料。模制材料可以是适当的硬质塑料、热塑塑料、层压材料(预浸料坯)或热固塑料，并且可以包括绝缘填充材料和/或在特定情况下可以包括导电填料。各种技术可用于利用模制材料覆盖半导体芯片，例如，压缩成型、层压和注射成型。 
图1A至图1F示例性地示出了用于制造器件100的方法。首先，提供第一半导体芯片的阵列。在图1A中示出了第一半导体芯片的阵列的第一半导体芯片1和2。该阵列可以包括其他第一半导体芯片。利用模制材料3来覆盖半导体芯片1和2(参见图1B)。然后，在半导体芯片1和2上设置第二半导体芯片的阵列。图1C示出了第二半导体芯片的阵列的两个第二半导体芯片4和5。该第二半导体芯片布置可以包括其他第二半导体芯片。也可以利用模制材料6来覆盖半导体芯片4和5(参见图1D)。然后，例如通过打磨来部分地去除模制材料6，直至半导体芯片4和5的厚度被减小(参见图1E)。然后，通过分离模制材料3和6来使半导体芯片1和2独立(参见图1F)。 
图1F示出了通过上述方法获得的器件100的横截面。器件100包括保持半导体芯片1的模制材料的第一层7，以及保持半导体芯片4的模制材料的第二层8。模制材料的第二层8的上表面与半导体芯片4的上表面齐平。因此，这些表面形成了公共平面。这些平面将与数学平面不同，以及可以具有一直到10μm范围内的一些微处理，并且可以弯曲。例如，半导体芯片4的厚度(在图1F中由d1表示)将小于200μm，具体地为小于150μm。
图2A至图2N示例性地示出了制造器件200的方法，图2N示出了该器件200的横截面。图2A至图2N示出的方法是图1A至图1F示出方法的改进。因此，下面描述的制造方法的细节可以应用于图1A至图1F的方法。 
如图2A所示，半导体芯片1和2以及可能的其他半导体芯片被设置在载体10之上。载体10可以是由刚性材料(例如，诸如镍、钢或不锈钢的金属)，层压材料、膜、或材料堆叠构成的板。载体10具有平坦表面，半导体芯片1和2设置于其上。载体10的形状未限制到任何几何形状，例如，载体10可以是圆形或方形。此外，载体10可以具有任何尺寸，并且第一半导体芯片的任何适当阵列都可以设置在载体10之上(图2A中仅示出了两个第一半导体芯片)。 
文中描述的半导体芯片1和2以及所有其他半导体芯片都可以由半导体材料制成的晶片来制造。在将晶片切割成方块，然后将各个半导体芯片1和2分割开之后，半导体芯片1和2以它们被进行晶片粘接的较大间隔重新设置到载体10上。半导体芯片1和2将由相同晶片来制造，但它们也可以由不同晶片制造。此外，半导体芯片1和2物理上可以是相同的，但它们也可以包含不同的集成电路和/或表示不同组件。半导体芯片1和2分别具有有源主表面11和12，并且可以利用其有源主表面11和12面向载体10布置到载体10之上。 
在将半导体芯片1和2设置到载体10上之前，诸如双面胶带的粘胶带13将被层压在载体10上。半导体芯片1和2可以被固定在粘胶带13上。为了将半导体芯片1和2附着到载体10，可以使用其他类型的附着材料。
在将半导体芯片1和2安装到载体10上之后，例如通过使用硬质塑料或热固材料3制模从而形成模制材料的第一层7来封装它们(参见图2B)。还利用模制材料3来填充半导体芯片1和2之间的间隙。模制材料3可以基于环氧材料，并且其可以包括由小颗粒的玻璃(SiO2)或诸如Al2O3的其他电绝缘矿物填充材料组成的填充材料，或者有机填充材料。在特定情况下，填充材料可由下面进一步描述的导电颗粒组成。模制材料的第一层7的厚度d2可以在300μm到1500μm的范围内，并且在一个实施例中，在400到600μm的范围内。厚度d2还可以取决于半导体芯片1和2的厚度。覆盖半导体芯片1和2的上表面的模制材料3具有大于100μm的厚度d3。 
如图2C所示，在模制材料的第一层7中形成通孔14。通孔14可以从模制材料的第一层7的上表面向下延伸至载体10的表面。因此，通孔14可以穿过粘胶带13延伸。可以使用激光束、蚀刻法、或者任何其他适当的方法来钻出通孔14。下面将进一步给出通孔14的其他实施例。通孔14的纵横比(为其宽度和其长度的比例)可以在从1:1到1:10的范围内，并且在一个实施例中为在从1:2到1:3的范围内。通孔14的宽度可以在从50到200μm的范围内。通孔14将在100到600μm的范围内彼此分离，但也可以具有其他间隔。 
使由模制材料的第一层7覆盖的半导体芯片1和2从载体10上脱离，并且粘胶带13从半导体芯片1和2以及模制材料的第一层7上剥离(参见图2D)。粘胶带13具有热释放特性，该特性在热处理期间去除粘胶带13。在适当的温度处执行从载体10上去除粘胶带13，该适当的温度取决于粘胶带13的热释放特性，并且通常高于150℃。
在从载体10和粘胶带13上释放模制材料的第一层7之前或之后，可以利用导电材料(可以为诸如铜、铝、或金的金属，诸如SnAg、SnAu或焊接材料的金属合金，或者任何导电膏)来填充通孔14。导电材料在模制材料的第一层7中形成了直通连接15(参见图2E)。用于制造直通连接15的方法提供了没有用导电材料完全填充的通孔14，而是仅通过导电材料涂覆通孔14的侧壁。例如，首先将诸如钯层或者金属络合物的种子层沉积到在通孔14的表面上。然后，将铜层无电镀地沉积到种子层上。该铜层可以具有小于1μm的厚度。然后，电镀沉积另一铜层，其具有大于5μm的厚度。也可以省略无电镀铜沉积。在另一实施例中，导电材料可以阴极真空喷镀到通孔14的表面上。例如，阴极真空喷镀具有例如大约50μm厚度的钛层，然后，阴极真空喷镀具有例如大约200nm厚度的铜层。然后，将铜层用作种子层，以电镀沉积具有例如大约5μm厚度的其他铜层。 
将提供在由导电层涂覆的通孔14中填充诸如环氧树脂的电绝缘材料。电绝缘材料可以防止导电层被腐蚀。 
在释放载体10和粘胶带13之后，半导体芯片1和2的有源主表面11和12以及模制材料的第一层7的底面形成公共平坦表面。如图2E所示，将再分配层16涂覆至该表面。 
为了示出再分配层16的结构和功能，在图2E中放大了再分配层16的一部分。在该实施例中，再分配层16包括三个介电层17、18和19以及两个呈布线层20和21形式的导电层。介电层17沉积在由半导体芯片1和2的主表面11和12以及模制材料的第一层7形成的平坦表面上。将布线层20涂覆至介电层17，以使其具有在嵌入到有源主表面11的接触垫22与布线层20的一个点处之间产生的电接触以及直通连接15与布线层20的另一点之间的另一电接触。介电层17具有开口，以产生这些接触。
介电层18、布线层21、和介电层19顺序涂覆至介电层17和布线层20。介电层17和18具有开口，以在嵌入到有源主表面11的接触垫23与布线层21之间形成电接触。介电层21在布置有接触垫24的区域内形成开口。接触垫24可以用于将半导体芯片1和2电连接到在器件200内部或外部的其他组件。代替两个布线层，还可以仅使用一个布线层，或者如果需要可以使用至少两个布线层。文中描述的其他再分配层的结构将于再分配层16的结构类似。 
以各种方式制造介电层17至19。例如，可以从气相或溶液中沉积介电层17至19，或者可以在半导体芯片1和2上层压介电层17至19。此外，薄膜技术方法可用于涂覆介电层17至19。介电层17至19中每一个均可以具有大到10μm的厚度。为了实现与布线层20和21的电接触，例如可以通过使用光刻法和/或蚀刻法为介电层17至19形成开口。例如，可以通过使用为构建金属化层而进行的金属化来形成布线层的导线，来制造布线层20和21。 
还可以电镀生成布线层20和21。为此，通常首次沉积诸如钯层的种子层，其可以非电镀地实现或者通过使用喷墨印刷技术来实现。然后，可以将种子层用作另一导电层的电镀沉积的电极。此外，同时可以生成布线层20和覆盖通孔14表面的导电层。 
可用于生成布线层20和21的另一种技术为激光直接成型。在激光直接成型(laser direct structuring)的情况下，电绝缘聚合物薄片被设置在模制材料的第一层7以及有源主表面11和12上。通过使用激光束来进行电路限定，其激活了在聚合物薄片中的特定添加剂，以允许后来的选择电镀。另一种可能性为如被用于“扇入晶圆级封装”的再分配层处理。 
模制材料的第一层7使再分配层16延伸到半导体芯片1和2之外。因此，接触垫24不必布置在半导体芯片1和2的区域内， 而可以布置在更大的区域上。由于模制材料的第一层7上接触垫24不仅可以彼此相隔较大的间距来布置而且可以布置最大数量的可以布置的接触垫，因此与将所有接触垫24布置到半导体芯片1和2的有源主表面11，12的区域内的情况相比，用于布置接触垫24的增大区域被增大了。 
直通连接15使再分配层16与模制材料的第一层7的相对侧电接触。也被称作过孔的直通连接还可以通过在载体10上设置导电结构并在半导体芯片1和2通过模制材料3覆盖的同时用模制材料3覆盖这些结构来制造。如果这些结构具有电绝缘侧壁，则可以使用具有导电填充物的模制化合物。在模制材料的第一层7中可以结合由材料制成的结构(其可通过水或者其他溶剂溶解)。之后，该结构可以被溶解，从而创建通孔14，然后可以在其中形成直通连接15。此外，在从载体10上释放模制材料的第一层7之后，在涂覆再分配层16之前或之后，可以形成通孔14和直通连接15。 
在形成再分配层16之后，可以在再分配层16上设置半导体芯片4和5，其具有面向再分配层16的有源主表面25和26(参见图2F)。半导体芯片4和5可以通过焊料堆叠27(例如，具有在30到80μm范围内的直径的微球)电连接到再分配层16的接触垫24。焊接堆叠27构建在上部半导体芯片4和5与下部半导体芯片1和2之间的电连接。例如，焊接材料可由包含下列材料的金属合金形成：SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu和SnBi。代替焊接堆叠27，可使用其他连接技术，例如，扩散焊接或通过使用导电粘合剂实现的粘合剂结合。 
然后，利用模制材料6覆盖半导体芯片4和5(参见图2G)，从而创建模制材料的第二层8。模制材料6可与用于形成模制材料的第一层7的模制材料3相同。模制材料的第二层8的厚度d4可以在从200到1000μm的范围内，并且在一个实施例中，在从400到 600μm的范围内。覆盖半导体芯片4和5的顶部的模制材料6可以具有大于100μm的厚度d5。 
然后，使模制材料的第二层8变薄(参见图2H)。可以使用与打磨半导体晶片所使用的机械相同的打磨机械。在一个实施例中，蚀刻被用于减小模制材料的第二层8的厚度。在这种情况下，应当使用蚀刻材料，以相同的蚀刻速度来蚀刻模制材料6以及半导体芯片4和5。 
执行变薄，直至半导体芯片4和5的厚度也减小了。在打磨之后，执行损伤蚀刻工艺，来去除由打磨导致的过渡和裂缝区域。最后，模制材料的第二层8可具有小于200μm或者小于100μm的厚度d6。在变薄之后，具有半导体芯片4和5的模制材料第二层8的厚度通常不小于50μm，但也可以小于50μm。作为变薄的结果，远离再分配层16的模制材料第二层8的表面与半导体芯片4和5的上表面齐平。这里，术语“齐平”不是数学上的意义，其可以包括在10μm范围内的微处理。因此，如上所述，模制材料第二层8与半导体芯片4和5的上表面形成的公共平坦表面。 
如图2I所示，可以在模制材料第二层8中形成直通连接28，并且可以在模制材料第二层8的顶部上形成再分配层29。直通连接28和再分配层29可以具有相同和相似的特性，并且可以分别以与在模制材料第一层7中形成的直通连接15以及再分配层16相同或相似的方式来制造。 
随后，可以在再分配层29上堆叠包括半导体芯片、模制材料、直通连接、和再分配层的其他层。在图2J中，示出了这种附加层30。在层30的情况下，以如图2H所示的方式来使模制材料和半导体芯片变薄。应当注意，层30中的半导体芯片可以具有与半导体芯片1和2完全不同的功能，并且层30中的直通连接不必直接位 于布置在模制材料的第二层8中的直通连接之上。层30的直通连接还可以移动到远离下部层的直通连接。这也可以应用于文中描述的所有其他层的直通连接。此外，层30的再分配层可以具有与再分配层16和29完全不同的路线。 
图2K示出了堆叠在层30上的另一层31。在层31的情况下，模制材料未变薄。层31是器件200的顶层。在图2K中，层31包括再分配层32，其被用于在器件200顶部之上堆叠其他器件和/或可以为元件堆叠装配做准备。在不期望这种堆叠的情况下，也可以省略再分配层32。此外，也可以使层31的模制材料和半导体芯片变薄。 
如图2L所示，还可以通过打磨使模制材料的第一层7以及半导体芯片1和2变薄。在打磨和损伤蚀刻之后，模制材料的第一层7具有在50到200μm范围内的厚度d7，且还可以比这更小。 
此后，另一再分配层33可以被附着到通过变薄形成的模制材料第一层7以及半导体芯片1和2的公共平坦表面。在该布置中，在变薄之后且涂覆再分配层33之前，可以生成直通连接。此外，焊料堆叠34可以位于再分配层33的接触垫上。可以通过“焊球放置”将焊料堆叠34涂覆至再分配层33，其中，由焊料组成的预先成型的球34被涂覆至外部接触垫。代替“焊球放置”，例如将通过使用利用焊锡膏的丝网印刷术然后通过热处理工艺来涂覆焊料堆叠34。焊料堆叠34可用于使器件200与诸如PCB(印刷电路板)的其他组件进行电接触。 
如图2N所示，通过分开模制材料层和再分配层(例如，通过锯开或通过激光束)来使器件200彼此分开。
本领域技术人员应当了解，图2N所示的堆叠器件200仅作为示例性实施例，并且可以具有多种改变。例如，在相同的器件200中可以包括不同类型的半导体芯片或无源元件。半导体芯片和无源元件可以在功能、尺寸、制造技术等方面不同。此外，每个层可以存在完全不同地功能，一个层的直通连接不必与相邻层的直通连接呈直线。此外，器件200中层的数量在2至无限个范围内。 
在制造期间，在将半导体芯片的下一层堆叠到层顶部上之前，可以提供对具有半导体芯片的层进行的测试。如果发现层的一个或更对(很对)个组件失效，则将磨掉整个层(例如，层30)并由一个新的层来重新涂覆(replay)。此外，如果发现半导体芯片有缺陷，则可以在缺陷半导体芯片上涂覆具有相同功能的另一半导体芯片，以代替缺陷半导体芯片。 
在一个实施例中，没有在缺陷半导体芯片上放置另一半导体芯片，并且可以放弃包括缺陷半导体芯片的器件。 
图2A至图2N所示的制造方法一方面可以确保在制造期间模制材料是耐用的，足以避免模制材料的弯曲和破损。在模制材料的第一层7的情况下，可以制造具有足够厚度的该层。当稍后将模制材料的另一层堆叠到模制材料的第一层7顶部之上时，这些层确保堆叠层的耐用性，使得能够减小模制材料第一层7的厚度。另一方面，模制材料和半导体芯片的变薄导致器件200整个厚度的减小。这使得将器件200用于减小尺寸所需的应用成为可能。 
图3A至图3N示例性地示出了制造器件300的方法，图3N示出了其截面图。图3A至图3N示出的方法是图2A至图2N示出方法的改进。图3A至图3E所示的制造过程与图2A至图2E所示的制造过程原则上相同或相似。因此，在图2A至图2E以及图3A至图3E中，相同的参考标号用于表示相同的元件。
在图3F所示的制造过程中，图3的制造方法与图2的制造方法不同。根据图3F，再分配层35位于模制材料的第一层7相对于布置有再分配层16的表面的表面上。 
在制造再分配层35之后，可以在再分配层35上设置半导体芯片4和5，其具有面向再分配层35的有源主表面25和26(参见图3G)。 
制造模制材料的第二层8(参见图3H)，使模制材料的第二层8和半导体芯片4和5变薄(参见图3I)，形成直通连接28和再分配层29(参见图3J)，堆叠层30和31(参见图3K和图3L)，设置焊料堆叠(参见图3M)以及分割模制材料和再分配层(参见图3N)对应于图2G至图2K、图2M和图2N所示的器件200的制造。 
在器件300的情况下，可以不使模制材料的第一层7变薄。然而如果使模制材料的第一层7变薄，则在将再分配层35附着到模制材料的第一层7之前来实现(参见图3F)。当将再分配层35附着到模制材料的第一层7时，模制材料的第一层7可具有在300到1000μm范围内的厚度。 
另外，尽管仅相对于多种实施方式中的一种公开了本发明的实施例的特定特征或方面，但是如任何给定或特定应用所要求的，这些特征或方面可以与其他实施方式的一个或多个其他特征或方面进行结合。另外，就具体实施方式或权利要求中所使用的术语“包括(include)”、“具有(have)”、“带有(with)”、及它们的其他变体，这些术语旨在以类似于术语“包含(comprise)”的方式被包含。可能使用了术语“耦合(couple)”、“连接(connected)”、及它们的衍生词。应该理解，这些术语可以被用于表示两个元件彼此合作或互相作用，而不论它们是直接的物理或电接触，还是彼此非直接接触。另外，应该理解，本发明的实施例可以由分离电路、部分集成 电路、完全集成电路、或编程器件实现。而且，术语“示例性的”仅意味着作为实例，而不是最优或最佳的。还应该明了的是，为了简单和容易理解，此处描述的特征和/或元件都是以相对于彼此的特定尺寸示出的，并且它们的实际尺寸可能很大程度地不同于此处所示出的。 
尽管在此示出并描述了具体实施例，但是本领域普通技术人员应该理解的是，在不背离本发明的范围的条件下，各种可选和/或等同的实现方式可以代替所描述和示出的具体实施例。本申请旨在覆盖本文中所讨论的具体实施例的任何修改或变形。所以，本发明旨在仅由权利要求及其等同物限定。

Claims (24)

1.一种包括堆叠半导体芯片的器件的制造方法，包括：
提供第一半导体芯片的阵列；
利用模制材料覆盖所述第一半导体芯片的阵列；
在所述第一半导体芯片的阵列上方设置第二半导体芯片的阵列；
利用模制材料覆盖所述第二半导体芯片的阵列；
部分地去除覆盖所述第二半导体芯片的阵列的模制材料，直至减小所述第二半导体芯片的厚度；以及
通过分离所述模制材料使所述第一半导体芯片的阵列独立。
2.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，在所述减小所述第二半导体芯片的厚度之后，包括：在所述第二半导体芯片的阵列上方设置第三半导体芯片的阵列以及覆盖所述第三半导体芯片的阵列的模制材料。
3.根据权利要求2所述的包括堆叠半导体芯片的器件的制造方法，包括：减小所述第三半导体芯片的厚度。
4.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，包括：在利用模制材料覆盖所述第一半导体芯片的阵列之前，在载体上方设置所述第一半导体芯片的阵列。
5.根据权利要求4所述的包括堆叠半导体芯片的器件的制造方法，包括：在利用模制材料覆盖所述第一半导体芯片的阵列之后，在设置第二半导体芯片的阵列之前，去除所述载体。
6.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，在利用模制材料覆盖所述第一半导体芯片的阵列的步骤之后，在设置第二半导体芯片的阵列之前，包括：在覆盖所述第一半导体芯片的阵列的模制材料中形成直通连接。
7.根据权利要求6所述的包括堆叠半导体芯片的器件的制造方法，包括其中，所述模制材料的一个表面和所述第一半导体芯片的一个表面形成第一平坦表面，以及第一导电层被施加至所述第一平坦表面。
8.根据权利要求7所述的包括堆叠半导体芯片的器件的制造方法，包括：将第二导电层施加至所述模制材料的、与所述模制材料的所述一个表面相对的相对表面。
9.根据权利要求8所述的包括堆叠半导体芯片的器件的制造方法，包括其中：所述直通连接将所述第一导电层与所述第二导电层电连接。
10.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，包括其中，当所述第二半导体芯片的阵列设置在所述第一半导体芯片的阵列上方时，所述第二半导体芯片的有源主表面面向所述第一半导体芯片的有源主表面。
11.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，在利用模制材料覆盖所述第一半导体芯片的阵列的步骤之后，在通过分离所述模制材料使所述第一半导体芯片的阵列独立之前，包括：减小所述第一半导体芯片的厚度。
12.根据权利要求1所述的包括堆叠半导体芯片的器件的制造方法，包括：在将半导体芯片的其它阵列设置到测试过的半导体芯片上方之前，测试阵列的半导体芯片。
13.根据权利要求12所述的包括堆叠半导体芯片的器件的制造方法，包括其中，如果所述测试过的半导体芯片之一有缺陷，则设置在所述测试的半导体芯片上方的所述半导体芯片之一与缺陷的半导体芯片相同。
14.根据权利要求12所述的包括堆叠半导体芯片的器件的制造方法，包括其中，如果所述测试过的半导体芯片之一有缺陷，则不在有缺陷的半导体芯片上方设置其它半导体芯片。
15.一种包括堆叠半导体芯片的器件，包括：
第一半导体芯片；
模制材料的第一层，保持所述第一半导体芯片；
第二半导体芯片，被施加在所述模制材料的第一层上方；
以及
模制材料的第二层，保持所述第二半导体芯片，其中，背向所述第一半导体芯片的所述第二半导体芯片的主表面与所述模制材料的第二层的表面齐平。
16.根据权利要求15所述的包括堆叠半导体芯片的器件，包括其中，所述第一半导体芯片的主表面与所述模制材料的第一层的表面齐平。
17.根据权利要求16所述的包括堆叠半导体芯片的器件，包括其中，第一导电层被施加至所述第一半导体芯片的主表面以及所述模制材料的第一层的表面。
18.根据权利要求17所述的包括堆叠半导体芯片的器件，包括其中，所述第一导电层被布置在所述模制材料的第一层与所述模制材料的第二层之间。
19.根据权利要求17所述的包括堆叠半导体芯片的器件，包括其中，第二导电层被施加至所述模制材料的第一层的另一个表面。
20.根据权利要求19所述的包括堆叠半导体芯片的器件，包括其中，直通连接被布置在所述模制材料的第一层中，用于将所述第一导电层连接到第二导电层。
21.根据权利要求15所述的包括堆叠半导体芯片的器件，其中，所述第一半导体芯片和/或所述第二半导体芯片具有小于200μm的厚度。
22.根据权利要求15所述的包括堆叠半导体芯片的器件，其中，还包括施加在所述第二半导体芯片上方的第三半导体芯片，所述第三半导体芯片的设置方式与所述第二半导体芯片的设置方式相同。
23.一种包括堆叠半导体芯片的器件的制造方法，包括：
提供第一半导体芯片的阵列；
利用模制材料覆盖所述第一半导体芯片的阵列；
在所述第一半导体芯片的阵列上设置第二半导体芯片的阵列；
利用模制材料覆盖所述第二半导体芯片的阵列；
部分地去除所述模制材料，直至所述第二半导体芯片的厚度被减小；以及
通过分离所述模制材料使所述第一半导体芯片独立。
24.根据权利要求23所述的包括堆叠半导体芯片的器件的制造方法，其中，在利用所述模制材料覆盖所述第一半导体芯片和所述第二半导体芯片之前，将所述第一半导体芯片和所述第二半导体芯片设置在载体上方，并且在利用所述模制材料覆盖所述第一半导体芯片和所述第二半导体芯片之后，在部分地去除所述模制材料之前，去除所述载体。
CN2008102115470A 2007-09-21 2008-09-19 包括堆叠半导体芯片的器件及其制造方法 Expired - Fee Related CN101393873B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/859,346 2007-09-21
US11/859,346 US7858440B2 (en) 2007-09-21 2007-09-21 Stacked semiconductor chips

Publications (2)

Publication Number Publication Date
CN101393873A CN101393873A (zh) 2009-03-25
CN101393873B true CN101393873B (zh) 2011-06-29

Family

ID=40435631

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008102115470A Expired - Fee Related CN101393873B (zh) 2007-09-21 2008-09-19 包括堆叠半导体芯片的器件及其制造方法

Country Status (3)

Country Link
US (1) US7858440B2 (zh)
CN (1) CN101393873B (zh)
DE (1) DE102008039388B4 (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7820485B2 (en) * 2008-09-29 2010-10-26 Freescale Semiconductor, Inc. Method of forming a package with exposed component surfaces
US8186221B2 (en) * 2009-03-24 2012-05-29 Freescale Semiconductor, Inc. Vertically integrated MEMS acceleration transducer
US8220330B2 (en) * 2009-03-24 2012-07-17 Freescale Semiconductor, Inc. Vertically integrated MEMS sensor device with multi-stimulus sensing
US8021919B2 (en) * 2009-03-31 2011-09-20 Infineon Technologies Ag Method of manufacturing a semiconductor device
DE102009029202B4 (de) * 2009-09-04 2017-05-24 Robert Bosch Gmbh Verfahren zum Herstellen eines mikromechanischen Systems
EP2309535A1 (en) 2009-10-09 2011-04-13 Telefonaktiebolaget L M Ericsson (Publ) Chip package with a chip embedded in a wiring body
US20110115069A1 (en) * 2009-11-13 2011-05-19 Serene Seoh Hian Teh Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same
US8723299B2 (en) 2010-06-01 2014-05-13 Infineon Technologies Ag Method and system for forming a thin semiconductor device
KR101679657B1 (ko) * 2010-09-29 2016-11-25 삼성전자주식회사 유리섬유를 이용한 웨이퍼 레벨 몰드 형성방법 및 그 방법에 의한 웨이퍼 구조
KR20120091694A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 반도체 패키지
US8461691B2 (en) 2011-04-29 2013-06-11 Infineon Technologies Ag Chip-packaging module for a chip and a method for forming a chip-packaging module
US8389333B2 (en) * 2011-05-26 2013-03-05 Stats Chippac, Ltd. Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
KR101332916B1 (ko) 2011-12-29 2013-11-26 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20130260510A1 (en) * 2012-04-02 2013-10-03 Infineon Technologies Ag 3-D Integrated Circuits and Methods of Forming Thereof
US9040346B2 (en) * 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US9040355B2 (en) 2012-07-11 2015-05-26 Freescale Semiconductor, Inc. Sensor package and method of forming same
US8878360B2 (en) 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US8709868B2 (en) 2012-08-23 2014-04-29 Freescale Semiconductor, Inc. Sensor packages and method of packaging dies of differing sizes
US8659167B1 (en) 2012-08-29 2014-02-25 Freescale Semiconductor, Inc. Sensor packaging method and sensor packages
US20140210106A1 (en) * 2013-01-29 2014-07-31 Apple Inc. ULTRA THIN PoP PACKAGE
US8890284B2 (en) 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US9490699B2 (en) 2013-03-14 2016-11-08 Intel Deutschland Gmbh Digitally controlled current mode power converter
US9327965B2 (en) 2013-03-15 2016-05-03 Versana Micro Inc Transportation device having a monolithically integrated multi-sensor device on a semiconductor substrate and method therefor
KR101488590B1 (ko) 2013-03-29 2015-01-30 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8975175B1 (en) * 2013-06-28 2015-03-10 Sunpower Corporation Solderable contact regions
TWI518854B (zh) * 2013-12-30 2016-01-21 財團法人工業技術研究院 模封組件及模封材料
DE102014111106A1 (de) * 2014-08-05 2016-02-11 Osram Opto Semiconductors Gmbh Elektronisches Bauelement, optoelektronisches Bauelement, Bauelementeanordnung und Verfahren zur Herstellung eines elektronisches Bauelements
DE102014117246B4 (de) * 2014-11-25 2018-11-15 Heraeus Deutschland GmbH & Co. KG Verfahren zum Herstellen eines Substratadapters, Substratadapter und Verfahren zum Kontaktieren eines Halbleiterelements
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US11222863B2 (en) 2016-04-01 2022-01-11 Intel Corporation Techniques for die stacking and associated configurations
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature
CN115699274A (zh) * 2021-02-18 2023-02-03 华为技术有限公司 用于AiP/AoB的射频布置
US20220375892A1 (en) * 2021-05-21 2022-11-24 Institute of semiconductors, Guangdong Academy of Sciences Chip packaging method and chip packaging structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324333B1 (ko) * 2000-01-04 2002-02-16 박종섭 적층형 패키지 및 그 제조 방법
JP4023159B2 (ja) 2001-07-31 2007-12-19 ソニー株式会社 半導体装置の製造方法及び積層半導体装置の製造方法
DE10164800B4 (de) * 2001-11-02 2005-03-31 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US7858440B2 (en) 2010-12-28
DE102008039388A1 (de) 2009-04-16
DE102008039388B4 (de) 2011-02-03
US20090079090A1 (en) 2009-03-26
CN101393873A (zh) 2009-03-25

Similar Documents

Publication Publication Date Title
CN101393873B (zh) 包括堆叠半导体芯片的器件及其制造方法
CN101308803B (zh) 半导体器件的制造方法
US8076180B2 (en) Repairable semiconductor device and method
TWI751944B (zh) 晶片封裝結構
US20090160053A1 (en) Method of manufacturing a semiconducotor device
US7867878B2 (en) Stacked semiconductor chips
CN102956468B (zh) 半导体器件以及包括研磨步骤的制造半导体器件的方法
KR101424298B1 (ko) 전자 3ｄ 모듈들의 일괄적 제조를 위한 프로세스
US7553699B2 (en) Method of fabricating microelectronic devices
US9583475B2 (en) Microelectronic package with stacked microelectronic units and method for manufacture thereof
US10790234B2 (en) Embedding known-good component in known-good cavity of known-good component carrier material with pre-formed electric connection structure
CN101339927A (zh) 半导体器件
EP2610906B1 (fr) Procédé de fabrication collective de modules électroniques 3D ne comportant que des circuits imprimés validés
US7786573B2 (en) Packaging chip having interconnection electrodes directly connected to plural wafers
CN103515256B (zh) 用于制造芯片封装的方法、芯片封装和晶圆级封装
CN114171406A (zh) 扇出式堆叠芯片的封装方法及封装结构
CN116344476A (zh) 基板结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110629