CN101339927A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101339927A
CN101339927A CNA2008101276314A CN200810127631A CN101339927A CN 101339927 A CN101339927 A CN 101339927A CN A2008101276314 A CNA2008101276314 A CN A2008101276314A CN 200810127631 A CN200810127631 A CN 200810127631A CN 101339927 A CN101339927 A CN 101339927A
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China
Prior art keywords
semiconductor chip
layer
hole
molding bed
electrically conducts
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CNA2008101276314A
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English (en)
Inventor
延斯·波赫
马库斯·布伦鲍尔
伊姆加德·埃舍尔-珀佩尔
托尔斯藤·迈耶
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN101339927A publication Critical patent/CN101339927A/zh
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Abstract

本发明描述了一种器件，其包括第一半导体芯片、嵌有第一半导体芯片的模塑料层、施加在模塑料层上的第一电性导通层、布置在模塑料层上的通孔和填充通孔的焊锡材料。

Description

半导体器件
技术领域
本发明涉及半导体器件和制造半导体器件的方法。
背景技术
对于高度的系统集成技术来说，将集成电路、传感器、微机械装置或者其它器件彼此堆叠是有用的。为了能将这些被堆叠器件电性连接起来，为至少一些被堆积器件设置从这些器件的顶面至其底面的电性导通的穿通可能是有用的。
由于这些原因以及其它原因，所以需要本发明。
附图说明
本文包含了附图以提供对本发明的进一步理解，其并入并构成了本说明书的一部分。附图示出了本发明的实施例，并和说明一起用于阐述本发明的原理。参考下面的详细说明可以很容易看出本发明的其它实施例以及本发明的许多设想的优势，因为本发明的其它实施例以及本发明的许多设想的优势将更好理解。附图的元件没有必要相对成比例的。相同的参考数字指的是同一部件。
图1是器件100-1作为典型实施例的示意图。
图2是器件100-2作为典型实施例的示意图。
图3是器件100-3作为典型实施例的示意图。
图4A是两个堆叠的器件100-3的示意图。
图4B是器件100-3的两种不同的顶视图的示意图。
图5A到5L是制成器件100-3的方法的示意图。
图6A到6K是制成器件100-3的另一种方法的示意图。
图7A到7J是制成器件100-3的另一种方法的示意图。
图8A到图8C是作为典型实施例的具有电性导通通孔接触的模塑料层的剖面照片。
具体实施方式
在下列详细描述中，参考形成本说明书的一部分的附图，其中，示出了实施本发明的具体实施例。关于图，诸如“顶”、“底”、“前”、“后”、“前导”、“尾随”等的方向性术语参考所描述的附图的方向使用。由于本发明实施例的组件可以在许多不同方向放置，所以方向性术语仅用于说明，而没有任何限制的意思。应该理解的是，在不背离本发明的范围的条件下，可以使用其他实施例，并且可以进行结构或逻辑改变。所以，下列详细描述不应被理解为限制性的意思，并且本发明的范围由所附的权利要求限定。
在下面的公开内容中，参考附图描述了本发明的实施例，其中通常始终使用相同的参考数字来代表同样的元件，并且其中不同的结构没有必要用按比例绘制。在下面的描述中为了说明，列出了许多特定的细节，以提供对本发明实施例的一个或多个方面的全面理解。然而，很明显，对于本发明所属领域的技术人员来说，可以通过较少的这些特定细节来实践本发明实施例的一个或多个方面。在其它实例中，为了便于描述本发明实施例的一个或多个方面，已知的结构和器件将以方框图的形式表示。因此，下面的描述不是限制性的，本发明的范围由所附权利要求限定。
下面描述的器件包含嵌入模塑料中的半导体芯片。这些半导体芯片可以是完全不相同的类型，并可以包含有集成电路或光电电路。半导体芯片可以被配置成MEMS(微机电系统)，并可以包含有微机械结构，比如桥结构，薄膜结构或者舌状结构。半导体芯片也可以被配置为传感器或者致动器，比如压力传感器、加速度传感器、转动传感器或者麦克风等等。嵌有这些功能性元件的半导体芯片通常包含电子电路，该电路用于驱动这些功能性元件或者进一步处理由这些功能元件产生的信号。半导体芯片不需要由特殊的半导体材料制成，而且可能还包含非半导体的无机和/或有机材料，例如绝缘体、塑料或金属。
半导体芯片可以有接触垫，允许半导体芯片具有电性接触。这些接触垫由任何期望的电性导通材料制成，例如金属、像铝、金或铜、金属合金或电性导通有机材料。这些接触垫可以位于半导体芯片的活性(active或者是主动)表面或者半导体芯片的其它表面上。
下面说明的器件包含覆盖了至少一部分半导体芯片的模塑料层。这个模塑料层可以是任何合适的热塑性或热固性的材料。可以使用比如压模法或喷射模塑法等不同的技术将模塑料层覆盖在半导体芯片上。例如，模塑料可以包围住半导体芯片的主表面和侧表面。模塑料层可以延伸到半导体芯片之外，这样模塑料层主表面的尺寸可以比半导体芯片主表面的尺寸大。
模塑料层上可以施加第一电性导通层。第一电性导通层用于将半导体芯片的接触垫电性相连到外部接触。第一电性导通层可以是再分配层或者是再分配层的一部分。第一电性导通层可以以任何期望的几何形状以及期望的材料成分而制成。例如，第一电性导通层可以由线状导线通道组成，或可以有特殊的形状，比如形成电感线圈，也可以以覆盖某一区域的层的形式。任何期望的电性导通材料，比如金属、像铝、金或铜、金属合金或者有机导体，都可以被用作制成材料。第一电性导通层不需要是均质的或仅由一种材料制成，也就是说第一电性导通层中可以包含各种成分和浓度的材料。第一电性导通层可以位于电介质层的上方或下方或之间。此外，可以设置几个第一电性导通层彼此堆叠，例如，为了获得互相交叉的导电通道。
模塑料层内可以布置通孔，通孔从模塑料层的一个主表面延伸到模塑料层的其它主表面或从器件的一个主表面到器件的其它主表面。通孔可以由机械钻孔、激光束钻孔、蚀刻法、冲压法或者其它合适的方法生成。通孔的纵横比，也就是它们的宽度和长度之比，可以在1∶1到1∶5之间并尤其是在1∶2到1∶4之间。通孔的宽度可以在50到500μm之间并尤其是在100到200μm之间。通孔的长度可以在100到1000μm之间并尤其是在500到800μm之间。
模塑料层可以包含由玻璃(SiO2)小粒子构成的填充材料，或其它电性绝缘的矿物填充材料，如Al2O3，或有机填充材料。填充材料采用的晶粒尺寸取决于将要在模塑料层中生成的通孔的宽度。对于在100μm范围内或更小的通孔宽度，可以采用10μm或者更小的晶粒尺寸。对于100μm以上的通孔宽度，可以采用约为20到30μm的平均晶粒尺寸。
通孔表面可以被第二电性导通层覆盖。对于此层，可以使用电性导通材料，例如金属，如铝、金或铜、金属合金或者有机导体等作为该层的材料。第二电性导通层也可以由不同的单层构成，例如钛基或者钯基晶籽层、铜层、以及抛光的镍金面。也可能还有其它变化。第二电性导通层具有的厚度可以在0.2到75μm之间并尤其是在1到10μm之间。沉积在通孔表面的第二电性导通层形成将模塑料层的一个主表面与模塑料层的其它主表面之间连接的垂直接触。在生成第二电性导通层之后，在通孔内填充焊锡材料或另外一种电性导通材料。焊锡材料可以由金属合金制成，该金属合金可以由下列材料构成：SnPb，SnAg，SnAgCu，SnAgCuNi，SnAu，SnCu和/或SnBi。焊锡材料可以是无铅的。可选择地，通孔可以不涂覆有第二电性导通层，而是填充有焊锡材料。根据另一个可选择方案，通孔可以涂覆有第二电性导通层，但未填充满，或者可以填充或涂覆有电绝缘材料。为了防止腐蚀，第二电性导通层上可以涂覆有抗腐蚀金属层比如NiAu表面。用合适的材料填充或涂覆通孔有助于防止第二电性导通层被腐蚀。
在与施加第一电性导通层的表面相对的模塑料层的表面上，可以施加第三电性导通层。例如，第三电性导通层可以由任何需要的几何形状和任何需要的材料成分制成。例如，第三电性导通层可以由比如线状导线通道或例如用以形成电感线圈的特定形状构成，也可以以覆盖某区域的层的形式。任何需要的电性导通材料，比如像铝、金或铜的金属、金属合金或者有机导体，都可以被用作材料。第三电性导通层可以与第二电性导通层和/或布置在通孔内的焊锡材料接触。第三电性导通材料可以便于从器件顶侧接触半导体芯片。
图1是依据一个实施例的器件100-1的示意图。第一半导体芯片101嵌入模塑料层102中。模塑料层102可以延伸到半导体芯片101的较大扩展部的两侧之外。通孔103位于模塑料层102中，并可以从模塑料层102的一个主表面104延伸到其另外一个主表面105。通孔103内填充了焊锡材料106。模塑料层102上施加有第一电性导通层107。第一电性导通层107可以由一个或多个导线通道实现。第一电性导通层107可以将第一半导体芯片101的接触垫108电性相连至布置在通孔103中的焊锡材料106。接触垫108所处的第一半导体芯片101的表面可以是第一半导体芯片101的活性(active或者说主动)主表面。电介质层109可以设置在第一半导体芯片101的活性主表面和第一电性导通层107之间。电介质层109在接触垫108的位置有开口，以允许形成接触垫108与导线通道107之间的连接。
图2是根据另一个实施例的器件100-2的示意图。器件100-2与图1所示的器件100-1在许多方面是相同的。然而，与器件100-1不同，器件100-2的通孔103中不必然需要填充焊锡材料。通孔103中可以不填充材料或可以填充另一种材料106尤其是填充一种电绝缘材料以代替焊锡材料。此外，通孔103的表面涂覆有第二电性导通层110。第一电性导通层107和第二电性导通层110可以相互连接。
图3是对图1所示的器件100-1和图2所示的器件100-2的改进后的器件100-3的示意图。器件100-3上配有位于模塑料层102的主表面104上方的第三电性导通层111。第三电性导通层111与涂覆通孔103表面的第二电性导通层110和/或沉积在通孔103中的材料106电性连接。此外，导线通道107上施加了电介质层112。在电介质层112中设置了开口以利用基础导线通道107形成外接触垫113。接触环或者其它形状可以作为外接触垫113的替代选择。在电性导通穿通的区域，电性导通层107和111上也可以由阻焊膜所覆盖。
第一电性导通层107与电介质层109和112形成了再分配层。电介质层109防止了导线通道107与第一半导体芯片101的活性主表面之间发生短路。第一电性导通层107将第一半导体芯片101的接触垫108与外接触垫113相连。外接触垫113允许从器件100-3的外部接触第一半导体芯片101。电介质层112保护了导线通道107，并且可以在焊锡沉积物例如焊球安置在外接触垫113的情况下作为焊锡阻挡层。应当注意，再分配层的数量并不局限于三层。为了便于设计导线通道107彼此交叉的地方，还可以提供更多的金属喷镀层和电介质层。同样，在第三电性导通层111和模塑料层102之间还可以布置另外的电介质层。此外，电介质层114也可以保护第三电性导通层111。电介质层114也可以有开口，以在器件100-3的顶部形成外接触垫115。外接触垫115可以通过涂覆在通孔103表面的第二电性导通层110和/或如通孔103中沉积的例如焊锡的填充材料106，与第一半导体芯片101上的接触垫108电性相连。电介质层109，112和114可以由任何一种电绝缘材料制成，比如，氮化硅或光刻胶。
可以将外接触垫113设置成不直接位于通孔103的下方，而可以偏离于通孔103。这样可以防止当沉积在外接触垫113上的焊锡熔化时沉积在通孔103中的焊锡材料106从通孔103中泄漏出来。
模塑料层102允许再分配层延伸到半导体芯片101之外。因此外接触垫113和/或115不一定非要布置在第一半导体芯片101的区域内，而是可以分布在一个较大的区域内。由于模塑料层102而产生的可用于布置外接触垫113和115的区域的增加意味着不仅仅可以将外接触垫113和115放置成彼此之间相距很远，并且与所有外接触垫113和115都放置在第一半导体芯片101的主表面区域的情况相比，可以在该区域放置的外接触垫113和115的最大个数也相应地增加。相邻的接触垫113和/或115之间的距离可以在100到600μm之间尤其是在300到500μm之间。
图4A是堆叠在另一个器件100-3顶部上的器件100-3的示意图。顶部的器件100-3的外接触垫113和底部的器件100-3的外接触垫115设置为它们可通过焊锡凸块或焊锡球116相互连接。其它基于互连的焊锡的变体，例如焊锡材料薄层或半球(半球形的焊锡材料)，也可以布置在焊盘(land pad)上。这样的互连能降低堆叠高度。同样，可以使用其它的互连方式，如导电胶，各向异性导电材料或扩散焊锡材料等。彼此堆叠的器件导致了较高的系统集成度。模塑料层102的通孔103中的垂直接触允许彼此堆叠的器件之间产生短电性连接。此外，通孔103中的垂直接触有助于传导和驱散由半导体芯片101产生的热量。很明显，对于本领域的技术人员来说，图4A所示的堆叠器件100-3仅仅是一个典型的实施例，还可能有许多变化。例如，器件100-3的顶部可以堆叠不同于器件100-3的其它类型器件。
图4B是器件100-3的两种可能的顶视图的示意图。在图4B左侧示出的器件100-3的实施例中外接触垫115布置在通孔103的上方。在图4B右侧示出的器件100-3实施例中，外接触垫115的至少一部分不布置在通孔103的上方。没有布置在通孔103上方的外接触垫115通过第三电性导通层111与各个通孔103相连。一些外接触垫115布置在第一半导体芯片101的上方。外接触垫115可以在器件100-3顶部形成满的或密度较低的焊盘(land pad)阵列。
图5A到5L是制造器件100-3的方法的示意图，该方法的剖视图在图5L中示出。如图5A所示，用于制造器件100-3的半导体芯片是在一个由半导体材料制成的晶片117上制造的。将晶片117切成小块，从而分成单个的半导体芯片之后，在载体119上以较大的间隔重新放置第一半导体芯片101和第二半导体芯片118，由于它们处于晶片键合中(如图5B所示)。为了将半导体芯片101和118附着在载体119上，可以在附着半导体芯片101和118之前，先将双面胶带贴在载体119上(未显示在图5B中)。也可以采用其它类型的附着材料。
半导体芯片101和118可以在同一晶片上制成，可供选择地，也可以在不同晶片上制成。此外，半导体芯片101和118可以形状相同，却包含不同的集成电路。在半导体芯片101和118附至载体119时，它们的活性主表面可以面对载体119。
将半导体芯片101和118装在载体119上之后，通过使用热塑性或热固性模塑料102制模，将芯片封装(如图5B所示)。半导体芯片101和118之间的空隙中也充满了模塑料102。模塑料层102的厚度范围可以在200到800μm之间。
将由模塑料层102覆盖的半导体芯片101和118从载体119上释放，去除掉半导体芯片101和118上以及模塑料102上的胶带。胶带可以具有热释放的特性，这允许在热处理过程中去除胶带。在适当的温度下执行载体119上的胶带的去除，这个温度取决于胶带的热释放特性并且一般在150摄氏度以上尤其是接近200摄氏度。去掉载体119之后，半导体芯片101和118由模塑料层102支撑在一起。
如图5D所示，在模塑料层102中形成了通孔103。通孔从模塑料层102的顶面104到达其底面105。通孔103可以通过激光束、机械钻孔、蚀刻法、冲压法或其它合适的方法钻出。使用激光束钻孔时，激光束可能是圆锥形的。因此模塑料层102的顶面104和通孔103的侧壁之间的夹角可能会偏离90度。
在产生了通孔103之后，可能会有一些清洁步骤。比如，将模塑料层102和半导体芯片101和118一起浸入包括水和/或异丙醇的超声波浴池中。
在生成第二电性导通层110之前，可以先在半导体芯片101和118的活性主表面上沉积掩蔽层120(如图5E所示)。例如，掩蔽层120可以是一层光刻胶、氮化硅或者其它抗蚀剂。
随后，如图5F所示重配置的晶片表面可以全部镀上金属层121。为此，可以使用标准的PCB(印刷电路板)通孔镀金属工艺。例如，首先在模塑料层102上沉积一层比如钯层的晶籽层。然后再非电镀(或者说化学)沉积一层铜。该铜层的厚度小于1μm。然后再电镀沉积厚度大于5μm的另一层铜。铜层的化学沉积也可以省略。
可以使用光刻或刻蚀步骤结构化金属层121以生成所需的金属结构。从而获得涂覆通孔103表面的第二电性导通层110(见图5G)。第二电性导通层110也可以堆叠在模塑料层102的主表面104和105上靠近通孔103的区域中，形成焊盘122。
可以设置为将如环氧树脂的电绝缘材料填充到涂覆有第二电性导通层110的通孔103中。可供选择的，给涂覆后的通孔103再涂覆另一层，比如镍金层，通孔103的其它部分是未填充的。电绝缘层以及另一层都可以保护第二电性导通层110不被腐蚀。
根据另一个实施例，通孔103内填充了焊锡材料106。为此，可以在焊盘122上放置助熔材料123和焊锡材料106(参见图5H)。
助熔材料123可以压印在焊盘122上。在模塑料层102的上方放一个丝网，用橡胶滚轴把助熔材料123压过丝网(stencil)。把焊锡材料106压印在助熔材料123上。可供选择地，可以使用拾取和安置工艺或堆积(shacking)工艺将焊锡材料106以焊锡球的形式放置在焊盘122上。焊锡材料106可以是无铅的金属合金，如SnPb，SnAg，SnAgCu，SnAgCuNi，SnAu，SnCu或SnBi。助熔材料123可以是有杂质的助熔剂，其在焊接过程中蒸发。
将助熔材料123和焊锡材料106加热到焊锡材料106的熔化温度，比如160摄氏度到300摄氏度之间尤其是在180摄氏度到260摄氏度之间。然后熔化的焊锡材料106流入通孔103中，并在里面凝固(见图5I)。
包括电性导通层107，115和电介质层109，112，114的再分配层可以由标准技术生成(见图5J)。例如，在模塑料层102的主表面104，105上溅射氮化硅作为电介质层109，112和114。电性导通层107和115通过喷镀金属和结构化步骤而制成，比如用消去(subtractive)工艺或可供选择的加成(additive)工艺。将电性导通层107和115布置成与焊锡材料106和/或涂覆通孔103表面的第二电性导通层110相接触。
电介质层112和114在外接触垫113和115的位置开口。焊锡球124可以放置在外接触垫113和/或115上(见图5K)。在放置焊锡球124之前或之后，通过分开模塑料层102，例如通过锯开，将半导体芯片101和118与彼此分开(见图5L)。
图6A到6K是制成另一种器件100-3的方法的示意图。图6A到图6K所示的生产方法在很多方面与图5A到图5L所示的方法是相同的(如图6A到图6C)。与图5A到5L所示的生产方法不同，在生成通孔103(见图6E)以及涂覆通孔103的表面的第一电性导通层110(见图6F和6G)之前，就把包含有电性导通层107，115和电介质层109，112，114的再分配层沉积在模塑料层102上(见图6D)。
图7A到7J是制成器件100-3方法的另一种变化的示意图。与图5A到5L所示的制造方法不同，在生成通孔103(见图7E)之前，就把电介质层109和114沉积在模塑料层102上(见图7D)。在生成通孔103之后，沉积(见图7F)并结构化(见图7G)金属层121。通过这样做，同时生成电性导通层107，110和111。三个电性导通层107，110和111可以通过晶籽层的化学沉积、连续的薄铜层的化学沉积和另一金属层的电镀沉积而生成。此外，需要注意的是，电介质层109和114也可以被省略。
生成了电性导通层107，110和111之后，可以再沉积一层电介质层112和125(见图7I)，并像上面描述的那样，将焊锡材料106填充到通孔103中(见图7H)。
图8A到8C是模塑料层的剖面照片，其中布置了通孔。所有的通孔都涂覆有铜层，一些通孔中内填充了焊锡材料。
另外，尽管仅相对于多种实施方式中的一种公开了本发明的实施例的特定特征或方面，但是如任何给定或特定应用所要求的，这些特征或方面可以与其他实施方式的一个或多个其他特征或方面进行结合。另外，就具体实施方式或权利要求中所使用的术语“包括(include)”、“具有(have)”、“带有(with)”、及它们的其他变体，这些术语旨在以类似于术语“包含(comprise)”的方式被包含。可能使用了术语“相连或耦合(couple)”、“连接(connected)”、及它们的衍生词。应该理解，这些术语可以被用于表示两个元件彼此合作或互相作用，而不论它们是直接的物理或电接触，还是彼此非直接接触。另外，应该理解，本发明的实施例可以由分离电路、部分集成电路、完全集成电路、或编程装置实现。而且，术语“示例性的”仅意味着作为实例，而不是最优或最佳的。还应该明了的是，为了简单和容易理解，此处描述的特征和/或元件都是以相对于彼此的特定尺寸示出的，并且它们的实际尺寸可能很大程度地不同于此处所示出的。
尽管在此示出并描述了具体实施例，但是本领域普通技术人员应该理解的是，在不背离本发明的范围的条件下，各种可选和/或等同的实现方式可以代替所描述和示出的具体实施例。本申请旨在覆盖本文中所讨论的具体实施例的任何修改或变形。所以，本发明旨在仅由权利要求及其等同物限定。

Claims (27)

1.一种器件，包括：
第一半导体芯片；
嵌有所述第一半导体芯片的模塑料层；
施加在所述模塑料层上的第一电性导通层；
布置在所述模塑料层中的通孔；
填充所述通孔的焊锡材料。
2.根据权利要求1所述的器件，其中，所述第一电性导通层与所述焊锡材料电性相连。
3.根据权利要求1所述的器件，其中，第二电性导通层覆盖所述通孔的表面。
4.根据权利要求3所述的器件，其中，所述第二电性导通层延伸到所述模塑料层的第一主表面。
5.根据权利要求3所述的器件，其中，所述第二电性导通层在所述模塑料层的第一主表面上形成焊盘。
6.根据权利要求1所述的器件，其中，所述第一电性导通层布置在所述第一半导体芯片的活性表面的上方。
7.根据权利要求1所述的器件，其中，所述第一半导体芯片的与所述活性表面相对的表面及所述第一半导体芯片的侧面都被模塑料层包围。
8.根据权利要求1所述的器件，还包括第二半导体芯片，其中，所述第一半导体芯片和所述第二半导体芯片彼此堆叠。
9.根据权利要求8所述的器件，其中，所述第一半导体芯片通过焊锡材料与所述第二半导体芯片电性相连。
10.一种器件，包括：
第一半导体芯片；
嵌有所述第一半导体芯片的模塑料层；
施加在所述模塑料层上的第一电性导通层；
布置在所述模塑料层中的通孔；
覆盖所述通孔表面的第二电性导通层。
11.根据权利要求10所述的器件，其中，所述第一电性导通层与所述第二电性导通层电性相连。
12.根据权利要求10所述的器件，其中，所述第二电性导通层延伸到所述模塑料层的第一主表面。
13.根据权利要求10所述的器件，其中，所述第二电性导通层在所述模塑料层的第一主表面上形成焊盘。
14.根据权利要求10所述的器件，还包括填充所述通孔的电绝缘材料。
15.根据权利要求10所述的器件，还包括第二半导体芯片，其中所述第一半导体芯片和所述第二半导体芯片彼此堆叠。
16.根据权利要求15所述的器件，其中，所述第一半导体芯片通过焊锡与所述第二半导体芯片电性相连。
17.一种方法，包括：
用模塑料覆盖第一半导体芯片；
在所述模塑料中形成通孔；
在所述通孔中沉积焊锡材料。
18.根据权利要求17所述的方法，其中，在用所述模塑料覆盖所述第一半导体芯片之前将所述第一半导体芯片放置于载体上，然后将所述载体去除。
19.根据权利要求17所述的方法，其中，向所述模塑料上施加电性导通层。
20.根据权利要求17所述的方法，其中，用所述模塑料覆盖第二半导体芯片，通过分割所述模塑料将所述第一半导体芯片和所述第二半导体芯片分开。
21.根据权利要求17所述的方法，其中，为了将所述焊锡材料沉积在所述通孔中，将所述焊锡沉淀物放置于所述通孔的上方，并熔化所述焊锡沉淀物。
22.一种方法，包括：
用模塑料覆盖半导体芯片；
在所述模塑料中形成通孔；
在所述模塑料的表面上生成第一电性导通层；
在所述通孔的表面上生成第二电性导通层。
23.根据权利要求22所述的方法，其中，在生成所述第一电性导通层之前，在所述模塑料中形成所述通孔。
24.根据权利要求22所述的方法，其中，在生成所述第一电性导通层之后，在所述模塑料中形成所述通孔。
25.根据权利要求22所述的方法，其中，在所述模塑料上沉积金属层，通过对所述金属层结构化以生成所述第一电性导通层和所述第二电性导通层。
26.根据权利要求22所述的方法，其中，在用所述模塑料覆盖所述半导体芯片之前先将所述半导体芯片置于载体上，然后将所述载体去除。
27.一种器件，包括：
第一半导体芯片；
嵌有所述第一半导体芯片的模塑料层；
施加在所述第一半导体芯片的所述模塑料层上的第一电性导通层；
第二半导体芯片；
嵌有所述第二半导体芯片的模塑料层；
施加在所述第二半导体芯片的模塑料层上的第一电性导通层；
其中第一半导体芯片和第二半导体芯片彼此堆叠；以及
把第二半导体芯片电性相连到第一半导体芯片的装置。
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US20090008793A1 (en) 2009-01-08
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US20090155956A1 (en) 2009-06-18
US8829663B2 (en) 2014-09-09

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