CN104025288A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN104025288A
CN104025288A CN201280064618.3A CN201280064618A CN104025288A CN 104025288 A CN104025288 A CN 104025288A CN 201280064618 A CN201280064618 A CN 201280064618A CN 104025288 A CN104025288 A CN 104025288A
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China
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semiconductor chip
downside
rewiring
upside
seal member
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CN201280064618.3A
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Inventor
朴润默
田炳栗
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Nepes Co Ltd
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Nepes Co Ltd
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明提供一种半导体封装，其具有通过密封结构将半导体芯片嵌入于半导体芯片，在所述嵌入的半导体芯片的下侧设置外侧连接部件的扇出结构。本发明一实施例的半导体封装包括：嵌入重新布线图案层；上侧半导体芯片，位于所述嵌入重新布线图案层的上侧；上层密封部件，密封所述上侧半导体芯片；下侧半导体芯片，位于所述嵌入重新布线图案层的下侧；以及下侧密封部件，密封成不露出所述下侧半导体芯片。

Description

半导体封装及其制造方法
技术领域
本发明的技术思想涉及一种半导体封装，更详细而言，涉及一种半导体封装及其制造方法，所述半导体封装具备扇出结构，通过密封部件嵌入半导体芯片，在所述嵌入的半导体芯片的下侧设置外侧连接部件。
背景技术
最近，半导体元件随着工序技术的微化及功能多样化而使得芯片大小减小且输入输出端子数量增加，电极衬垫间距逐渐微小化，而且随着加速多种功能的融合，将多个元件集成到一个封装内的系统级封装技术正在兴起。并且，为了最小化操作噪音以及提高信号速度，系统级封装技术变为能够维持短信号距离的三维层压技术方式。另一方面，为了这种技术改善要求以及控制产品价格上升而提高生产率并节省制造成本，引入层压多个半导体芯片来构成的半导体芯片封装。
以往的层压型半导体封装，例如系统级封装(system in package，SIP)由于在第一半导体芯片上层压的第二半导体芯片的外侧区域形成输入输出端子，因此需要所述第一半导体芯片和所述第二半导体芯片具有大小差，所述第一半导体芯片和第二半导体芯片的大小差越小输入输出端子的数量越受限制。
发明内容
(一)要解决的技术问题
本发明的技术思想欲实现的技术问题是提供一种半导体封装，其具有扇出结构，通过密封部件嵌入半导体芯片，在所述嵌入的半导体芯片的下侧设置外侧连接部件。
并且，本发明的技术思想欲实现的另一技术问题为提供所述半导体封装的制造方法。
(二)技术手段
为了实现上述技术问题，本发明的半导体封装可以包括：嵌入重新布线图案层；上侧半导体芯片，位于所述嵌入重新布线图案层的上侧；上侧密封部件，密封所述上侧半导体芯片；下侧半导体芯片，位于所述嵌入重新布线图案层的下侧；以及下侧密封部件，密封成不露出所述下侧半导体芯片。
可进一步包括：导电柱，与所述嵌入重新布线图案层电连接；以及外侧连接部件，与所述导电柱电连接。
可进一步包括外侧重新布线图案层，其位于所述下侧密封部件的下侧，将所述导电柱和所述外侧连接部件电连接。
所述外侧连接部件的一部分可位于所述下侧半导体芯片的下侧。
所述上侧密封部件和所述下侧密封部件可相互连接，密封成不露出所述嵌入重新布线图案层。
所述下侧密封部件可贯穿所述嵌入重新布线图案层的一部分而与所述上侧密封部件连接。
所述上侧半导体芯片和所述下侧半导体芯片可通过所述嵌入重新布线图案层相互电连接。
所述下侧半导体芯片可包括多个下侧半导体芯片。
可进一步包括与所述嵌入重新布线图案层电连接，并嵌入所述密封部件的多个导电柱，所述导电柱的一部分可位于所述多个下侧半导体芯片之间。
所述上侧半导体芯片可包括多个上侧半导体芯片。
所述上侧半导体芯片和所述下侧半导体芯片可具有相同大小。
根据本发明的另一侧面，可提供半导体封装的制造方法，其包括：在第一承载基板上粘贴上侧半导体芯片的步骤；形成密封所述上侧半导体芯片的上侧密封部件的步骤；在所述上侧密封部件上粘贴第二承载基板的步骤；去除所述第一承载基板，露出所述上侧半导体芯片的步骤；在所述露出的上侧半导体芯片及所述上侧密封部件上形成嵌入重新布线图案层的步骤；形成与所述嵌入重新布线图案层电连接的导电柱的步骤；在所述嵌入重新布线图案层的下侧以与所述上侧半导体芯片相反的位置粘贴下侧半导体芯片的步骤；形成密封所述下侧半导体芯片及所述导电柱的下侧密封部件的步骤；使所述下侧密封部件平坦以露出所述导电柱的步骤；在所述下侧密封部件上形成与所述导电柱电连接的外侧重新布线图案层的步骤；以及在所述外侧重新布线图案层上以电连接的方式粘贴外侧连接部件的步骤。
(二)有益效果
本发明技术思想的半导体封装，利用嵌入重新布线图案层，在上下侧安装半导体芯片，将至少一个半导体芯片嵌入密封部件内，在所述密封部件上形成外侧重新布线图案层，由此能够不受半导体芯片大小限制地使输入输出端子微小化，并且能够提供更多数量的输入输出端子。
半导体封装的背面和侧面由密封部件完全包围，因此能够提供封装在受到冲击时，对其进行保护的结构，由于贯穿嵌入重新布线图案层来填充密封部件，因此能够提高密封部件的贴合力。
附图说明
图1是表示本发明一实施例的半导体封装的剖面图。
图2至图8是表示本发明一实施例的半导体封装的剖面图。
图9至图18是根据工序步骤表示制造本发明一实施例的图1的半导体封装的制造方法的剖面图。
具体实施方式
以下，参照附图，对本发明的优选实施例进行详细说明。本发明的实施例为了向本领域技术人员更完整地说明本发明的技术思想而提供，下述实施例可变更为多种其它方式，本发明的技术思想不限于下述实施例。相反，实施例是为了更充实完善本公开，向本领域技术人员完整地传授技术思想而提供。如本说明书中所使用，术语“和/或”包括相应列举的项目中任意一个或一个以上的所有组合。同一附图标记始终表示同一构成要件。并且，附图的多种构成要件和区域是概略表示的。因此，本发明的技术思想不限于附图中所表示的相对大小或间隔。
图1是表示本发明一实施例的半导体封装1的剖面图。
参照图1，半导体封装1包括嵌入重新布线图案层30，以嵌入重新布线图案层30为基准位于相反位置的上侧半导体芯片10和下侧半导体芯片40。例如，上侧半导体芯片10可以位于嵌入重新布线图案层30的上侧，下侧半导体芯片40可以位于嵌入重新布线图案层30的下侧。半导体封装1可包括密封上侧半导体芯片10的上侧密封部件20以及密封下侧半导体芯片40的下侧密封部件60。并且，半导体封装1可进一步包括与嵌入重新布线图案层30电连接的导电柱50，与导电柱50电连接的外侧重新布线图案层70和外侧连接部件80。
上侧半导体芯片10和下侧半导体芯片40可以是同种产品或者异种产品。例如，上侧半导体芯片10和下侧半导体芯片40可以是存储器芯片或逻辑芯片。这些存储器芯片可包括例如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、闪烁存储器(flash)、相变随机存取存储器(PRAM)、电阻式随机存取存储器(ReRAM)、铁电随机存取存储器(FeRAM)或者磁随机存取存储器(MRAM)。这种逻辑芯片可以是控制存储器芯片的控制器。例如，上侧半导体芯片10可以是包括逻辑电路的逻辑芯片，下侧半导体芯片40可以是存储器芯片，或者也可以与此相反。半导体封装1可以是片上系统(SOC，system on chip)或者系统级封装。
上侧半导体芯片10和下侧半导体芯片40可以具有相同大小或者不同大小。
上侧半导体芯片10可包括上侧半导体芯片衬垫12。下侧半导体芯片40可包括下侧半导体芯片衬垫42，并且，在下侧半导体芯片40的上侧可以包括与绝缘层44和下侧半导体芯片衬垫42连接的焊盘46。
嵌入重新布线图案层30可包括第一绝缘层32、重新布线图案34及第二绝缘层36。重新布线图案34可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。重新布线图案34可重新布线上侧半导体芯片10和/或下侧半导体芯片40，并且可与外侧连接部件80电连接。因此，可以使上侧半导体芯片10和/或下侧半导体芯片40的输入输出端子微小化，并且能够增加所述输入输出端子的数量。并且，上侧半导体芯片10和/或下侧半导体芯片40与嵌入重新布线图案层30连接，由此半导体封装可具有扇出结构。上侧半导体芯片10和下侧半导体芯片40可共用重新布线图案34，这种情况下，上侧半导体芯片10和下侧半导体芯片40可通过重新布线图案34相互电连接。并且，上侧半导体芯片10和下侧半导体芯片40可分别连接于电分离的重新布线图案34，这种情况下，上侧半导体芯片10和下侧半导体芯片40可以不通过重新布线图案34相互电连接。
重新布线图案34的上侧可以被第一绝缘层32覆盖，重新布线图案34的下侧可以被第二绝缘层36覆盖。重新布线图案34的上侧一部分可从第一绝缘层32露出，露出的重新布线图案34的上侧一部分可与上侧半导体芯片10电连接。即，重新布线图案34和上侧半导体芯片10的上侧半导体芯片衬垫12可电连接。并且，重新布线图案34的下侧一部分可从第二绝缘层36露出，露出的重新布线图案34的下侧一部分可与下侧半导体芯片40电连接。重新布线图案34可由一层或多层构成。
并且，嵌入重新布线图案层30可由预先制造的基板构成，通过压制、粘结、回流等粘结到上侧半导体芯片10及上侧密封部件20的情况也包括在本发明的技术思想范围内。
连接部件48可位于焊盘46和嵌入重新布线图案层30的露出的重新布线图案34，可电连接重新布线图案层30的重新布线图案34和下侧半导体芯片40的半导体芯片衬垫42。并且，下侧半导体芯片40和上侧半导体芯片10可通过嵌入重新布线图案层30和连接部件48相互电连接。连接部件48可包括导电物，例如可包括金属。连接部件48例如可以是锡球，可通过回流工序粘贴到焊盘46及嵌入重新布线图案层30。
上侧密封部件20可密封上侧半导体芯片10。上侧密封部件20可完全覆盖上侧半导体芯片10。作为替换方案，上侧半导体芯片10的最上侧从上侧密封部件20露出的情况也包括在本发明的技术思想范围内。上侧密封部件20可包括绝缘物，例如可包括环氧模塑化合物(epoxymold compound，EMC)。
导电柱50可与嵌入重新布线图案层30电连接。导电柱50可位于嵌入重新布线图案层30露出的区域，导电柱50可与嵌入重新布线图案层30电连接。导电柱50可位于下侧半导体芯片40的外侧。并且，上侧半导体芯片10可向导电柱50的上侧区域延伸。从嵌入重新布线图案层30计算，导电柱50的高度可高于下侧半导体芯片40的高度。导电柱可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。并且，导电柱50可包括包含导电焊料(solder)或者导电物质的焊膏(solder paste)。并且，导电柱50可以为如硅通孔(through silicon via，TSV)等贯穿电极。
下侧密封部件60可密封下侧半导体芯片40及导电柱50。下侧密封部件60可密封成不露出下侧半导体芯片40。并且，下侧密封部件60可密封嵌入重新布线图案层30。下侧密封部件60可填充下侧半导体芯片40与连接部件48之间的空间。下侧密封部件60可包括绝缘物，例如可包括环氧模塑化合物。
上侧密封部件20和下侧密封部件60可相互连接，可密封成不露出嵌入重新布线图案层30。作为替换方案，从上侧密封部件20和/或下侧密封部件60露出嵌入重新布线图案层30的情况也包括在本发明的技术思想范围内。上侧密封部件20和下侧密封部件60可包含相同物质，或者可包含不同物质。上侧密封部件20和下侧密封部件60可构成一体型结构体(one-body structure)。
从外侧重新布线图案层30计算，导电柱50的高度可高于下侧半导体芯片40的高度，因此下侧半导体芯片40可通过下侧密封部件60不露出地嵌入。
外侧重新布线图案层70可位于下侧密封部件60的下侧，可与导电柱50电连接。外侧重新布线图案层70可电连接导电柱50和外侧连接部件80。并且，上侧半导体芯片10和/或下侧半导体芯片40连接于外侧重新布线图案层70，由此半导体封装1可具有扇出结构。
外侧重新布线图案层70可包括第三绝缘层72、外侧重新布线图案74、第四绝缘层76及外侧焊盘78。外侧重新布线图案74可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。外侧重新布线图案74的上侧可被第三绝缘层72覆盖。外侧重新布线图案74的下侧可被第四绝缘层76覆盖。外侧重新布线图案74的上侧一部分可从第三绝缘层72露出，露出的外侧重新布线图案74的上侧一部分可与导电柱电连接。即，外侧重新布线图案74和嵌入重新布线图案层30可电连接。并且，外侧重新布线图案74的下侧一部分可从第四绝缘层76露出，露出的外侧重新布线图案74的下侧一部分可与外侧连接部件80电连接。露出的外侧重新布线图案74上可进一步形成外侧焊盘78。并且，外侧重新布线图案层70可由预先制造的基板构成，通过压制、粘结、回流等粘结到导电柱50及下侧密封部件60的情况也包括在本发明的技术思想范围内。
外侧连接部件80设置成与外侧重新布线图案层70电连接。外侧连接部件80可粘贴到露出的外侧重新布线图案74，或者粘贴到外侧焊盘78。外侧连接部件80可包括导电物，例如可包括金属。外侧连接部件80可以为锡球。
外侧重新布线图案层70可提供重新布线，由此，外侧连接部件80的一部分可位于下侧半导体芯片40的下侧。因此，可跨越相对宽的面积设置外侧连接部件80，结果，能够实现上侧半导体芯片10和/或下侧半导体芯片40的输入输出端子的微小化，并且能够增加所述输入输出端子的数量。
图2至图8示出本发明一实施例的半导体封装2、3、4、5、6、7、8。本实施例的半导体封装2、3、4、5、6、7、8是从上述实施例的半导体封装变更一部分结构的半导体封装，因此省略重复的结构。
参照图2，半导体封装2中，上侧密封部件20和下侧密封部件60相互连接，密封成不露出嵌入重新布线图案层30a。并且，下侧密封部件60可贯穿嵌入重新布线图案层30a的一部分，进一步与上侧密封部件20连接，由此，能够进一步增加上侧密封部件20和下侧密封部件60的粘结力。
参照图3，半导体封装3可包括多个下侧半导体芯片40a。多个下侧半导体芯片40a与图1的下侧半导体芯片40类似地可与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a之间可设置导电柱50a，导电柱50a可与嵌入重新布线图案层30电连接。
参照图4，半导体封装4可包括多个下侧半导体芯片40a。多个下侧半导体芯片40a与图1的下侧半导体芯片40类似地可与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a之间可设置导电柱50a，导电柱50a可与嵌入重新布线图案层30电连接。并且，半导体封装4中，上侧密封部件20和下侧密封部件60相互连接，可以密封成不漏出嵌入重新布线图案层30a。并且，下侧密封部件60可贯穿嵌入重新布线图案层30a的一部分，进一步与上侧密封部件20连接，由此，能够进一步增加上侧密封部件20和下侧密封部件60的粘结力。
参照图5，半导体封装5可包括多个上侧半导体芯片10a。多个上侧半导体芯片10a可与图1的上侧半导体芯片10类似地与嵌入重新布线图案层30电连接。
参照图6，半导体封装6可包括多个上侧半导体芯片10a。多个上侧半导体芯片10a可与图1的上侧半导体芯片10类似地与嵌入重新布线图案层30电连接。并且，半导体封装6中，上侧密封部件20和下侧密封部件60相互连接，可以密封成不露出嵌入重新布线图案层30a。并且，下侧密封部件60可贯穿嵌入重新布线图案层30a的一部分，进一步与上侧密封部件20连接，由此，能够进一步增加上侧密封部件20和下侧密封部件60的粘结力。
参照图7，半导体封装7可包括多个上侧半导体芯片10a和多个下侧半导体芯片40a。多个上侧半导体芯片10a可与图1的上侧半导体芯片10类似地与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a可与图1的下侧半导体芯片40类似地与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a之间可设置导电柱50a，导电柱50a可与嵌入重新布线图案层30电连接。
参照图8，半导体封装8可包括多个上侧半导体芯片10a和多个下侧半导体芯片40a。多个上侧半导体芯片10a可与图1的上侧半导体芯片10类似地与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a可与图1的下侧半导体芯片40类似地与嵌入重新布线图案层30电连接。多个下侧半导体芯片40a之间可设置导电柱50a，导电柱50a可与嵌入重新布线图案层30电连接。并且，半导体封装8中，上侧密封部件20和下侧密封部件60相互连接，可以密封成不露出嵌入重新布线图案层30a。并且，下侧密封部件60可贯穿嵌入重新布线图案层30a的一部分，进一步与上侧密封部件20连接，由此，能够进一步增加上侧密封部件20和下侧密封部件60的粘结力。
图9至图18是表示根据工序步骤制造本发明一实施例的图1的半导体封装1的制造方法的剖面图。
参照图9，利用粘结部件16将上侧半导体芯片10粘贴到第一承载基板14上。粘结部件16可以是液体粘结剂或者粘结胶带。上侧半导体芯片10的上侧半导体芯片衬垫12可朝向下侧，可与粘结部件16接触。第一承载基板14可包括硅(silicon)、玻璃(glass)、陶瓷(ceramic)、塑料(plastic)或者聚合物(polymer)。
参照图10，形成密封上侧半导体芯片10的上侧密封部件20。上侧密封部件20可完全覆盖上侧半导体芯片10。上侧密封部件20可包括绝缘物，例如可包括环氧模塑化合物。
参照图11，利用粘结部件17在上侧密封部件20上粘贴第二承载基板18。粘结部件17可以是液体粘结剂或者粘结胶带。第二承载基板18可包括硅、玻璃、陶瓷、塑料或者聚合物。接着，去除第一承载基板14而露出所述上侧半导体芯片10。由此，上侧半导体芯片衬垫12露出。
参照图12，在露出的上侧半导体芯片10及上侧密封部件20上形成嵌入重新布线图案层30。嵌入重新布线图案层30可由第一绝缘层32、重新布线图案34及第二绝缘层36构成。例如，在上侧半导体芯片10上形成第一绝缘层32，去除第一绝缘层32的一部分，露出上侧半导体芯片衬垫12。接着，形成与露出的上侧半导体芯片衬垫12电连接且向第一绝缘层32的上侧延伸的重新布线图案34。重新布线图案34可利用蒸镀、镀金等多种方法形成。在重新布线图案34上形成第二绝缘层36，去除第二绝缘层36的一部分，以便露出重新布线图案34的一部分。在露出的重新布线图案34上通过后续的工序可粘贴导电柱50(参照图13)或者连接部件48(参照图14)。
此外，嵌入重新布线图案层30可由预先制造的基板构成，通过压制、粘结、回流等粘结到上侧半导体芯片10及上侧密封部件20的情况也包括在本发明的技术思想范围内。
参照图13，形成与嵌入重新布线图案层30电连接的导电柱50。导电柱50可位于嵌入重新布线30的露出区域，导电柱50可与嵌入重新布线图案层30电连接。导电柱50可包括导电物，例如可包括金属，可包括铜、铜合金、铝或者铝合金。并且，导电性柱50可包括包含导电焊料或者导电物质的焊膏。虽然未图示，嵌入重新布置图案层30上形成掩模层，在所述掩模层上形成露出嵌入重新布置图案层30的一部分的开口部之后，用导电物填充所述开口部，通过去除所述掩膜层，形成导电柱50。所述掩膜层可包括例如光致抗蚀剂。
参照图14，在嵌入重新布线图案层30的下侧以与上侧半导体芯片10相反位置粘贴下侧半导体芯片。下侧半导体芯片40可包括露出下侧半导体芯片衬垫42的绝缘层44。下侧半导体芯片衬垫42上可包括焊盘46。连接部件48位于焊盘46和嵌入重新布线图案层30的露出的重新布线图案34。连接部件48可电连接下侧半导体芯片40和嵌入重新布线图案层30。并且，下侧半导体芯片40和上侧半导体芯片10可通过嵌入重新布线图案层30和连接部件48相互电连接。连接部件48可包括导电物，例如可包括金属。连接部件48例如可以是锡球，可通过回流工序粘贴到焊盘46及嵌入重新布线图案层30。从嵌入重新布线图案层30计算，导电柱50的高度可高于下侧半导体芯片40的高度。
作为替换方案，可调换图13所示的工序和图14所示的工序来实施。
参照图15，形成密封下侧半导体芯片40和导电性柱50的下侧密封部件60。下侧密封部件60密封下侧半导体芯片40使其不露出。并且，下侧密封部件60可密封嵌入重新布线图案层30。下侧密封部件60可填充下侧半导体芯片40的连接部件48之间的空间。下侧密封部件60可包括绝缘物，例如可包括环氧模塑化合物。
上侧密封部件20和下侧密封部件60可相互连接，可密封成嵌入重新布线图案层30不露出。作为替换方案，从上侧半导体芯片20和/或者下侧密封部件60露出嵌入重新布线图案层30的情况也包括在本发明的技术思想范围内。上侧密封部件20和下侧密封部件60可包含相同物质，或者可包含不同物质。上侧密封部件20和下侧密封部件60可构成一体型结构体。
作为替换方案，导电柱50可以为如硅通孔等贯穿电极。即，图12中，嵌入重新布线图案层30上先形成下侧密封部件60，去除下侧密封部件60的一部分来形成露出嵌入重新布线图案层30的重新布线图案34的开口部之后，可向所述开口部填充导电物来形成导电柱50。
参照图16，可利用研磨、回蚀或者机械化学抛光(mechanicalchemical polishing，CMP)使下侧密封部件60平坦，由此能够露出导电性柱50。如上所述，从嵌入重新布线图案层30计算，导电柱50的高度可高于下侧半导体芯片40的高度，因此，下侧半导体芯片40通过下侧密封部件60不露出地嵌入。
参照图17，在下侧密封部件60的下侧形成与导电柱50电连接的外侧重新布线图案层70。外侧重新布线图案层70可包括第三绝缘层72、外侧重新布线图案74、第四绝缘层76及外侧焊盘78。例如，在下侧密封部件60上形成第三绝缘层72，去除第三绝缘层72的一部分来露出导电柱50。接着，形成与露出的导电柱50电连接且向第三绝缘层72的上侧延伸的外侧重新布线图案74。外侧重新布线图案74可通过蒸镀、镀金等多种方法形成。外侧重新布线图案74上形成第四绝缘层76，去除第四绝缘层76的一部分，以便露出外侧重新布线图案74的一部分。露出的外侧重新布线图案74上可通过后续工序粘贴外侧连接部件80(参照图18)等。选择性地，可在露出的外侧重新布线图案74上进一步形成外侧焊盘78。
并且，外侧重新布线图案层70可由预先制造的基板构成，通过压制、粘结、回流等粘结到导电柱50及下侧密封部件60的情况也包括在本发明的技术思想范围内。
参照图18，在外侧重新布线图案层70上粘贴电连接的外侧连接部件80。外侧连接部件80可粘贴到露出的外侧重新布线图案74，或者粘贴到外侧焊盘78。外侧连接部件80可包括导电物，例如可包括金属。外侧连接部件80可以为焊锡。
接着，去除第二承载基板18，完成图1的半导体封装1。
以上说明的本发明的技术思想不限于前述实施例以及附图，本发明的技术思想所属技术领域的技术人员明确可知在不脱离本发明的技术思想的范围内可进行各种替换、变形及变更。

Claims (12)

1.一种半导体封装，其包括：
嵌入重新布线图案层；
上侧半导体芯片，位于所述嵌入重新布线图案层的上侧；
上侧密封部件，密封所述上侧半导体芯片；
下侧半导体芯片，位于所述嵌入重新布线图案层的下侧；以及
下侧密封部件，密封成不露出所述下侧半导体芯片。
2.根据权利要求1所述的半导体封装，其特征在于，还包括：
导电柱，与所述嵌入重新布线图案层电连接；以及
外侧连接部件，与所述导电柱电连接。
3.根据权利要求2所述的半导体封装，其特征在于，还包括外侧重新布线图案层，其位于所述下侧密封部件的下侧，将所述导电柱和所述外侧连接部件电连接。
4.根据权利要求2所述的半导体封装，其特征在于，所述外侧连接部件的一部分位于所述下侧半导体芯片的下侧。
5.根据权利要求1所述的半导体封装，其特征在于，所述上侧密封部件和所述下侧密封部件相互连接，密封成不露出所述嵌入重新布线图案层。
6.根据权利要求1所述的半导体封装，其特征在于，所述下侧密封部件贯穿所述嵌入重新布线图案层的一部分而与所述上侧密封部件连接。
7.根据权利要求1所述的半导体封装，其特征在于，所述上侧半导体芯片和所述下侧半导体芯片通过所述嵌入重新布线图案层相互电连接。
8.根据权利要求1所述的半导体封装，其特征在于，所述下侧半导体芯片包括多个下侧半导体芯片。
9.根据权利要求8所述的半导体封装，其特征在于，还包括与所述嵌入重新布线图案层电连接，并嵌入所述密封部件的多个导电柱，
所述导电柱的一部分位于所述多个下侧半导体芯片之间。
10.根据权利要求1所述的半导体封装，其特征在于，所述上侧半导体芯片包括多个上侧半导体芯片。
11.根据权利要求1所述的半导体封装，其特征在于，所述上侧半导体芯片和所述下侧半导体芯片具有相同大小。
12.一种半导体封装的制造方法，其包括：
在第一承载基板上粘贴上侧半导体芯片的步骤；
形成密封所述上侧半导体芯片的上侧密封部件的步骤；
在所述上侧密封部件上粘贴第二承载基板的步骤；
去除所述第一承载基板，露出所述上侧半导体芯片的步骤；
在所述露出的上侧半导体芯片及所述上侧密封部件上形成嵌入重新布线图案层的步骤；
形成与所述嵌入重新布线图案层电连接的导电柱的步骤；
在所述嵌入重新布线图案层的下侧以与所述上侧半导体芯片相反的位置粘贴下侧半导体芯片的步骤；
形成密封所述下侧半导体芯片及所述导电柱的下侧密封部件的步骤；
使所述下侧密封部件平坦以露出所述导电柱的步骤；
在所述下侧密封部件上形成与所述导电柱电连接的外侧重新布线图案层的步骤；以及
在所述外侧重新布线图案层上以电连接的方式粘贴外侧连接部件的步骤。
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