CN105489565A - 嵌埋元件的封装结构及其制法 - Google Patents

嵌埋元件的封装结构及其制法 Download PDF

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Publication number
CN105489565A
CN105489565A CN201410513135.8A CN201410513135A CN105489565A CN 105489565 A CN105489565 A CN 105489565A CN 201410513135 A CN201410513135 A CN 201410513135A CN 105489565 A CN105489565 A CN 105489565A
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China
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layer
embedded
line layer
perforate
encapsulating structure
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CN201410513135.8A
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CN105489565B (zh
Inventor
邱士超
林俊贤
白裕呈
萧惟中
孙铭成
沈子杰
陈嘉成
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

一种嵌埋元件的封装结构及其制法，在承载板上形成第一线路层后，移除该承载板并将该第一线路层接置于结合层上。接着于该第一线路层上接置电子元件，并依序形成封装层、第二线路层及绝缘层，并以包覆层包覆设置于该电子元件及该第二线路层上的晶片。通过本发明能够有效减少封装结构的厚度，且能在不须使用粘着剂的情况下固定该电子元件。

Description

嵌埋元件的封装结构及其制法
技术领域
本发明有关一种封装结构及其制法，尤指一种嵌埋元件的封装结构及其制法。
背景技术
电子产业近年来的蓬勃发展，电子产品逐渐要求薄型化。为满足此一薄型化的需求，减少基板厚度成为薄型化其中一个重要的发展方向。此外，生产效率的提升与成本的降低也为技术研发的重点之一。
请参阅图1，其为现有晶片尺寸封装结构的示意图。该晶片尺寸封装结构包括硬质板20、第一线路层21a、第二线路层21b、导电元件22、包覆层25及电子元件23。该硬质板20具有相对应的第一表面20a及第二表面20b，于该硬质板20第一表面20a及第二表面20b上分别设有第一线路层21a及第二线路层21b，且该第一线路层21a电性连接该第二线路层21b，该第一线路层21a并具有多个连接垫211。
该些导电元件22形成于连接垫211上，该电子元件23包埋于该包覆层25中，电子元件23具有作用面23a及非作用面23b，且该作用面23a具有多个电极垫231。
而该电子元件23设置于该包覆层25中的流程，为先将电子元件23设置于该包覆层25上后，加热包覆层25，然后压合该电子元件23与硬质板20，以使该电子元件23被包覆于包覆层25中，且令该电子元件23的非作用面23b接置于该硬质板20上。此外，该非作用面23b上粘附有粘晶膜24。
然而，现有晶片尺寸封装结构必须使用硬质板20，导致整体封装结构的厚度较厚，进而使得封装结构的体积较高。而电子元件23以黏晶膜24接置于硬质板20上，亦提高了材料成本，更降低了生产效率。
因此，如何提供一种嵌埋元件的封装结构及其制法，能避免上述现有技术的缺失，有效减少封装结构的厚度，并能降低工艺成本并提高生产效率，实为一重要课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种嵌埋元件的封装结构及其制法，能够有效减少封装结构的厚度，且能在不须使用粘着剂的情况下固定该电子元件。
本发明的嵌埋元件的封装结构的制法，包括：提供一结合垫，其上形成具有相对的第一表面与第二表面的第一线路层，且接置有电子元件，其中，该结合垫接置于该第一线路层的第二表面侧；形成封装层于该第一线路层上以包覆该电子元件，其中，该封装层具有至少一外露部份该第一线路层的第一表面的第一开孔；以及形成第二线路层于该封装层上，其中，该第二线路层的部分填入该第一开孔内，以电性连接该第一线路层。
本发明还提供一种嵌埋元件的封装结构，包括：封装层，其具有相对的第一表面及第二表面，且该封装层具有多个连通至该第二表面的第一开孔；第一线路层，其嵌埋于该封装层中并外露于该封装层的第一表面；电子元件，其嵌埋于该封装层中并外露于该封装层的第一表面；以及第二线路层，其形成于该封装层的第二表面上，且该第二线路层的部分填入该第一开孔内，以电性连接该第一线路层。
由上可知，本发明的嵌埋元件的封装结构及其制法，移除承载件后，将第一线路层及电子元件接置于结合垫上，并进行后续封装工艺，而不需使用如硬质板等作为承载件，能够有效减少封装结构的厚度，达到电子产品薄型化的需求。此外，本发明利用结合垫固定电子元件，而不需使用粘着材料，更能降低工艺成本并提高生产效率。
附图说明
图1为现有晶片尺寸封装结构的示意图；以及
图2A至图2K为本发明嵌埋元件的封装结构的制法示意图，其中，图2E’为图2E的另一实施方式；图2J’为图2J的另一实施方式。
符号说明
20硬质板
20a、3021、3041、3074第一表面
20b、3022、3042、3075第二表面
21a、304第一线路层
21b、309第二线路层
211、310连接垫
22导电元件
23、306电子元件
23a作用面
23b非作用面
231电极垫
24黏晶膜
25包覆层
30嵌埋元件的封装结构
301承载件
302种子层
3023第二开孔
303、303'图案化光阻层
305结合垫
307封装层
3071第一开孔
3072感光型材料
3073光罩
3076凹槽
308晶种层
311第一绝缘层
3111第三开孔
312第二绝缘层
3121容置空间
3122第四开孔
313导电体
314晶片
3141顶面
3142侧面
3143底面
315包覆层。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「上」、「第一」、「第二」、「顶」、「侧」及「底」等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2K，其为本发明嵌埋元件的封装结构的制法示意图。
如图2A所示，提供一承载件301，并于该承载件301上形成种子层302，该种子层302具有第一表面3021及相对的第二表面3022。该种子层302以无电镀(Electro-less)法或溅镀法形成。于本实施例中，该承载件301为表面具有胶材或离型材的玻璃板或金属板。
接着，于该种子层302的第一表面3021上设置图案化光阻层303，以部份外露该种子层302。
如图2B所示，于该种子层302的第一表面3021的外露部份上以电镀方式形成第一线路层304，该第一线路层304具有相对的第一表面3041及第二表面3042。其中，该第一线路层304的材料可为铜。接着移除该图案化光阻层303。
如图2C所示，移除图案化光阻层303后，形成贯通该种子层302的第二开孔3023，并移除该承载件301。于一实施例中，可先移除该承载件301后再形成该第二开孔3023，也可先形成该第二开孔3023后再移除该承载件301。
于本实施例中，该第二开孔3023以机械钻孔或激光钻孔的方式形成，也可以蚀刻方式形成。
如图2D所示，提供一结合垫305，自该种子层302侧接置该结合垫305，即将该种子层302的第二表面3022接置于该结合垫305上，以承载该第一线路层304，并以该第二开孔3023外露部份该结合垫305。而在第二开孔3023中外露该结合垫305的部份上接置电子元件306。
于本实施例中，该结合垫305可为胶带。而该电子元件306可为主动元件或被动元件，如多层陶瓷电容(Multi-layerCeramicCapacitor,MLCC)。
如图2E所示，形成封装层307于该第一线路层304及该种子层302上，且该封装层307完整包覆该电子元件306且部份包覆该第一线路层304。而该封装层307的形成，是将环氧树脂以压合(lamination)或模压(molding)的方式形成于该第一线路层304上。接着以激光钻孔的方式，形成至少一第一开孔3071。该第一开孔3071部份外露该第一线路层304的第一表面3041。
于一实施例中，该封装层307也可以曝光显影的方式形成。如图2E’所示，于该第一线路层304的第一表面3041及该种子层302上涂布感光型材料3072，并以一光罩3073进行曝光显影，去除未显影的感光型材料3072，留下已曝光的感光型材料3072以形成该封装层307及该第一开孔3071。
于该封装层307上及该第一开孔3071中，以无电镀(Electro-less)法或溅镀法形成晶种层308，如图2F所示。其中，该晶种层308的材料可为铜，该晶种层308作为后续电镀工艺时的电流路径。
如图2G所示，移除该结合垫305后，于晶种层308上形成图案化光阻层303’，以外露部份该晶种层308。且该图案化光阻层303’不覆盖于该第一开孔3071上。
如图2H所示，于该晶种层308的外露部份上以电镀方式形成第二线路层309后，移除该图案化光阻层303’。其中，该第二线路层309的材料可为铜。另于该第一线路层304的第二表面3042上的该种子层302的第二表面3022上，形成多个具备电性的连接垫310。其中，该多个连接垫310可以设置图案化的光阻层后以电镀方式形成，以电性连接该种子层302及该第一线路层304的第二表面3042，且可在形成该第二线路层309之前、同时或之后，形成该多个连接垫310。于另一实施例中，也可先形成第二线路层309，然后才移除结合垫305。
于本实施例中，该第二线路层309形成于该封装层307上，且该第二线路层309的部份填入该封装层307的第一开孔3071中，并电性连接该晶种层308及该第一线路层304的第一表面3041。
如图2I所示，移除该晶种层308中未被该第二线路层309所覆盖者，以及移除该种子层302中未被该多个连接垫310所覆盖者。移除方式可以蚀刻法进行。
如图2J所示，形成第一绝缘层311于该封装层307上，且该封装层307具有第三开孔3111。该第一绝缘层311包覆部份该第二线路层309，并以该第三开孔3111外露该第一开孔3071内的该第二线路层309。其中，该第三开孔3111与该第一开孔3071大小相同，亦即该第一开孔3071的侧面与该第三开孔3111的侧面齐平。于另一实施例中，该第三开孔3111可大于或小于该第一开孔3071，亦即外露部份该封装层307，或覆盖部份该第二线路层309。
于该封装层307的另一面上，即于该第一线路层304的第二表面3042侧的该封装层307及该第一线路层304上形成第二绝缘层312。该第二绝缘层312定义有一容置空间3121，以外露部份该第一线路层304、部份该封装层307、该多个连接垫310及该电子元件306。
于一实施例中，如图2J’所示，可不形成该多个连接垫310，而是以该第二绝缘层312部份外露该第一线路层304或该电子元件306的多个第四开孔3122的大小，来界定后续多个导电体313与该第一线路层304、该电子元件306的接触面积。
于本实施例中，该第一绝缘层311及该第二绝缘层312的材质为绿漆(soldermask)。
如图2K所示，提供一晶片314，先于该晶片314上形成多个导电体313，接着通过该多个导电体313将该晶片314接置于该多个连接垫310及该电子元件306上，以使该晶片314通过该多个导电体313电性连接至该第一线路层304、该第二线路层309或该电子元件306。其中，该多个导电体313可为焊锡凸块或铜柱。
于另一实施例中，接续图2J’，将晶片314及多个导电体313接置于该多个第四开孔3122，以电性连接该第一线路层304。
接着形成包覆层315于该封装层307的第一表面3074上，即该容置空间3121中，该包覆层315的材质可为封装化合物(moldingcompound)或底部填胶(underfill)。该包覆层315包覆该第一线路层304、该电子元件306、该多个导电体313、该封装层307，以及该晶片314的侧面3142与底面3143，并外露该晶片314的顶面3141。最后，得到本发明的嵌埋元件的封装结构30。
本发明还提供一种嵌埋元件的封装结构30，请再参阅图2K。该嵌埋元件的封装结构30包括第一绝缘层311、封装层307、第二线路层309、第一线路层304、电子元件306以及多个导电体313。
该封装层307具有相对的第一表面3074及第二表面3075，且该封装层307具有多个连通至该第二表面3075的第一开孔3071。该第一线路层304嵌埋于该封装层307中并外露于该封装层307的第一表面3074。该电子元件306亦嵌埋于该封装层307的凹槽3076中并外露于该封装层307的第一表面3074。
于本实施例中，该封装层307的材质为感光性材料或环氧树脂。该电子元件306可为主动元件或被动元件，如多层陶瓷电容(Multi-layerCeramicCapacitor,MLCC)。该第一线路层304的第二表面3042与该封装层307的第一表面3074齐平。
该第一绝缘层311形成于该封装层307的第二表面3075上，并具有多个对应该第一开孔3071的第三开孔3111。该第二线路层309也形成于该封装层307的第二表面3075上，即该第二线路层309的部份嵌埋于该第一绝缘层311中，并接置该封装层307的第二表面3075。且该第二线路层309的部份填入该第一开孔3071内，并延伸至该第三开孔3111中，以电性连接该第一线路层304。另该多个导电体313形成于该第一线路层304及该电子元件306上。
于本实施例中，该嵌埋元件的封装结构30还包括第二绝缘层312、多个连接垫310、晶片314以及包覆层315。
该多个连接垫310形成于电性连接该第二线路层309的第一线路层304的第二表面3042上。
第二绝缘层312形成于该封装层307的第一表面3074及该第一线路层304上，并以该第二绝缘层312、该封装层307及该第一线路层304定义出一容置空间3121。
将形成有多个导电体313的晶片314设置于该多个连接垫310上或第一线路层304上，以电性连接至该第一线路层304、该第二线路层309或该电子元件306。而包覆层315则是填充于该容置空间3121中，以包覆该多个导电体313、该第一线路层304、该封装层307，以及该晶片314的侧面3142与底面3143，并外露该晶片314的顶面3141。
于本实施例中，该第一绝缘层311及该第二绝缘层312的材质为绿漆(soldermask)，而该多个导电体313可为焊锡凸块或铜柱。
藉由本发明的嵌埋元件的封装结构及其制法，能在承载件上形成第一线路层后，移除该承载件，并将该第一线路层及电子元件接置于结合垫上，以进行后续封装工艺，而不需使用如硬质板等作为承载件，据此能够有效减少封装结构的厚度，达到电子产品薄型化的需求。此外，本发明利用结合垫搭配封装层以固定电子元件，不需使用粘着材料，因此具备能降低工艺成本并提高生产效率的功效。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (33)

1.一种嵌埋元件的封装结构的制法，包括：
提供一结合垫，其上形成具有相对的第一表面与第二表面的第一线路层，且接置有电子元件，其中，该结合垫接置于该第一线路层的第二表面侧；
形成封装层于该第一线路层上以包覆该电子元件，其中，该封装层具有至少一外露部份该第一线路层的第一表面的第一开孔；以及
形成第二线路层于该封装层上，其中，该第二线路层的部分填入该第一开孔内，以电性连接该第一线路层。
2.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，于形成该第二线路层后，还包括形成第一绝缘层于该封装层上，其中，该第一绝缘层具有外露该第一开孔内的第二线路层的第三开孔。
3.如权利要求2所述的嵌埋元件的封装结构的制法，其特征为，该第一开孔的侧面与该第三开孔的侧面齐平。
4.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，该制法还包括移除该结合垫的步骤。
5.如权利要求4所述的嵌埋元件的封装结构的制法，其特征为，于形成该第二线路层后，还包括于该第一线路层的第二表面侧的封装层及第一线路层上形成第二绝缘层的步骤。
6.如权利要求5所述的嵌埋元件的封装结构的制法，其特征为，该第二绝缘层外露部份该第一线路层或该电子元件。
7.如权利要求4所述的嵌埋元件的封装结构的制法，其特征为，该制法还包括于形成该第二线路层之前、同时或之后，形成多个连接垫于该第一线路层的第二表面上。
8.如权利要求7所述的嵌埋元件的封装结构的制法，其特征为，该制法还包括先于一晶片上形成多个导电体，接着通过该多个导电体将该晶片接置于该多个连接垫及该电子元件上。
9.如权利要求4所述的嵌埋元件的封装结构的制法，其特征为，该制法还包括先于一晶片上形成多个导电体，接着通过该多个导电体将该晶片接置于该第一线路层及该电子元件上。
10.如权利要求8或9所述的嵌埋元件的封装结构的制法，其特征为，该制法还包括形成包覆层以包覆该晶片。
11.如权利要求10所述的嵌埋元件的封装结构的制法，其特征为，该晶片的顶面外露于该包覆层。
12.如权利要求8或9所述的嵌埋元件的封装结构的制法，其特征为，该多个导电体为焊锡凸块或铜柱。
13.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，于该结合垫上形成该第一线路层还包括下述步骤：
于一承载件上形成种子层；
于该种子层上形成外露部份该种子层的图案化光阻层，以令该第一线路层形成于该外露的种子层上；
移除该图案化光阻层；
移除该承载件且形成贯通该种子层的第二开孔；
自该种子层侧接置该结合垫，以承载该第一线路层；以及
于该第二开孔中的该结合垫上接置该电子元件。
14.如权利要求13所述的嵌埋元件的封装结构的制法，其特征为，先形成贯通该种子层的第二开孔，再移除该承载件。
15.如权利要求13所述的嵌埋元件的封装结构的制法，其特征为，先移除该承载件，再形成贯通该种子层的第二开孔。
16.如权利要求13所述的嵌埋元件的封装结构的制法，其特征为，该第二开孔以蚀刻、机械钻孔或激光钻孔的方式形成。
17.如权利要求13所述的嵌埋元件的封装结构的制法，其特征为，该承载件为表面具有胶材或离型材的玻璃板或金属板。
18.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，该封装层的形成还包括涂布感光型材料于该第一线路层的第一表面上，并以一光罩进行曝光显影，以形成该封装层及该第一开孔。
19.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，该封装层的形成还包括将环氧树脂以压合或模压方式形成于该第一线路层上，并以激光钻孔的方式，以形成该第一开孔。
20.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，该电子元件为主动元件或被动元件。
21.如权利要求1所述的嵌埋元件的封装结构的制法，其特征为，该结合垫为胶带。
22.一种嵌埋元件的封装结构，包括：
封装层，其具有相对的第一表面及第二表面，且该封装层具有多个连通至该第二表面的第一开孔；
第一线路层，其嵌埋于该封装层中并外露于该封装层的第一表面；
电子元件，其嵌埋于该封装层中并外露于该封装层的第一表面；以及
第二线路层，其形成于该封装层的第二表面上，且该第二线路层的部分填入该第一开孔内，以电性连接该第一线路层。
23.如权利要求22所述的嵌埋元件的封装结构，其特征为，该结构还包括第一绝缘层，其形成于该封装层的第二表面上，且该第一绝缘层具有多个对应该第一开孔的第三开孔。
24.如权利要求23所述的嵌埋元件的封装结构，其特征为，该第二线路层的部分填入该第一开孔内并延伸至该第三开孔中。
25.如权利要求22所述的嵌埋元件的封装结构，其特征为，该结构还包括第二绝缘层，其形成于该封装层的第一表面上及该第一线路层上，并外露部份该第一线路层或该电子元件。
26.如权利要求22所述的嵌埋元件的封装结构，其特征为，该结构还包括晶片，该晶片形成有多个导电体，该多个导电体电性连接该第一线路层。
27.如权利要求26所述的嵌埋元件的封装结构，其特征为，该结构还包括包覆层，形成于该封装层的第一表面上，以包覆该晶片。
28.如权利要求27所述的嵌埋元件的封装结构，其特征为，该晶片的顶面外露于该包覆层。
29.如权利要求26所述的嵌埋元件的封装结构，其特征为，该多个导电体为焊锡凸块或铜柱。
30.如权利要求26所述的嵌埋元件的封装结构，其特征为，该结构还包含多个连接垫，其形成于该第一线路层与该多个导电体之间。
31.如权利要求22所述的嵌埋元件的封装结构，其特征为，该第一线路层的第二表面与该封装层的第一表面齐平。
32.如权利要求22所述的嵌埋元件的封装结构，其特征为，该封装层的材质为感光型材料或环氧树脂。
33.如权利要求22所述的嵌埋元件的封装结构，其特征为，该电子元件为主动元件或被动元件。
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