TW201611135A - 嵌埋元件之封裝結構及其製法 - Google Patents

嵌埋元件之封裝結構及其製法 Download PDF

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Publication number
TW201611135A
TW201611135A TW103131508A TW103131508A TW201611135A TW 201611135 A TW201611135 A TW 201611135A TW 103131508 A TW103131508 A TW 103131508A TW 103131508 A TW103131508 A TW 103131508A TW 201611135 A TW201611135 A TW 201611135A
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Taiwan
Prior art keywords
layer
package structure
embedded component
circuit layer
component according
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TW103131508A
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English (en)
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TWI582861B (zh
Inventor
邱士超
林俊賢
白裕呈
蕭惟中
孫銘成
沈子傑
陳嘉成
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103131508A priority Critical patent/TWI582861B/zh
Priority to CN201410513135.8A priority patent/CN105489565B/zh
Priority to US14/692,769 priority patent/US9716060B2/en
Publication of TW201611135A publication Critical patent/TW201611135A/zh
Application granted granted Critical
Publication of TWI582861B publication Critical patent/TWI582861B/zh
Priority to US15/625,083 priority patent/US10002825B2/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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Abstract

一種嵌埋元件之封裝結構及其製法，係在承載板上形成第一線路層後，移除該承載板並將該第一線路層接置於結合層上。接著於該第一線路層上接置電子元件，並依序形成封裝層、第二線路層及絕緣層，並以包覆層包覆設置於該電子元件及該第二線路層上的晶片。藉由本發明能夠有效減少封裝結構之厚度，且能在不須使用黏著劑的情況下固定該電子元件。

Description

嵌埋元件之封裝結構及其製法
本發明係有關一種封裝結構及其製法，尤指一種嵌埋元件之封裝結構及其製法。
電子產業近年來的蓬勃發展，電子產品逐漸要求薄型化。為滿足此一薄型化的需求，減少基板厚度成為薄型化其中一個重要的發展方向。此外，生產效率的提昇與成本之降低亦為技術研發的重點之一。
請參閱第1圖，係為習知晶片尺寸封裝結構之示意圖。該晶片尺寸封裝結構包括硬質板20、第一線路層21a、第二線路層21b、導電元件22、包覆層25及電子元件23。該硬質板20具有相對應之第一表面20a及第二表面20b，於該硬質板20第一表面20a及第二表面20b上分別設有第一線路層21a及第二線路層21b，且該第一線路層21a電性連接該第二線路層21b，該第一線路層21a並具有複數連接墊211。
該些導電元件22係形成於連接墊211上，該電子元件23包埋於該包覆層25中，電子元件23具有作用面23a及 非作用面23b，且該作用面23a具有複數電極墊231。
而該電子元件23設置於該包覆層25中之流程，係先將電子元件23設置於該包覆層25上後，加熱包覆層25，然後壓合該電子元件23與硬質板20，俾使該電子元件23被包覆於包覆層25中，且令該電子元件23之非作用面23b接置於該硬質板20上。此外，該非作用面23b上係黏附有黏晶膜24。
然而，習知晶片尺寸封裝結構必須使用硬質板20，導致整體封裝結構之厚度較厚，進而使得封裝結構之體積較高。而電子元件23以黏晶膜24接置於硬質板20上，亦提高了材料成本，更降低了生產效率。
因此，如何提供一種嵌埋元件之封裝結構及其製法，能避免上述習知技術之缺失，有效減少封裝結構之厚度，並能降低製程成本並提高生產效率，實為一重要課題。
鑒於上述習知技術之缺失，本發明係提供一種嵌埋元件之封裝結構之製法，係包括：提供一結合墊，其上形成具有相對之第一表面與第二表面的第一線路層，且接置有電子元件，其中，該結合墊係接置於該第一線路層之第二表面側；形成封裝層於該第一線路層上以包覆該電子元件，其中，該封裝層具有至少一外露部份該第一線路層之第一表面之第一開孔；以及形成第二線路層於該封裝層上，其中，該第二線路層之部分係填入該第一開孔內，以電性連接該第一線路層。
本發明復提供一種嵌埋元件之封裝結構，係包括：封裝層，係具有相對之第一表面及第二表面，且該封裝層具有複數連通至該第二表面之第一開孔；第一線路層，係嵌埋於該封裝層中並外露於該封裝層之第一表面；電子元件，係嵌埋於該封裝層中並外露於該封裝層之第一表面；以及第二線路層，係形成於該封裝層之第二表面上，且該第二線路層之部分係填入該第一開孔內，以電性連接該第一線路層。
由上可知，本發明之嵌埋元件之封裝結構及其製法，係移除承載件後，將第一線路層及電子元件接置於結合墊上，並進行後續封裝製程，而不需使用如硬質板等作為承載件，能夠有效減少封裝結構之厚度，達到電子產品薄型化之需求。此外，本發明利用結合墊固定電子元件，而不需使用黏著材料，更能降低製程成本並提高生產效率。
20‧‧‧硬質板
20a、3021、3041、3074‧‧‧第一表面
20b、3022、3042、3075‧‧‧第二表面
21a、304‧‧‧第一線路層
21b、309‧‧‧第二線路層
211、310‧‧‧連接墊
22‧‧‧導電元件
23、306‧‧‧電子元件
23a‧‧‧作用面
23b‧‧‧非作用面
231‧‧‧電極墊
24‧‧‧黏晶膜
25‧‧‧包覆層
30‧‧‧嵌埋元件之封裝結構
301‧‧‧承載件
302‧‧‧種子層
3023‧‧‧第二開孔
303、303'‧‧‧圖案化光阻層
305‧‧‧結合墊
307‧‧‧封裝層
3071‧‧‧第一開孔
3072‧‧‧感光型材料
3073‧‧‧光罩
3076‧‧‧凹槽
308‧‧‧晶種層
311‧‧‧第一絕緣層
3111‧‧‧第三開孔
312‧‧‧第二絕緣層
3121‧‧‧容置空間
3122‧‧‧第四開孔
313‧‧‧導電體
314‧‧‧晶片
3141‧‧‧頂面
3142‧‧‧側面
3143‧‧‧底面
315‧‧‧包覆層
第1圖係為習知晶片尺寸封裝結構之示意圖；以及第2A至2K圖係為本發明嵌埋元件之封裝結構之製法示意圖，其中，第2E’圖係第2E圖之另一實施方式；第2J’圖係第2J圖之另一實施方式。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝 之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「頂」、「側」及「底」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
請參閱第2A至2K圖，係為本發明嵌埋元件之封裝結構之製法示意圖。
如第2A圖所示，提供一承載件301，並於該承載件301上形成種子層302，該種子層302具有第一表面3021及相對之第二表面3022。該種子層302係以無電鍍(Electro-less)法或濺鍍法形成。於本實施例中，該承載件301係為表面具有膠材或離型材之玻璃板或金屬板。
接著，於該種子層302之第一表面3021上設置圖案化光阻層303，以部份外露該種子層302。
如第2B圖所示，於該種子層302之第一表面3021的外露部份上以電鍍方式形成第一線路層304，該第一線路層304具有相對之第一表面3041及第二表面3042。其中，該第一線路層304之材料可為銅。接著移除該圖案化光阻層303。
如第2C圖所示，移除圖案化光阻層303後，形成貫 通該種子層302之第二開孔3023，並移除該承載件301。於一實施例中，可先移除該承載件301後再形成該第二開孔3023，亦可先形成該第二開孔3023後再移除該承載件301。
於本實施例中，該第二開孔3023係以機械鑽孔或雷射鑽孔之方式形成，亦可以蝕刻方式形成。
如第2D圖所示，提供一結合墊305，自該種子層302側接置該結合墊305，即將該種子層302之第二表面3022接置於該結合墊305上，以承載該第一線路層304，並以該第二開孔3023外露部份該結合墊305。而在第二開孔3023中外露該結合墊305的部份上接置電子元件306。
於本實施例中，該結合墊305可為膠帶。而該電子元件306可為主動元件或被動元件，如多層陶瓷電容(Multi-layer Ceramic Capacitor,MLCC)。
如第2E圖所示，形成封裝層307於該第一線路層304及該種子層302上，且該封裝層307係完整包覆該電子元件306且部份包覆該第一線路層304。而該封裝層307之形成，係將環氧樹脂以壓合(lamination)或模壓(molding)之方式形成於該第一線路層304上。接著以雷射鑽孔之方式，形成至少一第一開孔3071。該第一開孔3071係部份外露該第一線路層304之第一表面3041。
於一實施例中，該封裝層307亦可以曝光顯影之方式形成。如第2E’圖所示，於該第一線路層304之第一表面3041及該種子層302上塗佈感光型材料3072，並以一光罩 3073進行曝光顯影，去除未顯影之感光型材料3072，留下已曝光之感光型材料3072以形成該封裝層307及該第一開孔3071。
於該封裝層307上及該第一開孔3071中，以無電鍍(Electro-less)法或濺鍍法形成晶種層308，如第2F圖所示。其中，該晶種層308之材料可為銅，該晶種層308係作為後續電鍍製程時之電流路徑。
如第2G圖所示，移除該結合墊305後，於晶種層308上形成圖案化光阻層303’，以外露部份該晶種層308。且該圖案化光阻層303’不覆蓋於該第一開孔3071上。
如第2H圖所示，於該晶種層308之外露部份上以電鍍方式形成第二線路層309後，移除該圖案化光阻層303’。其中，該第二線路層309之材料可為銅。另於該第一線路層304之第二表面3042上的該種子層302之第二表面3022上，形成複數具備電性的連接墊310。其中，該複數連接墊310可以設置圖案化的光阻層後以電鍍方式形成，以電性連接該種子層302及該第一線路層304之第二表面3042，且可在形成該第二線路層309之前、同時或之後，形成該複數連接墊310。於另一實施例中，亦可先形成第二線路層309，然後才移除結合墊305。
於本實施例中，該第二線路層309係形成於該封裝層307上，且該第二線路層309之部份係填入該封裝層307之第一開孔3071中，並電性連接該晶種層308及該第一線路層304之第一表面3041。
如第2I圖所示，移除該晶種層308中未被該第二線路層309所覆蓋者，以及移除該種子層302中未被該複數連接墊310所覆蓋者。移除方式可以蝕刻法進行。
如第2J圖所示，形成第一絕緣層311於該封裝層307上，且該封裝層307具有第三開孔3111。該第一絕緣層311係包覆部份該第二線路層309，並以該第三開孔3111外露該第一開孔3071內的該第二線路層309。其中，該第三開孔3111與該第一開孔3071大小相同，亦即該第一開孔3071之側面與該第三開孔3111之側面齊平。於另一實施例中，該第三開孔3111可大於或小於該第一開孔3071，亦即外露部份該封裝層307，或覆蓋部份該第二線路層309。
於該封裝層307之另一面上，即於該第一線路層304之第二表面3042側的該封裝層307及該第一線路層304上形成第二絕緣層312。該第二絕緣層312定義有一容置空間3121，以外露部份該第一線路層304、部份該封裝層307、該複數連接墊310及該電子元件306。
於一實施例中，如第2J’圖所示，可不形成該複數連接墊310，而是以該第二絕緣層312部份外露該第一線路層304或該電子元件306的複數個第四開孔3122之大小，來界定後續複數導電體313與該第一線路層304、該電子元件306的接觸面積。
於本實施例中，該第一絕緣層311及該第二絕緣層312之材質為綠漆(solder mask)。
如第2K圖所示，提供一晶片314，先於該晶片314上 形成複數導電體313，接著透過該複數導電體313將該晶片314接置於該複數連接墊310及該電子元件306上，俾使該晶片314透過該複數導電體313電性連接至該第一線路層304、該第二線路層309或該電子元件306。其中，該複數導電體313可為銲錫凸塊或銅柱。
於另一實施例中，接續第2J’圖，將晶片314及複數導電體313接置於該複數個第四開孔3122，以電性連接該第一線路層304。
接著形成包覆層315於該封裝層307之第一表面3074上，即該容置空間3121中，該包覆層315之材質可為封裝化合物(molding compound)或底部填膠(underfill)。該包覆層315係包覆該第一線路層304、該電子元件306、該複數導電體313、該封裝層307，以及該晶片314之側面3142與底面3143，並外露該晶片314之頂面3141。最後，得到本發明之嵌埋元件之封裝結構30。
本發明復提供一種嵌埋元件之封裝結構30，請再參閱第2K圖。該嵌埋元件之封裝結構30係包括第一絕緣層311、封裝層307、第二線路層309、第一線路層304、電子元件306以及複數導電體313。
該封裝層307具有相對之第一表面3074及第二表面3075，且該封裝層307具有複數連通至該第二表面3075之第一開孔3071。該第一線路層304係嵌埋於該封裝層307中並外露於該封裝層307之第一表面3074。該電子元件306亦嵌埋於該封裝層307之凹槽3076中並外露於該封裝層 307之第一表面3074。
於本實施例中，該封裝層307之材質為感光性材料或環氧樹脂。該電子元件306可為主動元件或被動元件，如多層陶瓷電容(Multi-layer Ceramic Capacitor,MLCC)。該第一線路層304之第二表面3042係與該封裝層307之第一表面3074齊平。
該第一絕緣層311係形成於該封裝層307之第二表面3075上，並具有複數對應該第一開孔3071之第三開孔3111。該第二線路層309亦形成於該封裝層307之第二表面3075上，即該第二線路層309之部份係嵌埋於該第一絕緣層311中，並接置該封裝層307之第二表面3075。且該第二線路層309之部份係填入該第一開孔3071內，並延伸至該第三開孔3111中，以電性連接該第一線路層304。另該複數導電體313係形成於該第一線路層304及該電子元件306上。
於本實施例中，該嵌埋元件之封裝結構30復包括第二絕緣層312、複數連接墊310、晶片314以及包覆層315。
該複數連接墊310係形成於電性連接該第二線路層309之第一線路層304之第二表面3042上。
第二絕緣層312係形成於該封裝層307之第一表面3074及該第一線路層304上，並以該第二絕緣層312、該封裝層307及該第一線路層304定義出一容置空間3121。
將形成有複數導電體313之晶片314設置於該複數連接墊310上或第一線路層304上，以電性連接至該第一線 路層304、該第二線路層309或該電子元件306。而包覆層315則是填充於該容置空間3121中，以包覆該複數導電體313、該第一線路層304、該封裝層307，以及該晶片314之側面3142與底面3143，並外露該晶片314之頂面3141。
於本實施例中，該第一絕緣層311及該第二絕緣層312之材質為綠漆(solder rmask)，而該複數導電體313可為銲錫凸塊或銅柱。
藉由本發明之嵌埋元件之封裝結構及其製法，能在承載件上形成第一線路層後，移除該承載件，並將該第一線路層及電子元件接置於結合墊上，以進行後續封裝製程，而不需使用如硬質板等作為承載件，據此能夠有效減少封裝結構之厚度，達到電子產品薄型化之需求。此外，本發明利用結合墊搭配封裝層以固定電子元件，不需使用黏著材料，因此具備能降低製程成本並提高生產效率之功效。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
30‧‧‧嵌埋元件之封裝結構
302‧‧‧種子層
3076‧‧‧凹槽
304‧‧‧第一線路層
3041、3074‧‧‧第一表面
3042、3075‧‧‧第二表面
306‧‧‧電子元件
307‧‧‧封裝層
3071‧‧‧第一開孔
308‧‧‧晶種層
309‧‧‧第二線路層
310‧‧‧連接墊
311‧‧‧第一絕緣層
3111‧‧‧第三開孔
312‧‧‧第二絕緣層
3121‧‧‧容置空間
313‧‧‧導電體
314‧‧‧晶片
3141‧‧‧頂面
3142‧‧‧側面
3143‧‧‧底面
315‧‧‧包覆層

Claims (33)

  1. 一種嵌埋元件之封裝結構之製法，係包括：提供一結合墊，其上形成具有相對之第一表面與第二表面的第一線路層，且接置有電子元件，其中，該結合墊係接置於該第一線路層之第二表面側；形成封裝層於該第一線路層上以包覆該電子元件，其中，該封裝層具有至少一外露部份該第一線路層之第一表面之第一開孔；以及形成第二線路層於該封裝層上，其中，該第二線路層之部分係填入該第一開孔內，以電性連接該第一線路層。
  2. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，於形成該第二線路層後，復包括形成第一絕緣層於該封裝層上，其中，該第一絕緣層具有外露該第一開孔內之第二線路層之第三開孔。
  3. 如申請專利範圍第2項所述之嵌埋元件之封裝結構之製法，其中，該第一開孔之側面與該第三開孔之側面齊平。
  4. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，復包括移除該結合墊之步驟。
  5. 如申請專利範圍第4項所述之嵌埋元件之封裝結構之製法，於形成該第二線路層後，復包括於該第一線路層之第二表面側之封裝層及第一線路層上形成第二絕緣層之步驟。
  6. 如申請專利範圍第5項所述之嵌埋元件之封裝結構之製法，其中，該第二絕緣層外露部份該第一線路層或該電子元件。
  7. 如申請專利範圍第4項所述之嵌埋元件之封裝結構之製法，復包括於形成該第二線路層之前、同時或之後，形成複數連接墊於該第一線路層之第二表面上。
  8. 如申請專利範圍第7項所述之嵌埋元件之封裝結構之製法，復包括先於一晶片上形成複數導電體，接著透過該複數導電體將該晶片接置於該複數連接墊及該電子元件上。
  9. 如申請專利範圍第4項所述之嵌埋元件之封裝結構之製法，復包括先於一晶片上形成複數導電體，接著透過該複數導電體將該晶片接置於該第一線路層及該電子元件上。
  10. 如申請專利範圍第8或9項所述之嵌埋元件之封裝結構之製法，復包括形成包覆層以包覆該晶片。
  11. 如申請專利範圍第10項所述之嵌埋元件之封裝結構之製法，其中，該晶片之頂面係外露於該包覆層。
  12. 如申請專利範圍第8或9項所述之嵌埋元件之封裝結構之製法，其中，該複數導電體為銲錫凸塊或銅柱。
  13. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，其中，於該結合墊上形成該第一線路層復包括下述步驟：於一承載件上形成種子層； 於該種子層上形成外露部份該種子層之圖案化光阻層，以令該第一線路層形成於該外露之種子層上；移除該圖案化光阻層；移除該承載件且形成貫通該種子層之第二開孔；自該種子層側接置該結合墊，以承載該第一線路層；以及於該第二開孔中的該結合墊上接置該電子元件。
  14. 如申請專利範圍第13項所述之嵌埋元件之封裝結構之製法，其中，係先形成貫通該種子層之第二開孔，再移除該承載件。
  15. 如申請專利範圍第13項所述之嵌埋元件之封裝結構之製法，其中，係先移除該承載件，再形成貫通該種子層之第二開孔。
  16. 如申請專利範圍第13項所述之嵌埋元件之封裝結構之製法，其中，該第二開孔係以蝕刻、機械鑽孔或雷射鑽孔之方式形成。
  17. 如申請專利範圍第13項所述之嵌埋元件之封裝結構之製法，其中，該承載件係為表面具有膠材或離型材之玻璃板或金屬板。
  18. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，其中，該封裝層之形成復包括塗佈感光型材料於該第一線路層之第一表面上，並以一光罩進行曝光顯影，以形成該封裝層及該第一開孔。
  19. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之 製法，其中，該封裝層之形成復包括將環氧樹脂以壓合或模壓方式形成於該第一線路層上，並以雷射鑽孔之方式，以形成該第一開孔。
  20. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，其中，該電子元件係為主動元件或被動元件。
  21. 如申請專利範圍第1項所述之嵌埋元件之封裝結構之製法，其中，該結合墊為膠帶。
  22. 一種嵌埋元件之封裝結構，係包括：封裝層，係具有相對之第一表面及第二表面，且該封裝層具有複數連通至該第二表面之第一開孔；第一線路層，係嵌埋於該封裝層中並外露於該封裝層之第一表面；電子元件，係嵌埋於該封裝層中並外露於該封裝層之第一表面；以及第二線路層，係形成於該封裝層之第二表面上，且該第二線路層之部分係填入該第一開孔內，以電性連接該第一線路層。
  23. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，復包括第一絕緣層，係形成於該封裝層之第二表面上，且該第一絕緣層具有複數對應該第一開孔之第三開孔。
  24. 如申請專利範圍第23項所述之嵌埋元件之封裝結構，其中，該第二線路層之部分係填入該第一開孔內並延伸至該第三開孔中。
  25. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，復包括第二絕緣層，係形成於該封裝層之第一表面上及該第一線路層上，並外露部份該第一線路層或該電子元件。
  26. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，復包括晶片，該晶片係形成有複數導電體，該複數導電體電性連接該第一線路層。
  27. 如申請專利範圍第26項所述之嵌埋元件之封裝結構，復包括包覆層，形成於該封裝層之第一表面上，以包覆該晶片。
  28. 如申請專利範圍第27項所述之嵌埋元件之封裝結構，其中，該晶片之頂面係外露於該包覆層。
  29. 如申請專利範圍第26項所述之嵌埋元件之封裝結構，其中，該複數導電體為銲錫凸塊或銅柱。
  30. 如申請專利範圍第26項所述之嵌埋元件之封裝結構，復包含複數連接墊，係形成於該第一線路層與該複數導電體之間。
  31. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，其中，該第一線路層之第二表面與該封裝層之第一表面齊平。
  32. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，其中，該封裝層之材質為感光型材料或環氧樹脂。
  33. 如申請專利範圍第22項所述之嵌埋元件之封裝結構，其中，該電子元件係為主動元件或被動元件。
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