CN112103193B - 一种嵌埋结构及制备方法、基板 - Google Patents
一种嵌埋结构及制备方法、基板 Download PDFInfo
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Abstract
本发明公开了一种嵌埋结构的制备方法,包括步骤:在临时承载板上制作第二电路层,覆盖第二电路层制作第一介电层,图形影像化处理第一介电层形成贴装器件的空腔,使器件设置有端子的一面朝向空腔的开口测,制备第二介电层,使器件嵌埋于第二介电层内,器件端子表面与第二介电层表面为一预设值,在第二介电层表面制备第一电路层,第一电路层与器件端子直接连接。本发明还公开了一种嵌埋结构,及包含该嵌埋结构的基板,通过本发明的实施,简化了现有技术中嵌埋结构的工艺步骤,根据本申请的端子面朝上配置,使器件与线路一体电镀相连,保证器件与线路的连接稳定性,确保良好的电信号。
Description
技术领域
本发明涉及半导体领域,具体涉及一种嵌埋结构及制备方法、基板。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。电子产品越来越小型化,智能化,相应对构成电子产品内部的核心部件基板以及元器件要求越来越高,轻薄化,稳定的性能成为制作电子产品的关键因素。
如何简化流程实现器件封装模块的轻薄化和稳定的性能成为各大器件厂商要解决的问题。现有技术对器件的嵌埋处理其实施包含两部分,一部分为矩形空腔阵列聚合物框架制作,一部分为依托聚合物框架实施器件嵌埋处理。通过两部分完成的器件嵌埋必然有工序流程复杂,制作成本高,封装体较厚等缺点,且器件与线路的焊接不可避免要在空腔底部完成,致使焊接效果无法直观检查,嵌埋品质无法保证。
现有技术中,器件与线路是通过不同材料焊接而成,此种工艺直接影响了器件与线路之间的电信号连接的稳定性,从而增加了产品的残次率,且器件与线路间通过焊料焊接,器件下方间隙大小不稳定,其间层压介电材料时填充效果不稳定,存在填充不良的隐患,影响产品的可靠性。
发明内容
鉴于上述现有技术的种种不足,本发明的主要目的在于提供一种嵌埋结构及其制备方法、基板,该嵌埋结构及其制备方法、基板,器件嵌埋工序流程简单,封装厚度更薄,器件与线路电信号连接更稳定。本概述并非是为了限制权利要求的保护范围。所述技术方案如下:
第一方面,本申请实施例提供了一种嵌埋结构的制备方法,包括以下步骤:准备临时承载板500;在所述临时承载板500上下表面的至少一面制备第二电路层310,覆盖所述第二电路层310制备第一介电层130;图形影像化处理并固化所述第一介电层130,形成空腔230,在所述空腔230内贴装器件200并热固化,所述器件200设置有端子210的一面朝向所述空腔230的开口侧;制备第二介电层140,所述器件200嵌埋于所述第二介电层140内,且所述第二介电层140表面高于所述端子210表面一预设值;在所述第二介电层140表面制备与所述端子210直接连接的第一电路层300,且贯穿所述第二介电层140制作金属柱400,所述第一电路层300通过所述金属柱400与所述第二电路层310连接;分割所述临时承载板,形成第一阶段嵌埋结构体;在所述第一阶段嵌埋结构体的双面形成焊料掩膜700,并在所述焊料掩膜700上进行开口,露出所述第二电路层310和所述第一电路层300的表面,对所述第二电路层310和所述第一电路层300表面进行金属化处理。
根据本申请的一些实施例,所述准备临时承载板500,在所述临时承载板500上下表面的至少一面制备第二电路层310具体为:准备临时承载板500;在所述临时承载板500上下表面的至少一面层压光刻胶600;所述光刻胶600经曝光,显影得出所述第二电路层310开窗图形;电镀所述开窗图形,去除光刻胶,形成所述第二电路层310。
根据本申请的一些实施例,在所述第二介电层140表面制备与所述端子210直接连接的第一电路层300,且贯穿所述第二介电层140制作金属柱400具体为:通过化学镀铜或者溅射的方式在所述第二介电层140表面形成一层金属种子层320;层压光刻胶600,图形影像化处理所述光刻胶600,露出所述第一电路层300图形及所述金属柱图形410;电镀所述第一电路层300图形及所述金属柱图形410形成所述第一电路层300及金属柱400;其中所述第一电路层300通过种子层320与所述端子210电连接。
根据本申请的一些实施例,所述预设值取值范围为5~30um。
根据本申请的一些实施例,所述临时承载板500为4层对称结构,从中间到两面依次为有机层510,第一金属层520,第二金属层530,防护层540。
根据本申请的一些实施例,在所述空腔230内贴装器件200并热固化具体方法为:通过在所述器件非端子面220施加超薄型薄膜粘合剂,加热使所述器件200与所述空腔下面防护层530直接黏附;或者通过在所述空腔230底部施加黏附材料240,使所述器件200与所述临时承载板500粘接固定。
根据本申请的一些实施例,所述第一介电层130与所述第二介电层140的介电材料为感光型介电材料或非感光型介电材料。
第二方面,本申请实施例提供了一种嵌埋结构的制备方法,包括以下步骤:准备临时承载板500,在所述临时承载板500上下表面的至少一面制备第二电路层310,覆盖所述第二电路层310制备第一介电层130;图形影像化处理并固化所述第一介电层130,露出所述第二电路层310表面,层压光刻胶600后进行图形影像化处理得到金属柱图形410,电镀形成金属柱400;去除光刻胶600,形成空腔230,在所述空腔230内贴装器件200并热固化,所述器件200设置有端子210的一面朝向所述空腔230的开口侧;制备第二介电层140,所述器件200嵌埋于所述第二介电层140内,且所述第二介电层140表面高于所述端子210表面一预设值;在所述第二介电层140表面制备与所述端子210直接连接的第一电路层300,所述第一电路层300通过所述金属柱400与所述第二电路层310连接;分割所述临时承载板,形成第一阶段嵌埋结构体;在所述第一阶段嵌埋结构体的双面形成焊料掩膜700,并在所述焊料掩膜700上进行开口,露出所述第二电路层310和所述第一电路层300的表面,对所述第二电路层310和所述第一电路层300表面进行金属化处理。
第三方面,本申请实施例提供了一种嵌埋结构,包括:介电层100,所述介电层100包括相对设置的第一表面110及第二表面120;嵌埋在所述介电层100的器件200和端子210,所述器件200设置有所述端子210的一面与所述第一表面110差值为一预设值,所述器件200非端子面220与所述第二表面120共面;第一电路层300,设置在所述介电层100的第一表面110,所述第一电路层300与所述端子210直接电连接;第二电路层310,设置在与所述介电层100的第二表面120共面;金属柱400,用于连接所述第一电路层300与所述第二电路层310。
根据本申请的一些实施例,所述预设值取值范围为5~30um。
第四方面,本申请实施例提供了一种基板,包括至少一层所述的一种嵌埋结构。
根据本申请的一种嵌埋结构及其制备方法、基板,至少具有如下有益效果:使用本申请的制备流程,减少了工艺步骤,降低了制造难度,提高了产品品质且降低了制造成本,根据本申请的配置,很好的解决现有方案在器件与电路连接时需要精准涂布焊料的问题,通过端子面朝上配置,经图形影像化处理后,器件与线路一体电镀相连,保证了器件与线路的连接稳定性,能够确保良好的电信号,且在实施的过程中便于通过外观监控检查,通过端子面朝上布置,器件背面经整体涂布的粘性材料或DAF(超薄型薄膜粘合剂)与承载板的承载金属相连,很好的解决了现有技术中端子面朝下时的线路与器件间填充不良的隐患,通过端子面朝上配置,使器件与下方承载板贴装相连,器件与电路层处于同一基准面,进一步降低了封装体的整体厚度。
本申请的附加方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解,其中:
图1a为本申请一个实施例的制备方法的步骤流程图;
图1b为本申请另一个实施例的制备方法的步骤流程图;
图2为本申请一个实施例的整体结构截面示意图;
图3为本申请另一个实施例的整体结构截面示意图;
图4a至图4j是本申请一个实施例的制备流程中间状态的截面图;
图5a至图5l是本申请另一个实施例的制备流程中间状态的截面图。
介电层100、介电层第一表面110、介电层第二表面120、第一介电层130、第二介电层140、器件200、端子210、非端子面220、空腔230、黏附材料240、空腔开窗250、第一电路层300、第二电路层310、种子层320、金属表面层330、金属柱400、金属柱图形410、临时承载板500、有机层510、第一金属层520、第二金属层530、防护层540、分板面550、光刻胶600、焊料掩膜700
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本申请进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本申请,并不用于限定本申请,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本申请所能产生的功效及所能达成的目的下,均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
本部分将详细描述本申请的具体实施例,本申请之较佳实施例在附图中示出,附图的作用在于用图形补充说明书文字部分的描述,使人能够直观地、形象地理解本申请的每个技术特征和整体技术方案,但其不能理解为对本申请保护范围的限制。
在申请的描述中,若干的含义是一个或者多个,多个的含义是两个以上,大于、小于、超过等理解为不包括本数,以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。
为了方便理解本申请实施例提供的一种嵌埋结构,下面结合附图说明一下其具体的结构。首先参考图2及图3,其中,图2中示出了一种嵌埋结构整体结构截面示意图,图3中示出了一种嵌埋结构另一个实施例的整体结构截面示意图。由图2和图3可以看出,一种嵌埋结构主要包括介电层100,介电层100包括第一介电层130,第二介电层140,介电层100还包括相对设置的第一表面110及第二表面120,制作介电层的介电材料一般为有机或无机介电材料一种或多种的混合物,如聚酰亚胺、环氧树脂,双马来酰亚胺,三嗪树脂,陶瓷填料,玻璃纤维等,按功能性要求分目前有感光型和非感光型。可以理解的是,此处可选感光型材料作为介电材料。
如图2,一种嵌埋结构还包括嵌埋在介电层的器件200,端子210,器件200正面设置有端子210,端子210表面与第一表面110差值位于设定范围内,此处为5-30um,可选5um、10um、15um、18um、20um、25um、28um或30um等不同的差值,端子210表面为与第一表面110同方向的一面,非端子面220与第二表面120共面,这样设置可以进一步降低封装后的结构厚度,可以理解的是,器件200可以是裸芯片,IC,BGA等有源器件,其中芯片可以为不同功能的芯片,如CPU芯片,射频驱动芯片或者其他处理器的芯片,也可以是无源器件,在采用无源器件时,可以为电容、电感和电阻。介电层100环绕并包裹器件200设置,介电层100的第一表面110设置有第一电路层300,第一电路层300与器件200的端子直接电连接,可以理解的是,这种连接方式解决了现有方案需要精准涂布焊料的问题,由于器件与线路一体电镀相连,保证了器件与线路的连接稳定性,确保了良好的电信号。与第一电路层300相对的设置有第二电路层310,第二电路层310设置在与介电层100的第二面120,并于第二面120共面,如图2示,第一电路层300与第二电路层310通过金属柱400连接。
图3中示出的一种嵌埋结构的整体结构示意图是该申请的另一个实施例,其与图2的主要结构大致相同,区别点主要在于工艺流程的实施先后,这点将在后续制备流程中详细论述,此处不再赘述。
应当理解的是,在图2或图3中,示出了介电层100中嵌埋两个器件200的具体结构示意图,但是在本申请实施例中,嵌埋在介电层100中的器件200的个数不仅限于两个,也可以是一个或者三个或者多个,但是无论在介电层100中埋设几个器件200,该器件200与其他结构层的连接方式均相同,同样可以理解的是,在本申请实施例中,该嵌埋结构不局限于一层,根据设计需要,可以是两层或者多层,但是无论设计几层,其设计的整体结构是一样的,从上到下依次为第一电路层300,环绕包裹若干器件200和金属柱400的介电层100,第二电路层310,需要说明是,本申请制备方法以一层嵌埋结构包裹两个器件为例进行的示例说明。
为了方便理解本申请实施例提供的一种嵌埋结构,见图2所示,本申请第一实施例提供了一种嵌埋结构的制备方法,如图1a,该方法具体包括如下步骤:
准备临时承载板500;在临时承载板500上下表面的至少一面制备第二电路层310,覆盖第二电路层310制备第一介电层130。
具体的,如图4a、图4b和图4c中所示,图4a中,在承载板防护层540表面层压光刻胶600,经曝光,显影得出第二电路层310的开窗图形,如图4b,电镀第二电路层310,去除光刻胶,层压介电材料形成第一介电层130并进行预固化,如图4c,图形影像化处理第一介电层130,露出第二电路层310上表面,并完全热固化介电材料。
在实际实施的时候,为保证填充效果,介电材料用量一般按照实际需要的填充量计算,此处,介电材料层压后表面应高于第二电路层310表面5-20um,可选5um、10um、15um、18um或20um等不同的差值,介电材料可选有机或无机介电材料一种或多种的混合物,如聚酰亚胺、环氧树脂,双马来酰亚胺,三嗪树脂,陶瓷填料,玻璃纤维等,按功能性要求分目前有感光型和非感光型介电材料,需要说明的是,本实施例选择感光型介电材料制作介电层100,这是因为,使用感光材料时,在经过图形影像化处理将需要裸露的线路或铜柱部分裸露出来后,不需要经镭射,钻孔等减薄工艺加工裸露线路或铜柱表面,使用图形图像化处理即可,提升了生产效率,且经层压整平后无需整体减薄处理,使得介电层100更均匀,在实际实施时,也不会对下方器件构成损害,提高了良品率。使用感光型介电材料压合时加热平台短暂热固化或光固化即可。若介电材料采用非感光型材料时,线路上表面可采用减薄工艺,如磨板或等离子蚀刻等加工方式对介电材料进行整体减薄直至露出线路上表面,也可以采用镭射烧结的方式对线路上表面介电材料进行烧结,得出所需线路上表面。
如图4a中所示,承载板为对称结构,中间为有机层510,从中间到两面依次为有机层510,第一金属层520,第一金属层530,防护层540。可以理解的是,有机层510可选PP等有机材料,第一金属层520可选金属材料诸如如铜,第一金属层530可选金属材料如铜,第一金属层520与第一金属层530为物理压合而成,防护层540是电镀形成的,其材料可以为cu、ti、ni、CuWTi、CuNiCu和CuTiCu等,但不局限于此。承载板的各层厚度可以调节,该实施例给出的是从有机层510计算,需要说明的是,各层可选18um铜层,3um铜层,3-10um防护层,防护层金属可以设置为镍或钛等。在实际制备中,由于承载板是对称结构,制作时在承载板的对称面可以各制作一张题述嵌埋结构,制作好后,进行分板可得两张基板,基板均为网格状的矩阵阵列,包含若干个单元,每个单元有一个或多个器件组合。
图形影像化处理并固化第一介电层130,形成空腔230,在空腔230内贴装器件200并热固化,器件200设置有端子210的一面朝向空腔230的开口侧。
具体的,如图4c和图4d中所示,图形影像化处理第一介电层130,得到用于贴装器件的空腔230,空腔的尺寸可以根据器件尺寸对应设计,在空腔底部施加黏附材料240,黏附材料240存在较多可选方式,用作黏附器件与下方金属层,其通过点胶或印刷等方式实施涂布。黏附材料240可以是有机或无机材料,一般为锡膏、银浆、红胶或绿油等。贴装器件200,器件200具有端子210,以及相对应的非端子面220,贴装时,使器件200的非端子面220与黏附材料240粘接固定并热固化黏附材料240,贴装可采用高精度的常规SMT流程,贴装加回流加热焊接。可以理解的是,黏附材料240还可以不布置,通过器件非端子面220施加DAF(超薄型薄膜粘合剂),贴装时通过加热平台DAF与下方金属层直接黏附。
制备第二介电层140,器件200嵌埋于第二介电层140内,且第二介电层140表面高于器件端子表面一预设值。
具体的,参见图4e中所示,层压介电材料,图形影像化处理介电材料,露出空腔开窗250以及导通金属柱图形410,并热固化介电材料。
此处,为保证填充效果,介电材料用量按填充量计算,高于器件上表面一定厚度,可理解的是,第二介电层高于端子表面210厚度为5-30um,可选5um、10um、15um、18um、20um、25um或30um等不同的差值。
在第二介电层140表面制备与端子210直接连接的第一电路层300,且贯穿第二介电层140制作金属柱400,第一电路层300通过金属柱400与第二电路层310连接。
具体的,参见图4f、图4g中所示,如图4f,在第二介电层140表面具体为端子表面210、导通金属柱图形410内表面和第二介电层140的表面110制作种子层。如图4g,在种子层上,层压光刻胶600,图形影像化处理光刻胶600,露出待镀第一电路层300图形及导通金属柱400图形,电镀第一电路层300图形及导通金属柱400图形得到第一电路层300及金属柱400。
上述步骤可以看出,第一电路层300与器件200的端子面210通过种子层使用电镀的方式直接电连接,可以理解的是,这种连接方式解决了现有方案需要精准涂布焊料的问题,由于器件与线路一体电镀相连,保证了器件与线路的连接稳定性,确保了良好的电信号。
种子层的制作具体为,使用化学镀铜或者溅射的方式在第二介电层140表面形成一层金属种子层320,常用的种子层金属是钛、铜、钛钨合金,但不仅限于上述金属,种子层厚度一般为0.8-5um,可以理解的是,本实施例可选金属溅射的方式,溅射0.1um厚度的钛,1um厚度的铜。
分割临时承载板,形成第一阶段嵌埋结构体。
在第一阶段嵌埋结构体的双面形成焊料掩膜700,并在焊料掩膜700上进行开口,露出第二电路层310和第一电路层300的表面,对第二电路层310和第一电路层300表面进行金属化处理。
具体的,参见图4h、图4i和图4j中所示,如图4h,去除光刻胶600,蚀刻暴漏于第二介电层140表面的种子层320,层压光刻胶600用以保护线路,整版曝光后分板,见图4i,分板时,从第一金属层520与第一金属层530处分板,分别蚀刻分板面540、第一金属层530和防护层540后去除光刻胶600。在分板蚀刻防护层540时,因承载板防护层较薄,本实施例中,防护层540厚度为3-10um,防护层金属可以设置为镍或钛等,和第一金属层530所用金属不同,这样可以采用不同的蚀刻液,且蚀刻量较小,由此,在蚀刻完防护层后对线路层的影响相对可以忽略不计。分板完成后,见图4j中所示,阻焊制作基板上下表面,阻焊制作包括,基板表面处理,阻焊层印刷,热预固化,曝光,显影,热固化处理,之后金属表面处理基板上下表面,形成金属表面层330,得到如图2所示的一种嵌埋结构的基板。
需要说明的是,本申请第一实施例提供的一种嵌埋结构的制备方法步骤流程只是示例了一层嵌埋结构的具体流程,根据需要可以重复上述步骤得到大于一层的嵌埋结构。
本申请另一个实施例的制备方法可以制作出如图3所示的一种嵌埋结构的基板。其制备方法与本申请第一个实施例的制备流程大体相同,见图1b,细节方面有一些差异,具体见如下步骤:
准备临时承载板500,在临时承载板500上下表面的至少一面制备第二电路层310,覆盖第二电路层310制备第一介电层130。
具体的,如图5a、图5b和图5c中所示,图5a中,在承载板防护层540表面层压光刻胶600,经曝光,显影得出第二电路层310的开窗图形,如图4i,电镀第二电路层310,去除光刻胶,层压介电材料形成第一介电层130并进行预固化,如图5c,图形影像化处理第一介电层130,露出第二电路层310上表面,并完全热固化介电材料。
在实际实施的时候,为保证填充效果,介电材料用量一般按照实际需要的填充量计算,此处,介电材料层压后表面应高于第二电路层310表面5-20um,可选5um、10um、15um、18um或20um等不同的差值。
图形影像化处理并固化第一介电层130,露出第二电路层310表面,层压光刻胶600后进行图形影像化处理得到金属柱图形410,电镀形成金属柱400;
去除光刻胶600,形成空腔230,在空腔230内贴装器件200并热固化,器件200设置有端子210的一面朝向空腔230的开口侧。
具体的,如图5c、图5d、图5e和图5f中所示,如图5c示,图形影像化处理第一介电层130,得到用于贴装器件的空腔230,层压光刻胶600之后进行图形影像化处理,得到导通金属柱图形410,见图5d,图5e中,电镀导通金属柱400,去除光刻胶600,如图5f,在器件空腔230底部施加黏附材料240,贴装器件200,器件200具有端子210,以及相对应的没有设置端子210的非端子面220,贴装时,使器件200的非端子面220与黏附材料240粘接固定并热固化黏附材料240,可以理解的是,黏附材料240还可以不布置,通过器件非端子面220施加DAF(超薄型薄膜粘合剂),贴装时通过加热平台DAF(超薄型薄膜粘合剂)与下方金属层直接黏附。
制备第二介电层140,器件200嵌埋于第二介电层140内,且第二介电层140表面高于端子210表面一预设值;
具体的,参见图5g中所示,层压介电材料,图形影像化处理介电材料,露出空腔开窗250以及金属柱400上表面,并热固化介电材料。
此处,为保证填充效果,介电材料用量按填充量计算,高于器件上表面一定厚度,可理解的是,第二介电层高于端子210表面厚度为5-30um,可选5um、10um、15um、18um、20um、25um或30um等不同的差值。
在第二介电层140表面制备与端子210直接连接的第一电路层300,第一电路层300通过金属柱400与第二电路层310连接。
具体的,参见图5h、图5i中所示,如图5h,在第二介电层140表面具体为端子210表面、金属柱400上表面和第二介电层140的表面110制作种子层。如图5i,在种子层上,层压光刻胶600,图形影像化处理光刻胶600,露出待镀第一电路层300图形,电镀第一电路层300。
上述步骤可以看出,第一电路层300与器件200的端子面210通过种子层使用电镀的方式直接电连接,可以理解的是,这种连接方式解决了现有方案需要精准涂布焊料的问题,由于器件与线路一体电镀相连,保证了器件与线路的连接稳定性,确保了良好的电信号。
种子层的制备与本申请第一实施例中种子层的制备流程相同,此处不再赘述。
分割临时承载板,形成第一阶段嵌埋结构体;
在第一阶段嵌埋结构体的双面形成焊料掩膜700,并在焊料掩膜700上进行开口,露出第二电路层310和第一电路层300的表面,对第二电路层310和第一电路层300表面进行金属化处理。
具体的,参见图5j、图5k和图5l中所示,如图5j,去除光刻胶600,蚀刻暴漏于第二介电层140表面的种子层320,层压光刻胶600用以保护线路,整版曝光后分板,见图5k,分板时,从第一金属层520与第一金属层530处分板,分别蚀刻分板面540、第一金属层530和防护层540后去除光刻胶600。在分板蚀刻防护层540时,因承载板防护层较薄,本实施例中,防护层540厚度为3-10um,防护层金属可以设置为镍或钛等,和第一金属层530所用金属不同,这样可以采用不同的蚀刻液,且蚀刻量较小,由此,在蚀刻完防护层后对线路层的影响相对可以忽略不计。分板完成后,见图5l中所示,阻焊制作基板上下表面,之后实施金属表面处理,形成金属表面层330,得到如图2所示的一种嵌埋结构的基板。
需要说明的是,根据需要,可以重复上述一些中间步骤制备若干层的多层嵌埋结构基板,通过上述流程可以得出,本申请提供的一种嵌埋结构,可以在一次实施制备流程中完成器件嵌埋结构的基板制作,解决了现有技术需要分两部分完成器件嵌埋的问题,由此得到本申请相比现有技术减少了工艺步骤,降低了制造难度,提高了产品品质且降低了制造成本。
由于本申请采用器件嵌埋特征,使得制作过程中能够便于通过外观监控检查器件与电路之间的连接质量。
通过端子面朝上布置,器件背面经整体涂布的粘性材料或DAF(超薄型薄膜粘合剂)与承载板的承载金属相连,很好解决了端子朝下时线路与器件间填充不良的隐患。
通过端子面朝上布置,使器件200与下方承载板通过粘性材料相连,器件200与第二电路层310处于同一基准面,进一步降低了封装体的整体厚度。
以上结合附图对本申请的较佳实施进行了具体说明,但本申请并不局限于上述实施方式,熟悉本领域的技术人员在不违背本申请精神的前提下还可作出种种的等同变形或替换,这些等同的变形或替换均包含在本申请权利要求所限定的范围内。
Claims (11)
1.一种嵌埋结构的制备方法,其特征在于,包括以下步骤:
准备临时承载板(500);在所述临时承载板(500)上下表面的至少一面制备第二电路层(310),覆盖所述第二电路层(310)制备第一介电层(130);
图形影像化处理并固化所述第一介电层(130),形成空腔(230),在所述空腔(230)内贴装器件(200)并热固化,所述器件(200)设置有端子(210)的一面朝向所述空腔(230)的开口侧;
制备第二介电层(140),所述器件(200)嵌埋于所述第二介电层(140)内,且所述第二介电层(140)表面高于所述端子(210)表面一预设值;
在所述第二介电层(140)表面制备与所述端子(210)连接的第一电路层(300),且贯穿所述第二介电层(140)制作金属柱(400),所述第一电路层(300)通过所述金属柱(400)与所述第二电路层(310)连接;
分割所述临时承载板(500),形成第一阶段嵌埋结构体;
在所述第一阶段嵌埋结构体的双面形成焊料掩膜(700),并在所述焊料掩膜(700)上进行开口,露出所述第二电路层(310)和所述第一电路层(300)的表面,对所述第二电路层(310)和所述第一电路层(300)表面进行金属化处理。
2.根据权利要求1所述的一种嵌埋结构的制备方法,其特征在于:在所述临时承载板(500)上下表面的至少一面制备第二电路层(310)的具体方法为:
在所述临时承载板(500)上下表面的至少一面层压光刻胶(600);
对所述光刻胶(600)进行曝光,显影得出所述第二电路层(310)的开窗图形;
电镀所述开窗图形,去除光刻胶,形成所述第二电路层(310)。
3.根据权利要求1所述的嵌埋结构的制备方法,其特征在于,在所述第二介电层(140)表面制备与所述端子(210)直接连接的第一电路层(300),且贯穿所述第二介电层(140)制作金属柱(400)的具体方法为:
通过化学镀铜或者溅射的方式在所述第二介电层(140)表面形成一层金属种子层(320);
层压光刻胶(600),图形影像化处理所述光刻胶(600),露出第一电路层(300)图形及金属柱图形(410);
电镀所述第一电路层(300)图形及所述金属柱图形(410)形成所述第一电路层(300)及金属柱(400);
其中所述第一电路层(300)通过金属种子层(320)直接与所述端子(210)电连接。
4.根据权利要求1所述的嵌埋结构的制备方法,其特征在于,所述预设值取值范围为5~30um。
5.根据权利要求1所述的嵌埋结构的制备方法,其特征在于,所述临时承载板(500)为4层对称结构,从中间到两面依次为有机层(510),第一金属层(520),第二金属层(530),防护层(540)。
6.根据权利要求1所述的嵌埋结构的制备方法,其特征在于,在所述空腔(230)内贴装器件(200)并热固化的具体方法为:
通过在所述器件非端子面(220)施加超薄型薄膜粘合剂,加热使所述器件(200)与所述空腔下面的临时承载板(500)直接黏附;
或者通过在所述空腔(230)底部施加黏附材料(240),使所述器件(200)与所述黏附材料(240)粘接固定。
7.根据权利要求1所述的嵌埋结构的制备方法,其特征在于,所述第一介电层(130)与所述第二介电层(140)的介电材料为感光型介电材料或非感光型介电材料。
8.一种嵌埋结构的制备方法,其特征在于,包括以下步骤:
准备临时承载板(500),在所述临时承载板(500)上下表面的至少一面制备第二电路层(310),覆盖所述第二电路层(310)制备第一介电层(130);
图形影像化处理并固化所述第一介电层(130),露出所述第二电路层(310)表面,层压光刻胶(600)后进行图形影像化处理得到金属柱图形(410),电镀形成金属柱(400);
去除光刻胶(600),形成空腔(230),在所述空腔(230)内贴装器件(200)并热固化,所述器件(200)设置有端子(210)的一面朝向所述空腔(230)的开口侧;
制备第二介电层(140),所述器件(200)嵌埋于所述第二介电层(140)内,且所述第二介电层(140)表面高于所述端子(210)表面一预设值;
在所述第二介电层(140)表面制备与所述端子(210)直接连接的第一电路层(300),所述第一电路层(300)通过所述金属柱(400)与所述第二电路层(310)连接;
分割所述临时承载板(500),形成第一阶段嵌埋结构体;
在所述第一阶段嵌埋结构体的双面形成焊料掩膜(700),并在所述焊料掩膜(700)上进行开口,露出所述第二电路层(310)和所述第一电路层(300)的表面,对所述第二电路层(310)和所述第一电路层(300)表面进行金属化处理。
9.一种嵌埋结构,其特征在于,包括:
介电层(100),所述介电层(100)包括相对设置的第一表面(110)及第二表面(120);
嵌埋在所述介电层(100)的器件(200)和端子(210),所述器件(200)设置有所述端子(210)的一面与所述第一表面(110)差值为一预设值,所述器件(200)非端子面(220)与所述第二表面(120)共面;
第一电路层(300),设置在所述介电层(100)的第一表面(110),所述第一电路层(300)与所述端子(210)直接电连接;
第二电路层(310),设置在与所述介电层(100)的第二表面(120),并与所述介电层(100)的第二表面(120)共面;
金属柱(400),用于连接所述第一电路层(300)与所述第二电路层(310)。
10.根据权利要求9所述的一种嵌埋结构,其特征在于,所述预设值取值范围为5~30um。
11.一种基板,其特征在于,包括至少一层如权利要求9或10任一项所述的一种嵌埋结构。
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