TW202213545A - 嵌埋結構及製備方法、基板 - Google Patents
嵌埋結構及製備方法、基板 Download PDFInfo
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- TW202213545A TW202213545A TW110124421A TW110124421A TW202213545A TW 202213545 A TW202213545 A TW 202213545A TW 110124421 A TW110124421 A TW 110124421A TW 110124421 A TW110124421 A TW 110124421A TW 202213545 A TW202213545 A TW 202213545A
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Abstract
本發明公開了一種嵌埋結構的製備方法,包括步驟:在臨時承載板上製作第二電路層,覆蓋第二電路層製作第一介電層,圖形影像化處理第一介電層形成貼裝器件的空腔,使器件設置有端子的一面朝向空腔的開口測,製備第二介電層,使器件嵌埋於第二介電層內,器件端子表面與第二介電層表面為一預設值,在第二介電層表面製備第一電路層,第一電路層與器件端子直接連接。本發明還公開了一種嵌埋結構,及包含該嵌埋結構的基板,通過本發明的實施,簡化了現有技術中嵌埋結構的工藝步驟,根據本申請的端子面朝上配置,使器件與線路一體電鍍相連,保證器件與線路的連接穩定性,確保良好的電信號。
Description
本發明涉及半導體領域,具體涉及一種嵌埋結構及製備方法、基板。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。電子產品越來越小型化,智慧化,相應對構成電子產品內部的核心部件基板以及元器件要求越來越高,輕薄化,穩定的性能成為製作電子產品的關鍵因素。
如何簡化流程實現器件封裝模組的輕薄化和穩定的性能成為各大器件廠商要解決的問題。現有技術對器件的嵌埋處理其實施包含兩部分,一部分為矩形空腔陣列聚合物框架製作,一部分為依託聚合物框架實施器件嵌埋處理。通過兩部分完成的器件嵌埋必然有工序流程複雜,製作成本高,封裝體較厚等缺點,且器件與線路的焊接不可避免要在空腔底部完成,致使焊接效果無法直觀檢查,嵌埋品質無法保證。
現有技術中,器件與線路是通過不同材料焊接而成,此種工藝直接影響了器件與線路之間的電信號連接的穩定性,從而增加了產品的殘次率,且器件與線路間通過焊料焊接,器件下方間隙大小不穩定,其間層壓介電材料時填充效果不穩定,存在填充不良的隱患,影響產品的可靠性。
鑒於上述現有技術的種種不足,本發明的主要目的在於提供一種嵌埋結構及其製備方法、基板,該嵌埋結構及其製備方法、基板,器件嵌埋工序流程簡單,封裝厚度更薄,器件與線路電信號連接更穩定。本概述並非是為了限制權利要求的保護範圍。所述技術方案如下:
第一方面,本申請實施例提供了一種嵌埋結構的製備方法,包括以下步驟:準備臨時承載板;在所述臨時承載板上下表面的至少一面製備第二電路層,覆蓋所述第二電路層製備第一介電層;圖形影像化處理並固化所述第一介電層,形成空腔,在所述空腔內貼裝器件並熱固化,所述器件設置有端子的一面朝向所述空腔的開口側;製備第二介電層,所述器件嵌埋於所述第二介電層內,且所述第二介電層表面高於所述端子表面一預設值;在所述第二介電層表面製備與所述端子直接連接的第一電路層,且貫穿所述第二介電層製作金屬柱,所述第一電路層通過所述金屬柱與所述第二電路層連接;分割所述臨時承載板,形成第一階段嵌埋結構體;在所述第一階段嵌埋結構體的雙面形成焊料掩膜,並在所述焊料掩膜上進行開口,露出所述第二電路層和所述第一電路層的表面,對所述第二電路層和所述第一電路層表面進行金屬化處理。
根據本申請的一些實施例,所述準備臨時承載板,在所述臨時承載板上下表面的至少一面製備第二電路層具體為:準備臨時承載板;在所述臨時承載板上下表面的至少一面層壓光刻膠;所述光刻膠經曝光,顯影得出所述第二電路層開窗圖形;電鍍所述開窗圖形,去除光刻膠,形成所述第二電路層。
根據本申請的一些實施例,在所述第二介電層表面製備與所述端子直接連接的第一電路層,且貫穿所述第二介電層製作金屬柱具體為:通過化學鍍銅或者濺射的方式在所述第二介電層表面形成一層金屬種子層;層壓光刻膠,圖形影像化處理所述光刻膠,露出所述第一電路層圖形及所述金屬柱圖形;電鍍所述第一電路層圖形及所述金屬柱圖形形成所述第一電路層及金屬柱;其中所述第一電路層通過種子層與所述端子電連接。
根據本申請的一些實施例,所述預設值取值範圍為5~30μm。
根據本申請的一些實施例,所述臨時承載板為4層對稱結構,從中間到兩面依次為有機層,第一金屬層,第二金屬層,防護層。
根據本申請的一些實施例,在所述空腔內貼裝器件並熱固化具體方法為:通過在所述器件非端子面施加超薄型薄膜粘合劑,加熱使所述器件與所述空腔下面防護層直接黏附;或者通過在所述空腔底部施加黏附材料,使所述器件與所述臨時承載板粘接固定。
根據本申請的一些實施例,所述第一介電層與所述第二介電層的介電材料為感光型介電材料或非感光型介電材料。
第二方面,本申請實施例提供了一種嵌埋結構的製備方法,包括以下步驟:準備臨時承載板,在所述臨時承載板上下表面的至少一面製備第二電路層,覆蓋所述第二電路層製備第一介電層;圖形影像化處理並固化所述第一介電層,露出所述第二電路層表面,層壓光刻膠後進行圖形影像化處理得到金屬柱圖形,電鍍形成金屬柱;去除光刻膠,形成空腔,在所述空腔內貼裝器件並熱固化,所述器件設置有端子的一面朝向所述空腔的開口側;製備第二介電層,所述器件嵌埋於所述第二介電層內,且所述第二介電層表面高於所述端子表面一預設值;在所述第二介電層表面製備與所述端子直接連接的第一電路層,所述第一電路層通過所述金屬柱與所述第二電路層連接;分割所述臨時承載板,形成第一階段嵌埋結構體;在所述第一階段嵌埋結構體的雙面形成焊料掩膜,並在所述焊料掩膜上進行開口,露出所述第二電路層和所述第一電路層的表面,對所述第二電路層和所述第一電路層表面進行金屬化處理。
協力廠商面,本申請實施例提供了一種嵌埋結構,包括:介電層,所述介電層包括相對設置的第一表面及第二表面;嵌埋在所述介電層的器件和端子,所述器件設置有所述端子的一面與所述第一表面差值為一預設值,所述器件非端子面與所述第二表面共面;第一電路層,設置在所述介電層的第一表面,所述第一電路層與所述端子直接電連接;第二電路層,設置在與所述介電層的第二表面共面;金屬柱,用於連接所述第一電路層與所述第二電路層。
根據本申請的一些實施例,所述預設值取值範圍為5~30 μm。
第四方面,本申請實施例提供了一種基板,包括至少一層所述的一種嵌埋結構。
根據本申請的一種嵌埋結構及其製備方法、基板,至少具有如下有益效果:使用本申請的製備流程,減少了工藝步驟,降低了製造難度,提高了產品品質且降低了製造成本,根據本申請的配置,很好的解決現有方案在器件與電路連接時需要精准塗布焊料的問題,通過端子面朝上配置,經圖形影像化處理後,器件與線路一體電鍍相連,保證了器件與線路的連接穩定性,能夠確保良好的電信號,且在實施的過程中便於通過外觀監控檢查,通過端子面朝上佈置,器件背面經整體塗布的粘性材料或DAF(超薄型薄膜粘合劑)與承載板的承載金屬相連,很好的解決了現有技術中端子面朝下時的線路與器件間填充不良的隱患,通過端子面朝上配置,使器件與下方承載板貼裝相連,器件與電路層處於同一基準面,進一步降低了封裝體的整體厚度。
本申請的附加方面和優點將在下面的描述中部分給出,部分將從下面的描述中變得明顯,或通過本發明的實踐瞭解到。
為了使本申請的目的、技術方案及優點更加清楚明白,以下結合附圖及實施例,對本申請進行進一步詳細說明。應當理解,此處所描述的具體實施例僅用以解釋本申請,並不用於限定本申請,故不具技術上的實質意義,任何結構的修飾、比例關係的改變或大小的調整,在不影響本申請所能產生的功效及所能達成的目的下,均應仍落在本申請所揭示的技術內容得能涵蓋的範圍內。
本部分將詳細描述本申請的具體實施例,本申請之較佳實施例在附圖中示出,附圖的作用在於用圖形補充說明書文字部分的描述,使人能夠直觀地、形象地理解本申請的每個技術特徵和整體技術方案,但其不能理解為對本申請保護範圍的限制。
在申請的描述中,若干的含義是一個或者多個,多個的含義是兩個以上,大於、小於、超過等理解為不包括本數,以上、以下、以內等理解為包括本數。如果有描述到第一、第二只是用於區分技術特徵為目的,而不能理解為指示或暗示相對重要性或者隱含指明所指示的技術特徵的數量或者隱含指明所指示的技術特徵的先後關係。
為了方便理解本申請實施例提供的一種嵌埋結構,下面結合附圖說明一下其具體的結構。首先參考圖2及圖3,其中,圖2中示出了一種嵌埋結構整體結構截面示意圖,圖3中示出了一種嵌埋結構另一個實施例的整體結構截面示意圖。由圖2和圖3可以看出,一種嵌埋結構主要包括介電層100,介電層100包括第一介電層130,第二介電層140,介電層100還包括相對設置的第一表面110及第二表面120,製作介電層100的介電材料一般為有機或無機介電材料一種或多種的混合物,如聚醯亞胺、環氧樹脂,雙馬來醯亞胺,三嗪樹脂,陶瓷填料,玻璃纖維等,按功能性要求分目前有感光型和非感光型。可以理解的是,此處可選感光型材料作為介電材料。
如圖2,一種嵌埋結構還包括嵌埋在介電層100的器件200,端子210,器件200正面設置有端子210,端子210表面與第一表面110差值位於設定範圍內,此處為5-30 μm,可選5 μm、10 μm、15 μm、18 μm、20 μm、25 μm、28 μm或30 μm等不同的差值,端子210表面為與第一表面110同方向的一面,非端子面220與第二表面120共面,這樣設置可以進一步降低封裝後的結構厚度,可以理解的是,器件200可以是裸晶片,IC,BGA等有源器件,其中,晶片可以為不同功能的晶片,如CPU晶片,射頻驅動晶片或者其他處理器的晶片,也可以是無源器件,在採用無源器件時,可以為電容、電感和電阻。介電層100環繞並包裹器件200設置,介電層100的第一表面110設置有第一電路層300,第一電路層300與器件200的端子直接電連接,可以理解的是,這種連接方式解決了現有方案需要精准塗布焊料的問題,由於器件200與線路一體電鍍相連,保證了器件200與線路的連接穩定性,確保了良好的電信號。與第一電路層300相對的設置有第二電路層310,第二電路層310設置在與介電層100的第二表面120,並於第二表面120共面,如圖2示,第一電路層300與第二電路層310通過金屬柱400連接。
圖3中示出的一種嵌埋結構的整體結構示意圖是該申請的另一個實施例,其與圖2的主要結構大致相同,區別點主要在於工藝流程的實施先後,這點將在後續製備流程中詳細論述,此處不再贅述。
應當理解的是,在圖2或圖3中,示出了介電層100中嵌埋兩個器件200的具體結構示意圖,但是在本申請實施例中,嵌埋在介電層100中的器件200的個數不僅限於兩個,也可以是一個或者三個或者多個,但是無論在介電層100中埋設幾個器件200,該器件200與其他結構層的連接方式均相同,同樣可以理解的是,在本申請實施例中,該嵌埋結構不局限於一層,根據設計需要,可以是兩層或者多層,但是無論設計幾層,其設計的整體結構是一樣的,從上到下依次為第一電路層300,環繞包裹若干器件200和金屬柱400的介電層100,第二電路層310,需要說明是,本申請製備方法以一層嵌埋結構包裹兩個器件為例進行的示例說明。
為了方便理解本申請實施例提供的一種嵌埋結構,見圖2所示,本申請第一實施例提供了一種嵌埋結構的製備方法,如圖1a,該方法具體包括如下步驟:
準備臨時承載板500;在臨時承載板500上下表面的至少一面製備第二電路層310,覆蓋第二電路層310製備第一介電層130。
具體的,如圖4a、圖4b和圖4c中所示,圖4a中,在承載板防護層540表面層壓光刻膠600,經曝光,顯影得出第二電路層310的開窗圖形,如圖4b,電鍍第二電路層310,去除光刻膠,層壓介電材料形成第一介電層130並進行預固化,如圖4c,圖形影像化處理第一介電層130,露出第二電路層310上表面,並完全熱固化介電材料。
在實際實施的時候,為保證填充效果,介電材料用量一般按照實際需要的填充量計算,此處,介電材料層壓後表面應高於第二電路層310表面5-20 μm,可選5 μm、10 μm、15 μm、18 μm或20 μm等不同的差值,介電材料可選有機或無機介電材料一種或多種的混合物,如聚醯亞胺、環氧樹脂,雙馬來醯亞胺,三嗪樹脂,陶瓷填料,玻璃纖維等,按功能性要求分目前有感光型和非感光型介電材料,需要說明的是,本實施例選擇感光型介電材料製作介電層100,這是因為,使用感光材料時,在經過圖形影像化處理將需要裸露的線路或銅柱部分裸露出來後,不需要經鐳射,鑽孔等減薄工藝加工裸露線路或銅柱表面,使用圖形圖像化處理即可,提升了生產效率,且經層壓整平後無需整體減薄處理,使得介電層100更均勻,在實際實施時,也不會對下方器件構成損害,提高了良品率。使用感光型介電材料壓合時加熱平臺短暫熱固化或光固化即可。若介電材料採用非感光型材料時,線路上表面可採用減薄工藝,如磨板或等離子蝕刻等加工方式對介電材料進行整體減薄直至露出線路上表面,也可以採用鐳射燒結的方式對線路上表面介電材料進行燒結,得出所需線路上表面。
如圖4a中所示,臨時承載板500為對稱結構,中間為有機層510,從中間到兩面依次為有機層510,第一金屬層520,第二金屬層530,防護層540。可以理解的是,有機層510可選PP等有機材料,第一金屬層520可選金屬材料諸如銅,第二金屬層530可選金屬材料如銅,第一金屬層520與第二金屬層530為物理壓合而成,防護層540是電鍍形成的,其材料可以為Cu、Ti、Ni、CuWTi、CuNiCu和CuTiCu等,但不局限於此。臨時承載板500的各層厚度可以調節,該實施例給出的是從有機層510計算,需要說明的是,各層可選18 μm銅層,3 μm銅層,3-10 μm防護層540,防護層540之金屬可以設置為鎳或鈦等。在實際製備中,由於臨時承載板500是對稱結構,製作時在臨時承載板500的對稱面可以各製作一張題述嵌埋結構,製作好後,進行分板可得兩張基板,基板均為網格狀的矩陣陣列,包含若干個單元,每個單元有一個或多個器件200的組合。
圖形影像化處理並固化第一介電層130,形成空腔230,在空腔230內貼裝器件200並熱固化,器件200設置有端子210的一面朝向空腔230的開口側。
具體的,如圖4c和圖4d中所示,圖形影像化處理第一介電層130,得到用於貼裝器件200的空腔230,空腔230的尺寸可以根據器件200的尺寸對應設計,在空腔230底部施加黏附材料240,黏附材料240存在較多可選方式,用作黏附器件200與下方金屬層,其通過點膠或印刷等方式實施塗布。黏附材料240可以是有機或無機材料,一般為錫膏、銀漿、紅膠或綠油等。貼裝器件200,器件200具有端子210,以及相對應的非端子面220,貼裝時,使器件200的非端子面220與黏附材料240黏接固定並熱固化黏附材料240,貼裝可採用高精度的常規SMT流程,貼裝將回流加熱焊接。可以理解的是,黏附材料240還可以不佈置,通過器件200的非端子面220施加DAF(超薄型薄膜粘合劑),貼裝時通過加熱平臺DAF與下方金屬層直接黏附。
製備第二介電層140,器件200嵌埋於第二介電層140內,且第二介電層140表面高於器件200的端子210表面一預設值。
具體的,參見圖4e中所示,層壓介電材料,圖形影像化處理介電材料,露出空腔開窗250以及導通金屬柱圖形410,並熱固化介電材料。
此處,為保證填充效果,介電材料用量按填充量計算,高於器件200上表面一定厚度,可理解的是,第二介電層140高於端子210表面厚度為5-30 μm,可選 5μm、10 μm、15 μm、18 μm、20 μm、25 μm或30 μm等不同的差值。
在第二介電層140表面製備與端子210直接連接的第一電路層300,且貫穿第二介電層140製作金屬柱400,第一電路層300通過金屬柱400與第二電路層310連接。
具體的,參見圖4f、圖4g中所示,如圖4f,在第二介電層140表面具體為端子表面210、導通金屬柱圖形410內表面和第二介電層140的第一表面110製作種子層320。如圖4g,在種子層320上,層壓光刻膠600,圖形影像化處理光刻膠600,露出待鍍第一電路層300圖形及導通金屬柱400圖形,電鍍第一電路層300圖形及導通金屬柱400圖形得到第一電路層300及金屬柱400。
上述步驟可以看出,第一電路層300與器件200的端子面210通過種子層320使用電鍍的方式直接電連接,可以理解的是,這種連接方式解決了現有方案需要精准塗布焊料的問題,由於器件200與線路一體電鍍相連,保證了器件200與線路的連接穩定性,確保了良好的電信號。
種子層320的製作具體為,使用化學鍍銅或者濺射的方式在第二介電層140表面形成一層金屬種子層320,常用的種子層320的金屬是鈦、銅、鈦鎢合金,但不僅限於上述金屬,種子層320厚度一般為0.8-5 μm,可以理解的是,本實施例可選金屬濺射的方式,濺射0.1 μm厚度的鈦,1 μm厚度的銅。
分割臨時承載板500,形成第一階段嵌埋結構體。
在第一階段嵌埋結構體的雙面形成焊料掩膜700,並在焊料掩膜700上進行開口,露出第二電路層310和第一電路層300的表面,對第二電路層310和第一電路層300表面進行金屬化處理。
具體的,參見圖4h、圖4i和圖4j中所示,如圖4h,去除光刻膠600,蝕刻暴漏於第二介電層140表面的種子層320,層壓光刻膠600用以保護線路,整版曝光後分板,見圖4i,分板時,從第一金屬層520與第一金屬層530處分板,分別蝕刻分板面550、第一金屬層530和防護層540後去除光刻膠600。在分板蝕刻防護層540時,因承載板防護層540較薄,本實施例中,防護層540厚度為3-10 μm,防護層540的金屬可以設置為鎳或鈦等,和第一金屬層530所用金屬不同,這樣可以採用不同的蝕刻液,且蝕刻量較小,由此,在蝕刻完防護層540後對線路層的影響相對可以忽略不計。分板完成後,見圖4j中所示,阻焊製作基板上下表面,阻焊製作包括,基板表面處理,阻焊層印刷,熱預固化,曝光,顯影,熱固化處理,之後金屬表面處理基板上下表面,形成金屬表面層330,得到如圖2所示的一種嵌埋結構的基板。
需要說明的是,本申請第一實施例提供的一種嵌埋結構的製備方法步驟流程只是示例了一層嵌埋結構的具體流程,根據需要可以重複上述步驟得到大於一層的嵌埋結構。
本申請另一個實施例的製備方法可以製作出如圖3所示的一種嵌埋結構的基板。其製備方法與本申請第一個實施例的製備流程大體相同,見圖1b,細節方面有一些差異,具體見如下步驟:
準備臨時承載板500,在臨時承載板500上下表面的至少一面製備第二電路層310,覆蓋第二電路層310製備第一介電層130。
具體的,如圖5a、圖5b和圖5c中所示,圖5a中,在承載板防護層540表面層壓光刻膠600,經曝光,顯影得出第二電路層310的開窗圖形,如圖4i,電鍍第二電路層310,去除光刻膠600,層壓介電材料形成第一介電層130並進行預固化,如圖5c,圖形影像化處理第一介電層130,露出第二電路層310上表面,並完全熱固化介電材料。
在實際實施的時候,為保證填充效果,介電材料用量一般按照實際需要的填充量計算,此處,介電材料層壓後表面應高於第二電路層310表面5-20 μm,可選5 μm、10 μm、15 μm、18 μm或20 μm等不同的差值。
圖形影像化處理並固化第一介電層130,露出第二電路層310表面,層壓光刻膠600後進行圖形影像化處理得到金屬柱圖形410,電鍍形成金屬柱400;
去除光刻膠600,形成空腔230,在空腔230內貼裝器件200並熱固化,器件200設置有端子210的一面朝向空腔230的開口側。
具體的,如圖5c、圖5d、圖5e和圖5f中所示,如圖5c示,圖形影像化處理第一介電層130,得到用於貼裝器件200的空腔230,層壓光刻膠600之後進行圖形影像化處理,得到導通金屬柱圖形410,見圖5d,圖5e中,電鍍導通金屬柱400,去除光刻膠600,如圖5f,在器件空腔230底部施加黏附材料240,貼裝器件200,器件200具有端子210,以及相對應的沒有設置端子210的非端子面220,貼裝時,使器件200的非端子面220與黏附材料240黏接固定並熱固化黏附材料240,可以理解的是,黏附材料240還可以不佈置,通過器件200非端子面220施加DAF(超薄型薄膜黏合劑),貼裝時通過加熱平臺DAF(超薄型薄膜粘合劑)與下方金屬層直接黏附。
製備第二介電層140,器件200嵌埋於第二介電層140內,且第二介電層140表面高於端子210表面一預設值;
具體的,參見圖5g中所示,層壓介電材料,圖形影像化處理介電材料,露出空腔開窗250以及金屬柱400上表面,並熱固化介電材料。
此處,為保證填充效果,介電材料用量按填充量計算,高於器件上表面一定厚度,可理解的是,第二介電層高於端子210表面厚度為5-30 μm,可選5 μm、10 μm、15 μm、18 μm、20 μm、25 μm或30 μm等不同的差值。
在第二介電層140表面製備與端子210直接連接的第一電路層300,第一電路層300通過金屬柱400與第二電路層310連接。
具體的,參見圖5h、圖5i中所示,如圖5h,在第二介電層140表面具體為端子210表面、金屬柱400上表面和第二介電層140的表面110製作種子層。如圖5i,在種子層320上,層壓光刻膠600,圖形影像化處理光刻膠600,露出待鍍第一電路層300圖形,電鍍第一電路層300。
上述步驟可以看出,第一電路層300與器件200的端子面210通過種子層320使用電鍍的方式直接電連接,可以理解的是,這種連接方式解決了現有方案需要精准塗布焊料的問題,由於器件200與線路一體電鍍相連,保證了器件200與線路的連接穩定性,確保了良好的電信號。
種子層320的製備與本申請第一實施例中種子層320的製備流程相同,此處不再贅述。
分割臨時承載板500,形成第一階段嵌埋結構體;
在第一階段嵌埋結構體的雙面形成焊料掩膜700,並在焊料掩膜700上進行開口,露出第二電路層310和第一電路層300的表面,對第二電路層310和第一電路層300表面進行金屬化處理。
具體的,參見圖5j、圖5k和圖5l中所示,如圖5j,去除光刻膠600,蝕刻暴漏於第二介電層140表面的種子層320,層壓光刻膠600用以保護線路,整版曝光後分板,見圖5k,分板時,從第一金屬層520與第二金屬層530處分板,分別蝕刻分板面550、第二金屬層530和防護層540後去除光刻膠600。在分板蝕刻防護層540時,因承載板防護層540較薄,本實施例中,防護層540厚度為3-10 μm,防護層540的金屬可以設置為鎳或鈦等,和第二金屬層530所用金屬不同,這樣可以採用不同的蝕刻液,且蝕刻量較小,由此,在蝕刻完防護層540後對線路層的影響相對可以忽略不計。分板完成後,見圖5l中所示,阻焊製作基板上下表面,之後實施金屬表面處理,形成金屬表面層330,得到如圖2所示的一種嵌埋結構的基板。
需要說明的是,根據需要,可以重複上述一些中間步驟製備若干層的多層嵌埋結構基板,通過上述流程可以得出,本申請提供的一種嵌埋結構,可以在一次實施製備流程中完成器件嵌埋結構的基板製作,解決了現有技術需要分兩部分完成器件嵌埋的問題,由此得到本申請相比現有技術減少了工藝步驟,降低了製造難度,提高了產品品質且降低了製造成本。
由於本申請採用器件嵌埋特徵,使得製作過程中能夠便於通過外觀監控檢查器件與電路之間的連接品質。
通過端子面朝上佈置,器件200背面經整體塗布的黏性材料或DAF(超薄型薄膜粘合劑)與承載板的承載金屬相連,很好解決了端子朝下時線路與器件間填充不良的隱患。
通過端子面朝上佈置,使器件200與下方承載板通過黏性材料相連,器件200與第二電路層310處於同一基準面,進一步降低了封裝體的整體厚度。
以上結合附圖對本申請的較佳實施進行了具體說明,但本申請並不局限於上述實施方式,熟悉本領域的技術人員在不違背本申請精神的前提下還可作出種種的等同變形或替換,這些等同的變形或替換均包含在本申請權利要求所限定的範圍內。
100:介電層
110:第一表面
120:第二表面
130:第一介電層
140:第二介電層
200:器件
210:端子
220:非端子面
230:空腔
240:黏附材料
250:空腔開窗
300:第一電路層
310:第二電路層
320:種子層
330:金屬表面層
400:金屬柱
410:金屬柱圖形
500:臨時承載板
510:有機層
520:第一金屬層
530:第二金屬層
540:防護層
550:分板面
600:光刻膠
700:焊料掩膜
本申請的上述和/或附加的方面和優點從結合下面附圖對實施例的描述中將變得明顯和容易理解,其中:
[圖1a]為本申請一個實施例的製備方法的步驟流程圖。
[圖1b]為本申請另一個實施例的製備方法的步驟流程圖。
[圖2]為本申請一個實施例的整體結構截面示意圖。
[圖3]為本申請另一個實施例的整體結構截面示意圖。
[圖4a]至[圖4j]是本申請一個實施例的製備流程中間狀態的截面圖。
[圖5a]至[圖5l]是本申請另一個實施例的製備流程中間狀態的截面圖。
Claims (11)
- 一種嵌埋結構的製備方法,其中,包括以下步驟: 準備臨時承載板;在所述臨時承載板上下表面的至少一面製備第二電路層,覆蓋所述第二電路層製備第一介電層; 圖形影像化處理並固化所述第一介電層,形成空腔,在所述空腔內貼裝器件並熱固化,所述器件設置有端子的一面朝向所述空腔的開口側; 製備第二介電層,所述器件嵌埋於所述第二介電層內,且所述第二介電層表面高於所述端子表面一預設值; 在所述第二介電層表面製備與所述端子連接的第一電路層,且貫穿所述第二介電層製作金屬柱,所述第一電路層通過所述金屬柱與所述第二電路層連接; 分割所述臨時承載板,形成第一階段嵌埋結構體; 在所述第一階段嵌埋結構體的雙面形成焊料掩膜,並在所述焊料掩膜上進行開口,露出所述第二電路層和所述第一電路層的表面,對所述第二電路層和所述第一電路層表面進行金屬化處理。
- 如請求項1所述的一種嵌埋結構的製備方法,其中,在所述臨時承載板上下表面的至少一面製備第二電路層的具體方法為: 在所述臨時承載板上下表面的至少一面層壓光刻膠; 對所述光刻膠進行曝光,顯影得出所述第二電路層的開窗圖形; 電鍍所述開窗圖形,去除光刻膠,形成所述第二電路層。
- 如請求項1所述的嵌埋結構的製備方法,其中,在所述第二介電層表面製備與所述端子直接連接的第一電路層,且貫穿所述第二介電層製作金屬柱的具體方法為: 通過化學鍍銅或者濺射的方式在所述第二介電層表面形成一層金屬種子層; 層壓光刻膠,圖形影像化處理所述光刻膠,露出所述第一電路層圖形及所述金屬柱圖形; 電鍍所述第一電路層圖形及所述金屬柱圖形形成所述第一電路層及金屬柱; 其中,所述第一電路層通過種子層直接與所述端子電連接。
- 如請求項1所述的嵌埋結構的製備方法,其中,所述預設值取值範圍為5~30 μm。
- 如請求項1所述的嵌埋結構的製備方法,其中,所述臨時承載板為4層對稱結構,從中間到兩面依次為有機層,第一金屬層,第二金屬層,防護層。
- 如請求項1所述的嵌埋結構的製備方法,其中,在所述空腔內貼裝器件並熱固化的具體方法為: 通過在所述器件非端子面施加超薄型薄膜粘合劑,加熱使所述器件與所述空腔下面的臨時承載板直接黏附; 或者通過在所述空腔底部施加黏附材料,使所述器件與所述黏附材料黏接固定。
- 如請求項1所述的嵌埋結構的製備方法,其中,所述第一介電層與所述第二介電層的介電材料為感光型介電材料或非感光型介電材料。
- 一種嵌埋結構的製備方法,其中,包括以下步驟: 準備臨時承載板,在所述臨時承載板上下表面的至少一面製備第二電路層,覆蓋所述第二電路層製備第一介電層; 圖形影像化處理並固化所述第一介電層,露出所述第二電路層表面,層壓光刻膠後進行圖形影像化處理得到金屬柱圖形,電鍍形成金屬柱; 去除光刻膠,形成空腔,在所述空腔內貼裝器件並熱固化,所述器件設置有端子的一面朝向所述空腔的開口側; 製備第二介電層,所述器件嵌埋於所述第二介電層內,且所述第二介電層表面高於所述端子表面一預設值; 在所述第二介電層表面製備與所述端子直接連接的第一電路層,所述第一電路層通過所述金屬柱與所述第二電路層連接; 分割所述臨時承載板,形成第一階段嵌埋結構體; 在所述第一階段嵌埋結構體的雙面形成焊料掩膜,並在所述焊料掩膜上進行開口,露出所述第二電路層和所述第一電路層的表面,對所述第二電路層和所述第一電路層表面進行金屬化處理。
- 一種嵌埋結構,其中,包括: 介電層,所述介電層包括相對設置的第一表面及第二表面; 嵌埋在所述介電層的器件和端子,所述器件設置有所述端子的一面與所述第一表面差值為一預設值,所述器件非端子面與所述第二表面共面; 第一電路層,設置在所述介電層的第一表面,所述第一電路層與所述端子直接電連接; 第二電路層,設置在與所述介電層的第二表面共面; 金屬柱,用於連接所述第一電路層與所述第二電路層。
- 如請求項10所述的一種嵌埋結構,其中,所述預設值取值範圍為5~30 μm。
- 一種基板,其中,包括至少一層如請求項10或11中任意一項所述的一種嵌埋結構。
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