TWI483363B - 晶片封裝基板、晶片封裝結構及其製作方法 - Google Patents

晶片封裝基板、晶片封裝結構及其製作方法 Download PDF

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Publication number
TWI483363B
TWI483363B TW101127523A TW101127523A TWI483363B TW I483363 B TWI483363 B TW I483363B TW 101127523 A TW101127523 A TW 101127523A TW 101127523 A TW101127523 A TW 101127523A TW I483363 B TWI483363 B TW I483363B
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Taiwan
Prior art keywords
chip package
electrical connection
layer
wafer
connection pads
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TW101127523A
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English (en)
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TW201405745A (zh
Inventor
E Tung Chou
Chih Jen Hsiao
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Zhen Ding Technology Co Ltd
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Publication of TW201405745A publication Critical patent/TW201405745A/zh
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Publication of TWI483363B publication Critical patent/TWI483363B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/181—Encapsulation

Description

晶片封裝基板、晶片封裝結構及其製作方法
本發明涉及電路板製作技術，尤其涉及一種晶片封裝基板、具有該晶片封裝基板的晶片封裝結構以及該晶片封裝結構的製作方法。
晶片封裝基板可為晶片提供電連接、保護、支撐、散熱、組裝等功效，以實現多引腳化，縮小封裝產品體積、改善電性能及散熱性、超高密度或多晶片模組化的目的。
當電子產品的體積日趨縮小，所採用的晶片封裝基板的體積和線路間距也必須隨之減小。然而，在目前習知的基板結構和工藝技術能力下，受限於銅箔的厚度，要使基板再薄化和線路間距再縮小的可能性很小，不利於應用在小型尺寸的電子產品上。因此，如何開發出新穎的薄型整合性基板，不但工藝快速簡單又適合量產，以符合電子產品對於尺寸、外型輕薄化的需求，實為相關業者努力的一大重要目標。
有鑒於此，有必要提供一種晶片封裝基板、晶片封裝結構及其製造方法及，以降低晶片封裝基板的整體厚度並降低製造成本，以符合市場產品輕薄化和低成本的需求。
一種晶片封裝基板，包括柔性絕緣層、導電線路圖形、防焊層、連續銅層及加強板。該柔性絕緣層包括相對的第一表面及第二表面，該柔性絕緣層具有複數貫通該第一表面及第二表面的通孔。該導電線路圖形形成於該柔性絕緣層的第一表面上，並覆蓋該複數通孔，從該複數通孔露出的導電線路圖形構成複數第一電性連接墊。該防焊層覆蓋部分該導電線路圖形的以及從該導電線路圖形露出的該柔性絕緣層的第一表面，該導電線路圖形從該防焊層露出的部分構成複數第二電性連接墊，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接。該連續銅層沈積於該柔性絕緣層的第二表面、該複數通孔的內壁及該複數通孔內的第一電性連接墊的表面。該加強板，其貼合於該第二表面的連續銅層表面，且該加強板覆蓋該複數通孔。
一種晶片封裝結構的製作方法，包括步驟：提供如上所述的晶片封裝基板；將一個晶片封裝於該晶片封裝基板上，使得該晶片與該晶片封裝基板的複數第二電性連接墊電性連接；去除該加強板和該連續銅層；及形成與該複數第一電性連接墊一一電性連接的複數第一焊料凸塊，每個第一焊料凸塊均凸出於該第二表面。
一種晶片封裝結構，包括柔性絕緣層、導電線路圖形、防焊層、晶片及複數第一焊料凸塊。該柔性絕緣層包括相對的第一表面及第二表面，該柔性絕緣層具有複數貫通該第一表面及第二表面的通孔。該導電線路圖形形成於該柔性絕緣層的第一表面上，並覆蓋該複數通孔，從該複數通孔露出的導電線路圖形構成複數第一電性連接墊。該防焊層覆蓋部分該導電線路圖形以及從該導電線路圖形露出的該柔性絕緣層的第一表面，該導電線路圖形從該防 焊層露出的部分構成複數第二電連接墊，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接。該晶片與該複數第二電性連接墊電性連接，該晶片固定於該防焊層上。該複數第一焊料凸塊與該複數第一電性連接墊一一電性連接，該複數第一焊料凸塊分別從該複數第一通孔內向第二表面延伸並凸出於該第二表面。
本技術方案的晶片封裝基板、晶片封裝結構及其製作方法所使用的絕緣材料為柔性材料，其可以做的較薄，並且，本技術方案的晶片封裝基板為單層，整體厚度較薄，製作方法簡單，可降低製造成本，符合市場產品輕薄化和低成本的需求。
10‧‧‧柔性單面線路板
11‧‧‧柔性絕緣層
12‧‧‧導電線路圖形
111‧‧‧第一表面
112‧‧‧第二表面
13‧‧‧通孔
121‧‧‧第一電性連接墊
10a‧‧‧柔性單面覆銅基板
14‧‧‧銅箔層
113‧‧‧第一乾膜
114‧‧‧第二乾膜
15‧‧‧防焊層
16‧‧‧第二電性連接墊
18‧‧‧銅層
161‧‧‧表面處理層
115‧‧‧加強板
20‧‧‧晶片封裝基板
30‧‧‧晶片
32‧‧‧鍵合導線
31‧‧‧黏膠層
40‧‧‧封裝膠體
41‧‧‧封裝體
46‧‧‧第一焊料凸塊
50‧‧‧晶片封裝結構
60‧‧‧晶片封裝結構
30a‧‧‧晶片
32a‧‧‧接觸凸塊
161a‧‧‧第二焊料凸塊
40a‧‧‧底部填充劑
圖1是本發明第一實施例提供的柔性單面覆銅基板的剖面示意圖。
圖2是圖1中的柔性單面覆銅基板上形成複數通孔後的剖面示意圖。
圖3是圖2的銅箔層及柔性絕緣層上覆蓋乾膜後的剖面示意圖。
圖4是圖2中的銅箔層形成導電線路圖形後所形成的柔性單面線路板的剖面示意圖。
圖5是在圖4的柔性單面線路板上形成防焊層的剖面示意圖。
圖6是在圖5的柔性單面線路板的柔性絕緣層上形成銅層後的剖面示意圖。
圖7是將圖6的柔性單面線路板銅層上壓合加強板後的剖面示意圖 。
圖8是在圖7的柔性單面線路板上形成表面處理層後形成的晶片封裝基板的剖面示意圖。
圖9是在圖8的晶片封裝基板上固定一晶片後的剖面示意圖。
圖10是在圖8中的晶片封裝基板和晶片上形成封裝膠體後形成的封裝體的剖面示意圖。
圖11是將圖10的封裝體去除加強板後的剖面示意圖。
圖12是將圖11的封裝體去除銅層後的剖面示意圖。
圖13是在圖12的封裝體上形成第一焊料凸塊後形成的晶片封裝結構的剖面示意圖。
圖14是本發明第二實施例提供的晶片封裝結構的剖面示意圖。
下面將結合附圖及實施例對本技術方案提供的晶片封裝基板和晶片封裝結構及其製作方法作進一步的詳細說明。
請參閱圖1至圖13，本技術方案第一實施例提供的晶片封裝基板的製作方法包括以下步驟：
步驟1：請參閱圖1至圖4，提供柔性單面線路板10，該柔性單面線路板10包括相互疊合的柔性絕緣層11及導電線路圖形12。該柔性絕緣層11包括相對的第一表面111及第二表面112，該柔性絕緣層11上形成有複數貫通該第一表面111及第二表面112的通孔13，該導電線路圖形12覆蓋於該柔性絕緣層11的第一表面111上，且該導電線路圖形12覆蓋該通孔13。該複數通孔13分別用於填充預 焊料，以形成焊料凸塊。
該柔性單面線路板10可以採用下述方法形成：
第一，請參閱圖1，提供柔性單面覆銅基板10a，該柔性單面覆銅基板10a包括一個柔性絕緣層11及一銅箔層14。該柔性絕緣層11包括相對的所述第一表面111及第二表面112，該銅箔層14覆蓋於該柔性絕緣層11的第一表面111上。該柔性單面覆銅基板10a可以通過裁切卷帶式單面覆銅基板而形成。
該柔性絕緣層11的材質為柔性線路板常用的柔性材料，如聚醯亞胺(Polyimide,PI)、聚乙烯對苯二甲酸乙二醇酯(Polyethylene Terephthalate,PET)或聚萘二甲酸乙二醇酯(Polyethylene Naphthalate，PEN)等，優選為耐熱性較好的聚醯亞胺。該柔性絕緣層11的厚度範圍可以為15μm-250μm，優選為25μm-50μm，以同時滿足較好的機械強度及較薄的產品厚度的要求。該銅箔層14優選為壓延銅箔，也可以為電解銅箔。該銅箔層14的厚度優選為12μm-35μm。當然，該柔性絕緣層11及該銅箔層14的厚度還可以為其他厚度值。
第二，請一併參閱圖2，在該柔性絕緣層11中形成所述複數通孔13。該通孔13貫通該柔性絕緣層11的第一表面111及第二表面112，而不貫通該銅箔層14，從而使該複數通孔13對應處的銅箔層14從該柔性絕緣層11的第二表面112一側裸露出來。該複數通孔13可以通過鐳射鑽孔工藝或者定深機械鑽孔工藝形成。每個通孔13的橫截面的形狀為圓形，當然也可以根據需要設計為其他形狀。
第三，請一併參閱圖3-4，將該銅箔層14製作形成該導電線路圖 形12。該導電線路圖形12覆蓋每個通孔13，且導電線路圖形12暴露在複數通孔13的部分構成複數第一電性連接墊121。本實施例中，可以採用影像轉移工藝及蝕刻工藝將該銅箔層14製作形成導電線路圖形12。以下以採用乾膜進行影像轉移製作導電線路圖形12為例說明，製作形成導電線路圖形12的步驟可包括：首先，對該銅箔層14及該柔性絕緣層11的表面進行表面微蝕處理，以去除該銅箔層14及該柔性絕緣層11表面的污漬、油脂等，並使該銅箔層14的表面輕微腐蝕以具有一定的粗糙度，以有利於提高該銅箔層14與後續步驟中的乾膜之間的結合力，防止銅箔層14與乾膜之間有氣泡、雜質的出現，進一步提高下一步中乾膜顯影的解析度。當然，也可以採用其他表面處理方式如等離子體處理等對該銅箔層14及該柔性絕緣層11進行表面處理。
其次，請參閱圖3，在該銅箔層14上壓合一第一乾膜113，及在該柔性絕緣層11的第二表面112上壓合一第二乾膜114。
在該柔性絕緣層11的第二表面112上覆蓋第二乾膜114，是為了防止後續步驟中的蝕刻藥水進入該通孔13內腐蝕裸露的銅箔層14。當然，第二乾膜114也可以替換為低黏性的覆蓋膜、膠帶等遮擋物；另外，第二乾膜114也可僅覆蓋該通孔13的開口及周圍的部分第二表面112上，而無需覆蓋整個第二表面112，只要可以阻擋藥水進入通孔13即可。
第四，請參閱圖4，通過曝光、顯影、蝕刻以及剝膜工藝將該銅箔層14製作形成導電線路圖形12，形成柔性單面線路板10。
本實施例對該銅箔層14上的第一乾膜113進行選擇性曝光，對該 第二表面112上的第二乾膜114進行整面曝光。該銅箔層14上的第一乾膜113經過曝光顯影後形成圖案化的乾膜層，使得銅箔層14需要蝕刻去除的部分露出第一乾膜113，而銅箔層14需要形成線路的部分仍被第一乾膜113覆蓋。利用銅蝕刻液進行蝕刻，以去除露出第一乾膜113的銅箔層14，從而使得銅箔層14被圖案化的乾膜覆蓋的部分形成導電線路圖形12。每個通孔13均被導電線路圖形12覆蓋。
當然，也可以通過濕膜工藝將該銅箔層14製作形成導電線路圖形12。另外，將該銅箔層14製作形成導電線路圖形12之後，還可以包括沖孔工藝，以形成複數工具孔(圖未示)，該工具孔貫通柔性絕緣層11及導電線路圖形12。該工具孔用於後續步驟中對線路板進行定位。
步驟2：請參閱圖5，在該導電線路圖形12的表面部分區域以及從該導電線路圖形12露出的柔性絕緣層11的第一表面111形成防焊層15，使該導電線路圖形12上未被覆蓋防焊層15的部位構成複數第二電性連接墊16。每個第二電性連接墊16與一個第一電性連接墊121對應且通過導電線路圖形12中的線路連接。或者說，該複數第二電性連接墊16分別由該複數通孔13露出的第一電性連接墊121延伸形成。該複數第一電性連接墊121與該複數第二電性連接墊16一一對應連接。
本實施例中，使用液態感光防焊油墨製作防焊層，其步驟為：在該導電線路圖形12表面以及導電線路圖形12的間隙印刷液態感光防焊油墨；預烘烤使該液態感光防焊油墨表面預固化；通過選擇性UV曝光使該液態感光防焊油墨部分區域發生交聯反應；通過顯 影流程將該液態感光防焊油墨的未發生交聯反應的區域去除，以露出複數第二電性連接墊16；最後，加熱固化該液態感光防焊油墨，從而在該導電線路圖形12的部分區域以及導電線路圖形12的間隙形成防焊層15，該導電線路圖形12未覆蓋防焊層15的部位為防焊層開口區。
該液態感光防焊油墨優選為柔性電路板專用的具有耐撓折性能的液態感光防焊油墨，以防該防焊層15在後續的製作流程中以及使用中發生斷裂。當然，也可以使用具有耐撓折性能的熱固性油墨形成該防焊層15，此時不需要曝光顯影，只需要使用有圖案的網版在該導電線路圖形12的部分區域以及導電線路圖形12的間隙印刷該熱固性油墨，在需要防焊層15開口的部位通過網版遮蔽使熱固性油墨不能印刷到該第二電性連接墊16即可，之後加熱固化該熱固性油墨即可形成該防焊層15。
可以理解，步驟1和步驟2的過程可為卷對卷(roll to roll,RTR)制程，該卷對卷制程可採用如下方法進行：
(一)提供一卷帶式柔性單面覆銅基板，該卷帶式柔性單面覆銅基板包括複數沿其長度方向依次連接的單面覆銅基板單元，每個單面覆銅基板單元均包括柔性絕緣層11以及銅箔層14，該柔性絕緣層11包括相對的所述第一表面111及所述第二表面112，該銅箔層14層覆蓋於該柔性絕緣層11的第一表面111。
(二)以卷對卷方式在每個單面覆銅基板單元的該柔性絕緣層11上加工形成該複數通孔13，該複數通孔13貫通該柔性絕緣層11的第一表面111及第二表面112；
(三)以卷對卷方式將每個單面覆銅基板單元的該銅箔層14製作形成導電線路圖形12，從而將該卷帶式柔性單面覆銅基板製成卷帶式柔性單面線路板，該卷帶式柔性單面線路板包括由該複數單面覆銅基板單元製成的複數柔性單面線路板10，其中，每個通孔13均被所述導電線路圖形12所覆蓋，由複數通孔13從該柔性絕緣層11側裸露出來的該部分導電線路圖形12構成所述複數第一電性連接墊121。
(四)在該卷帶式柔性單面線路板上形成防焊層15，以使防焊層15覆蓋每個柔性單面線路板10的部分導電線路圖形12表面以及從導電線路圖形12露出的所述第一表面111，從該防焊層15露出的導電線路圖形12構成複數第二電性連接墊16，該複數第二電性連接墊16與該複數第一電性連接墊121一一對應連接。
(五)沿每個柔性單面線路板10的邊界切割卷帶式柔性單面線路板，從而獲得複數分離的具有防焊層15的柔性單面線路板10。
上述卷對卷制程的形成通孔13、製作導電線路圖形12以及形成防焊層15的方法與步驟1和步驟2中對應的方法相同。
步驟3：請參閱圖6至8，在該第二表面112、通孔13的內壁以及第一電性連接墊121表面形成一層連續的銅層18，在該柔性絕緣層11的第二表面112一側貼合加強板115，以及在該複數第二電性連接墊16上形成表面處理層161，從而形成晶片封裝基板20。
本步驟中形成銅層18、貼合加強板115以及在第二電性連接墊16上形成表面處理層161的步驟如下：
第一，請參閱圖6，在該柔性絕緣層11的第二表面112、該通孔13 的內壁上以及該第一電性連接墊121上通過濺鍍形成一層連續的銅層18。該銅層18位於該第一電性連接墊121上的部分與該第一電性連接墊121緊密結合，從而使該銅層18與該導電線路圖形12相導通。該銅層18與該導電線路圖形12相導通的作用為在後續步驟中進行電鍍金時形成通路。當然，該銅層18也可以通過化學鍍銅等方式形成。優選地，該銅層18小於或等於25微米。
第二，請參閱圖7，在該第二表面112的銅層18上貼合加強板115，該加強板115覆蓋銅層18及通孔13。加強板115可通過膠片黏接於該銅層18上。該加強板115的其中一作用為保護該銅層18，以防止在該銅層18被鍍金藥水侵蝕、污染以及防止該銅層18上鍍上金，另一作用為支撐該柔性單面線路板10。該加強板115的材質可以為增強材料的環氧樹脂板、酚醛樹脂板或金屬板等，當然不限於上述材料，一般具有支撐作用的材料均可用於所述加強板115。
第三，請參閱圖8，在該複數第二電性連接墊16上分別形成表面處理層161，以保護該第二電性連接墊16以防止其氧化。
本實施例中，形成該複數表面處理層161的方式為電鍍金。該複數表面處理層161分別與對應的第二電性連接墊16電導通。可以理解，形成該表面處理層161的方法也可以取代為鍍鎳金、化鎳浸金、鍍鎳鈀金、鍍錫等，並不以本實施例為限，當然，該表面處理層161也可以省略。
至此，晶片封裝基板20製作完成。該晶片封裝基板20包括該柔性絕緣層11、形成柔性絕緣層11的第一表面111的導電線路圖形12及防焊層15。該柔性絕緣層11的第二表面112形成有複數通孔13 ，導電線路圖形12覆蓋該複數通孔13，該導電線路圖形12從該複數通孔13的第二表面112一側露出的部分構成複數第一電性連接墊121。該柔性絕緣層11的第二表面112、該通孔13的內壁以及該第一電性連接墊121上形成有一層連續的銅層18。該第二表面112的銅層18上貼附有加強板115，且該加強板115覆蓋銅層18及通孔13，該加強板115的材質可以為增強材料的環氧樹脂板、酚醛樹脂板或金屬板等。該防焊層15覆蓋該導電線路圖形12的表面部分區域以及從該導電線路圖形12露出的柔性絕緣層11的第一表面111，該導電線路圖形12上未被覆蓋防焊層15的部位構成複數第二電性連接墊16，該複數第二電性連接墊16與該複數第一電性連接墊121一一對應連接，每個第二電性連接墊16的表面形成表面處理層161，該表面處理層161的材料可以為鎳金、鎳鈀金、錫等。
該晶片封裝基板20可進一步通過後續步驟將晶片30封裝於其上，也可以被包裝後運送至晶片封裝工廠進行後續的晶片封裝。具體的晶片封裝步驟如步驟4-7所述。
步驟4：請參閱圖9，提供一導線接合(wire bonding,WB)晶片30，並將晶片30與第二電性連接墊16電性連接。具體的，晶片30具有複數鍵合接點以及自複數鍵合接點延伸的多條鍵合導線32，鍵合導線32與第二電性連接墊16一一對應。多條鍵合導線32的一端電性連接該晶片30，另一端分別電性連接該複數第二電性連接墊16表面的表面處理層161，從而使晶片30與導電線路圖形12電連接。
優選的，該晶片30通過一黏膠層31固定於該防焊層15表面，該鍵 合導線32可通過焊接的方式連接於對應的表面處理層161。該鍵合導線32的材料一般為金。
步驟5：請參閱圖10，採用封裝膠體40將鍵合導線32、晶片30及晶片封裝基板20外露的防焊層15和表面處理層161進行包覆封裝，形成一封裝體41。該鍵合導線32、晶片30均完全包覆於該封裝膠體40內。本實施例中，該封裝膠體40為黑膠，當然，該封裝膠體40也可以其他封裝膠體材料，並不以本實施例為限。
步驟6：請參閱圖11及圖12，去除該加強板115和該銅層18。
通過剝除的方式將該銅層18上的加強板115去除，之後再通過蝕刻的方式去除該銅層18，從而使所述柔性絕緣層11的第二表面112及第一電性連接墊121露出。通過蝕刻液去除該銅層18時，封裝體41在蝕刻液中不能停留太長時間，以防止所述第一電性連接墊121被侵蝕。
步驟7：請參閱圖13，在每個通孔13內填充焊料，並使焊料固化形成第一焊料凸塊46，每個第一焊料凸塊46均突出於該第二表面112，每個通孔13表面的第一焊料凸塊46與該通孔13對應的第一電性連接墊121電連接，從而，形成一晶片封裝結構50。
本實施例中，每個第一焊料凸塊46凸出於該第二表面112部分的形狀為球狀，即該第一焊料凸塊46為焊球狀，可以理解該第一焊料凸塊46的形狀不限，還可以橢球狀、柱體狀等。該第一焊料凸塊46的材料一般主要包括錫，其可通過電鍍或印刷的方式形成。該第一焊料凸塊46用於與另一晶片封裝基板(圖未示)上的焊墊電連接並封裝在一起，或者與印刷電路板(圖未示)上焊墊電連 接並封裝在一起。
由於該第二電性連接墊16與第一電性連接墊121通過導電線路圖形12電性連接，所以當該晶片封裝結構50封裝於另一封裝基板或印刷電路板上時，該晶片30可依次通過該鍵合導線32、表面處理層161、第二電性連接墊16、第一電性連接墊121及第一焊料凸塊46，最終電連接於另一封裝基板或印刷電路板。
經過本實施例的製作方法製作而成的晶片封裝結構50包括柔性絕緣層11、形成柔性絕緣層11的第一表面111的導電線路圖形12、防焊層15、晶片30、封裝膠體40及複數第一焊料凸塊46。該柔性絕緣層11的第二表面112形成有複數通孔13，導電線路圖形12覆蓋該複數通孔13，該導電線路圖形12從該複數通孔13的第二表面112一側露出的部分構成複數第一電性連接墊121。該複數第一焊料凸塊46分別填充於該複數通孔13，該複數第一焊料凸塊46分別與對應的第一電性連接墊121電連接並凸出於該第二表面112。本實施例中，該複數第一焊料凸塊46凸出於第二表面112的部分呈球形，該複數第一焊料凸塊46凸出於第二表面112的部分的形狀還可以為橢球狀、柱體狀等，並不以本實施例為限。該防焊層15覆蓋該導電線路圖形12的表面部分區域以及從該導電線路圖形12露出的柔性絕緣層11的第一表面111，該導電線路圖形12上未被覆蓋防焊層15的部位構成複數第二電性連接墊16，該複數第二電性連接墊16與該複數第一電性連接墊121通過導電線路圖形12一一對應連接，每個第二電性連接墊16的表面形成有表面處理層161。該晶片30通過一黏膠層31固定於該防焊層15上。該晶片30具有複數鍵合接點以及自複數鍵合接點延伸的多條鍵合導線32， 該多條鍵合導線32與複數第二電性連接墊16一一對應連接。封裝膠體40包覆該鍵合導線32、晶片30及晶片封裝基板20的外露的防焊層15和表面處理層161。本實施例中，該封裝膠體40為黑膠。
本技術方案的晶片封裝基板20及晶片封裝結構50所使用的絕緣材料為聚醯亞胺等柔性材料，其可以做的較薄；另外，本技術方案的晶片封裝基板20的導電線路圖形12為單層，整體厚度較薄，製作方法較簡單，可降低製造成本，符合市場產品輕薄化和低成本的需求。
請參閱圖14，本發明第二實施例提供一種晶片封裝結構60及其製作方法。該晶片封裝結構60與第一實施例的晶片封裝結構50結構相似，不同之處在於，晶片封裝結構60中的晶片30a為覆晶封裝(flip-chip)晶片，晶片30a的封裝方式為覆晶封裝。也就是說，該晶片封裝結構60包括晶片30a、柔性絕緣層11、導電線路圖形12、防焊層15及複數第一焊料凸塊46。本實施例中的柔性絕緣層11、導電線路圖形12、防焊層15及複數第一焊料凸塊46的結構位置關係與第一實施例中的柔性絕緣層11、導電線路圖形12、防焊層15及複數第一焊料凸塊46相同。其不同之處在於，晶片30a具有與該複數第二電性連接墊16一一對應的接觸凸塊32a，該複數第二電性連接墊16表面的表面處理層161表面均形成有第二焊料凸塊161a。該晶片30a的複數接觸凸塊32a分別與該複數第二電性連接墊16表面的第二焊料凸塊161a相接觸並電連接。該接觸凸塊32a也可以由焊料製成。該晶片30a與該防焊層15之間填充有底部填充劑40a，以使晶片30a與導電線路圖形12及防焊層15牢固結合，增強晶片封裝結構60的信賴度。本實施例中，省去了第一實 施例的封裝膠體40。
該晶片封裝結構60的製作方法與第一實施例的製作方法不同之處在於步驟4和步驟5，其他步驟1-3、6-7對應相同，本實施例中採用步驟4’和步驟5’取代第一實施例製作方法的步驟4和步驟5，具體如下所述：
步驟4’：提供所述覆晶封裝晶片30a，晶片30a具有分別與該複數第二電性連接墊16對應的複數接觸凸塊32a，在該複數第二電性連接墊16的表面處理層161的表面分別形成第二焊料凸塊161a，並使該複數接觸凸塊32a分別與對應的第二焊料凸塊161a相連接並電導通。
本實施例中，可通過電鍍或印刷的方式將複數第二焊料凸塊161a分別形成於對應的表面處理層161的表面，且該複數第二焊料凸塊161a凸出於該防焊層15的表面。該第二焊料凸塊161a可以為柱狀、球狀等，本實施例中為柱狀，其材料一般主要為錫。該接觸凸塊32a的形狀一般為球狀，其一般也由焊料製成，其材料主要為錫。該複數接觸凸塊32a與對應的第二焊料凸塊161a的連接可採用如下方法：首先，將覆晶封裝晶片30a放置於設置了複數第二焊料凸塊161a的晶片封裝基板20上，並使該複數接觸凸塊32a分別與對應的第二焊料凸塊161a相接觸；然後，將該晶片30a和設置了複數第二焊料凸塊161a的晶片封裝基板20一起經過回焊爐，使接觸凸塊32a和第二焊料凸塊161a熔融結合後冷卻固化，從而使接觸凸塊32a和第二焊料凸塊161a相互連接並電導通。
步驟5’：將底部填充劑40a填充於該晶片30a與晶片封裝基板20之間的縫隙內，從而將該晶片30a與晶片封裝基板20封裝固定。 將步驟5’制得的封裝體再經過與第一實施例的步驟6和步驟7類似的方法去除加強板115和銅層18及形成第一焊料凸塊46，獲得晶片封裝結構60。底部填充劑40a黏結晶片30a的表面以及防焊層15的表面，並包圍接觸凸塊32a及第二焊料凸塊161a。
該底部填充劑40a的填充是通過毛細作用，將液態的底部填充劑40a的材料從晶片30a的邊緣滲透至該晶片30a與晶片封裝基板20之間的內部區域。該底部填充劑40a一般採用環氧樹脂，如底部填充劑材料Loctite 3536。
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，於爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。
11‧‧‧柔性絕緣層
12‧‧‧導電線路圖形
111‧‧‧第一表面
112‧‧‧第二表面
13‧‧‧通孔
121‧‧‧第一電性連接墊
15‧‧‧防焊層
16‧‧‧第二電性連接墊
161‧‧‧表面處理層
30‧‧‧晶片
32‧‧‧鍵合導線
31‧‧‧黏膠層
40‧‧‧封裝膠體
46‧‧‧第一焊料凸塊
50‧‧‧晶片封裝結構

Claims (15)

  1. 一種晶片封裝基板，包括：柔性絕緣層，其包括相對的第一表面及第二表面，該柔性絕緣層具有複數貫通該第一表面及第二表面的通孔；導電線路圖形，形成於該柔性絕緣層的第一表面上，並覆蓋該複數通孔，從該複數通孔露出的導電線路圖形構成複數第一電性連接墊；防焊層，覆蓋部分該導電線路圖形以及從該導電線路圖形露出的該柔性絕緣層的第一表面，該導電線路圖形從該防焊層露出的部分構成複數第二電性連接墊，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接，該第一電性連接墊用於設置焊料凸塊以焊接另一晶片封裝基板或電路板，該第二電性連接墊用於通過鍵合導線電連接一晶片或通過焊接電連接一晶片；連續銅層，沈積於該柔性絕緣層的第二表面、該複數通孔的內壁及該複數通孔內的第一電性連接墊的表面；及可被移除的加強板，其貼合於該第二表面的連續銅層表面，且該加強板覆蓋該複數通孔。
  2. 如請求項1所述的晶片封裝基板，其中，每個第二電性連接墊的表面均沈積有表面處理層。
  3. 如請求項2所述的晶片封裝基板，其中，該表面處理層的材料包括金或錫。
  4. 如請求項1所述的晶片封裝基板，其中，該加強板的材料為環氧樹脂板、酚醛樹脂板或金屬板。
  5. 如請求項1所述的晶片封裝基板，其中，該連續銅層的厚度小於或等於25 微米。
  6. 一種晶片封裝結構的製作方法，包括步驟：形成該晶片封裝基板，形成該晶片封裝基板包括：提供一柔性單面覆銅基板，該柔性單面覆銅基板包括該柔性絕緣層以及銅箔層，該柔性絕緣層包括相對的該第一表面及該第二表面，該銅箔層覆蓋於該柔性絕緣層的第一表面；在該柔性絕緣層上形成該複數通孔，該複數通孔貫通該柔性絕緣層的第一表面及第二表面；通過將該銅箔層製作形成導電線路圖形，從而將該柔性單面覆銅基板製成柔性單面線路板，其中，每個通孔均被該導電線路圖形所覆蓋，由複數通孔從該柔性絕緣層側裸露出來的該部分導電線路圖形構成該複數第一電性連接墊；及在該柔性單面線路板的部分導電線路圖形表面以及從導電線路圖形露出的該第一表面形成該防焊層，使從該防焊層露出的導電線路圖形構成複數第二電性連接墊，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接；在該第二表面、該通孔的內壁以及第一電性連接墊表面形成一層連續的銅層，在該柔性絕緣層的第二表面一側貼合加強板從而形成該晶片封裝基板；將一個晶片封裝於該晶片封裝基板上，使得該晶片與該晶片封裝基板的複數第二電性連接墊電性連接；去除該加強板和該連續銅層；及形成與該複數第一電性連接墊一一電性連接的複數第一焊料凸塊，每個第一焊料凸塊均凸出於該第二表面。
  7. 如請求項6所述的晶片封裝結構的製作方法，其中，該晶片封裝基板通過 如下步驟製作形成：提供一卷帶式柔性單面覆銅基板，該卷帶式柔性單面覆銅基板包括複數沿其長度方向依次連接的單面覆銅基板單元，每個單面覆銅基板單元均包括所述柔性絕緣層以及銅箔層，該柔性絕緣層包括相對的所述第一表面及所述第二表面，該銅箔層覆蓋於該柔性絕緣層的第一表面；以卷對卷方式在每個單面覆銅基板單元的該柔性絕緣層上加工形成所述複數通孔，該複數通孔貫通該柔性絕緣層的第一表面及第二表面；以卷對卷方式將每個單面覆銅基板單元的該銅箔層製作形成導電線路圖形，從而將該卷帶式柔性單面覆銅基板製成卷帶式柔性單面線路板，該卷帶式柔性單面線路板包括由該複數單面覆銅基板單元製成的複數柔性單面線路板，其中，每個通孔均被所述導電線路圖形所覆蓋，由複數通孔從該柔性絕緣層側裸露出來的該部分導電線路圖形構成所述複數第一電性連接墊；在該卷帶式柔性單面線路板上形成防焊層，以使防焊層覆蓋每個柔性單面線路板的部分導電線路圖形表面以及從導電線路圖形露出的所述第一表面，從該防焊層露出的導電線路圖形構成複數第二電性連接墊，從而形成該晶片封裝基板，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接；以及沿每個柔性單面線路板的邊界切割卷帶式柔性單面線路板，從而獲得複數分離的柔性單面線路板。
  8. 如請求項6所述的晶片封裝結構的製作方法，其中，該晶片為導線鍵合晶片，將該導線鍵合晶片封裝於該晶片封裝基板包括步驟：提供該導線鍵合晶片，並將該導線鍵合晶片固定於該防焊層上，使該導線鍵合晶片的多條鍵合導線與所述複數第二電性連接墊一一對應連接；及 採用封裝膠體將該導線鍵合晶片包覆封裝於該晶片封裝基板上，使得封裝膠體包覆該多條鍵合導線、該晶片封裝基板的防焊層和所述複數第二電性連接墊。
  9. 如請求項6所述的晶片封裝結構的製作方法，其中，該晶片為覆晶封裝晶片，將該覆晶封裝晶片封裝於該晶片封裝基板包括步驟：在每個第二電性連接墊表面形成第二焊料凸塊；提供所述覆晶封裝晶片，該覆晶封裝晶片具有與該複數第二電性連接墊一一對應的複數接觸凸塊；使該複數接觸凸塊分別與對應的第二焊料凸塊相連接並電導通；及將底部填充劑填充於該晶片與該晶片封裝基板之間，從而將該晶片固定於該晶片封裝基板。
  10. 如請求項9所述的晶片封裝結構的製作方法，其中，使該複數接觸凸塊分別與對應的第二焊料凸塊相連接並電導通包括步驟：將覆晶封裝晶片放置於該晶片封裝基板上，並使該複數接觸凸塊分別與對應的第二焊料凸塊相接觸；以及回焊該覆晶封裝晶片和該晶片封裝基板，使每個接觸凸塊和對應的第二焊料凸塊熔融結合並冷卻固化，從而使接觸凸塊和第二焊料凸塊相互連接並電導通。
  11. 如請求項6至9任一項所述的晶片封裝結構的製作方法，其中，每個第二電性連接墊的表面均形成有表面處理層，該表面處理層通過電鍍金、鍍鎳金、化鎳浸金、鍍鎳鈀金或鍍錫的方法形成。
  12. 一種晶片封裝結構，包括：柔性絕緣層，包括相對的第一表面及第二表面，該柔性絕緣層具有複數貫通該第一表面及第二表面的通孔；導電線路圖形，形成於該柔性絕緣層的第一表面上，並覆蓋該複數通孔 ，從該複數通孔露出的導電線路圖形構成複數第一電性連接墊；防焊層，覆蓋部分該導電線路圖形以及從該導電線路圖形露出的該柔性絕緣層的第一表面，該導電線路圖形從該防焊層露出的部分構成複數第二電連接墊，該複數第二電性連接墊與該複數第一電性連接墊一一對應連接，該第一電性連接墊表面設置有第一焊料凸塊，該第一焊料凸塊突出於該第二表面，該第一焊料凸塊用於焊接另一封裝基板或印刷電路板，該第二電性連接墊用於通過鍵合導線電連接一晶片或通過焊接電連接一晶片；與該複數第二電性連接墊電性連接的晶片，該晶片固定於該防焊層上；及形成在該複數第一電性連接墊上、與該複數第一電性連接墊一一電性連接的複數第一焊料凸塊，該複數第一焊料凸塊分別從該複數第一通孔內向第二表面延伸並凸出於該第二表面。
  13. 如請求項12所述的晶片封裝結構，其中，該晶片封裝結構進一步包括封裝膠體，該晶片為導線鍵合晶片，該導線鍵合晶片固定於該防焊層上，該導線鍵合晶片的多條鍵合導線與該複數第二電性連接墊一一對應連接，該封裝膠體包覆封裝該導線鍵合晶片、該多條鍵合導線、該防焊層和所述複數第二電性連接墊。
  14. 如請求項12所述的晶片封裝結構，其中，該晶片為覆晶封裝晶片，該覆晶封裝晶片具有與該複數第二電性連接墊一一對應的複數接觸凸塊，每個第二電性連接墊上均形成有第二焊料凸塊，該複數接觸凸塊分別與對應的第二焊料凸塊相連接並電導通，該覆晶封裝晶片與該防焊層之間填充有底部填充劑以固定該晶片。
  15. 如請求項12至14任一項所述的晶片封裝結構，其中，每個第二電性連接墊表面均沈積有表面處理層，該表面處理層的材料包括金或錫。
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CN103579128B (zh) 2016-12-21

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