CN103579128A - 芯片封装基板、芯片封装结构及其制作方法 - Google Patents

芯片封装基板、芯片封装结构及其制作方法 Download PDF

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Publication number
CN103579128A
CN103579128A CN201210261162.1A CN201210261162A CN103579128A CN 103579128 A CN103579128 A CN 103579128A CN 201210261162 A CN201210261162 A CN 201210261162A CN 103579128 A CN103579128 A CN 103579128A
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Prior art keywords
chip
electric connection
layer
base plate
connection pad
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CN201210261162.1A
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CN103579128B (zh
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周鄂东
萧志忍
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Liding Semiconductor Technology Qinhuangdao Co ltd
Zhen Ding Technology Co Ltd
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Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Zhending Technology Co Ltd
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Application filed by Hongqisheng Precision Electronics Qinhuangdao Co Ltd, Zhending Technology Co Ltd filed Critical Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Priority to CN201210261162.1A priority Critical patent/CN103579128B/zh
Priority to TW101127523A priority patent/TWI483363B/zh
Priority to US13/771,320 priority patent/US8951848B2/en
Publication of CN103579128A publication Critical patent/CN103579128A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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Abstract

一种芯片封装基板，包括柔性绝缘层、导电线路图形、防焊层、连续铜层及加强板。绝缘层包括相对的第一和第二表面，且具有多个贯通该绝缘层的通孔。导电线路图形形成于该第一表面上，并覆盖多个通孔，从通孔露出的导电线路图形构成第一电性连接垫。防焊层部分覆盖导电线路图形以及露出的第一表面，导电线路图形从防焊层露出的部分形成多个第二电连接垫，第二电性连接垫与第一电性连接垫一一对应连接。连续铜层形成于柔性绝缘层的第二表面、通孔的内壁及通孔内的第一电性连接垫的表面。加强板贴合于铜层表面且覆盖该通孔。本发明还提供一种采用上述基板的封装结构及封装结构的制作方法。

Description

芯片封装基板、芯片封装结构及其制作方法
技术领域
本发明涉及电路板制作技术，尤其涉及一种芯片封装基板、具有该芯片封装基板的芯片封装结构以及该芯片封装结构的制作方法。
背景技术
芯片封装基板可为芯片提供电连接、保护、支撑、散热、组装等功效，以实现多引脚化，缩小封装产品体积、改善电性能及散热性、超高密度或多芯片模块化的目的。
当电子产品的体积日趋缩小，所采用的芯片封装基板的体积和线路间距也必须随之减小。然而，在目前现有的基板结构和工艺技术能力下，受限于铜箔的厚度，要使基板再薄化和线路间距再缩小的可能性很小，不利于应用在小型尺寸的电子产品上。因此，如何开发出新颖的薄型整合性基板，不但工艺快速简单又适合量产，以符合电子产品对于尺寸、外型轻薄化的需求，实为相关业者努力的一大重要目标。
发明内容
有鉴于此，有必要提供一种芯片封装基板、芯片封装结构及其制作方法及，以降低芯片封装基板的整体厚度并降低制造成本，以符合市场产品轻薄化和低成本的需求。
一种芯片封装基板，包括柔性绝缘层、导电线路图形、防焊层、连续铜层及加强板。该柔性绝缘层包括相对的第一表面及第二表面，该柔性绝缘层具有多个贯通该第一表面及第二表面的通孔。该导电线路图形形成于该柔性绝缘层的第一表面上，并覆盖该多个通孔，从该多个通孔露出的导电线路图形构成多个第一电性连接垫。该防焊层覆盖部分该导电线路图形的以及从该导电线路图形露出的该柔性绝缘层的第一表面，该导电线路图形从该防焊层露出的部分构成多个第二电性连接垫，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接。该连续铜层沉积于该柔性绝缘层的第二表面、该多个通孔的内壁及该多个通孔内的第一电性连接垫的表面。该加强板，其贴合于该第二表面的连续铜层表面，且该加强板覆盖该多个通孔。
一种芯片封装结构的制作方法，包括步骤：提供如上所述的芯片封装基板；将一个芯片封装于该芯片封装基板上，使得该芯片与该芯片封装基板的多个第二电性连接垫电性连接；去除该加强板和该连续铜层；及形成与该多个第一电性连接垫一一电性连接的多个第一焊料凸块，每个第一焊料凸块均凸出于该第二表面。
一种芯片封装结构，包括柔性绝缘层、导电线路图形、防焊层、芯片及多个第一焊料凸块。该柔性绝缘层包括相对的第一表面及第二表面，该柔性绝缘层具有多个贯通该第一表面及第二表面的通孔。该导电线路图形形成于该柔性绝缘层的第一表面上，并覆盖该多个通孔，从该多个通孔露出的导电线路图形构成多个第一电性连接垫。该防焊层覆盖部分该导电线路图形以及从该导电线路图形露出的该柔性绝缘层的第一表面，该导电线路图形从该防焊层露出的部分构成多个第二电连接垫，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接。该芯片与该多个第二电性连接垫电性连接，该芯片固定于该防焊层上。该多个第一焊料凸块与该多个第一电性连接垫一一电性连接，该多个第一焊料凸块分别从该多个第一通孔内向第二表面延伸并凸出于该第二表面。
本技术方案的芯片封装基板、芯片封装结构及其制作方法所使用的绝缘材料为柔性材料，其可以做的较薄，并且，本技术方案的芯片封装基板为单层，整体厚度较薄，制作方法简单，可降低制造成本，符合市场产品轻薄化和低成本的需求。
附图说明
图1是本发明第一实施例提供的柔性单面覆铜基板的剖面示意图。
图2是图1中的柔性单面覆铜基板上形成多个通孔后的剖面示意图。
图3是图2的铜箔层及柔性绝缘层上覆盖干膜后的剖面示意图。
图4是图2中的铜箔层形成导电线路图形后所形成的柔性单面线路板的剖面示意图。
图5是在图4的柔性单面线路板上形成防焊层的剖面示意图。
图6是在图5的柔性单面线路板的柔性绝缘层上形成铜层后的剖面示意图。
图7是将图6的柔性单面线路板铜层上压合加强板后的剖面示意图。
图8是在图7的柔性单面线路板上形成表面处理层后形成的芯片封装基板的剖面示意图。
图9是在图8的芯片封装基板上固定一芯片后的剖面示意图。
图10是在图8中的芯片封装基板和芯片上形成封装胶体后形成的封装体的剖面示意图。
图11是将图10的封装体去除加强板后的剖面示意图。
图12是将图11的封装体去除铜层后的剖面示意图。
图13是在图12的封装体上形成第一焊料凸块后形成的芯片封装结构的剖面示意图。
图14是本发明第二实施例提供的芯片封装结构的剖面示意图。
主要元件符号说明
柔性单面线路板 10
柔性绝缘层 11
导电线路图形 12
第一表面 111
第二表面 112
通孔 13
第一电性连接垫 121
柔性单面覆铜基板 10a
铜箔层 14
第一干膜 113
第二干膜 114
防焊层 15
第二电性连接垫 16
铜层 18
表面处理层 161
加强板 115
芯片封装基板 20
芯片 30
键合导线 32
粘胶层 31
封装胶体 40
封装体 41
第一焊料凸块 46
芯片封装结构 50
芯片封装结构 60
芯片 30a
接触凸块 32a
第二焊料凸块 161a
底部填充剂 40a
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合附图及实施例对本技术方案提供的芯片封装基板和芯片封装结构及其制作方法作进一步的详细说明。
请参阅图1至图13，本技术方案第一实施例提供的芯片封装基板的制作方法包括以下步骤：
步骤1：请参阅图1至图4，提供柔性单面线路板10，该柔性单面线路板10包括相互叠合的柔性绝缘层11及导电线路图形12。该柔性绝缘层11包括相对的第一表面111及第二表面112，该柔性绝缘层11上形成有多个贯通该第一表面111及第二表面112的通孔13，该导电线路图形12覆盖于该柔性绝缘层11的第一表面111上，且该导电线路图形12覆盖该通孔13。该多个通孔13分别用于填充预焊料，以形成焊料凸块。
该柔性单面线路板10可以采用下述方法形成：
第一，请参阅图1，提供柔性单面覆铜基板10a，该柔性单面覆铜基板10a包括一个柔性绝缘层11及一铜箔层14。该柔性绝缘层11包括相对的所述第一表面111及第二表面112，该铜箔层14覆盖于该柔性绝缘层11的第一表面111上。该柔性单面覆铜基板10a可以通过裁切卷带式单面覆铜基板而形成。
该柔性绝缘层11的材质为柔性线路板常用的柔性材料，如聚酰亚胺（Polyimide, PI）、聚乙烯对苯二甲酸乙二醇酯(Polyethylene Terephthalate, PET)或聚萘二甲酸乙二醇酯(Polyethylene Naphthalate，PEN)等，优选为耐热性较好的聚酰亚胺。该柔性绝缘层11的厚度范围可以为15μm-250μm，优选为25μm-50μm，以同时满足较好的机械强度及较薄的产品厚度的要求。该铜箔层14优选为压延铜箔，也可以为电解铜箔。该铜箔层14的厚度优选为12μm-35μm。当然，该柔性绝缘层11及该铜箔层14的厚度还可以为其他厚度值。
第二，请一并参阅图2，在该柔性绝缘层11中形成所述多个通孔13。该通孔13贯通该柔性绝缘层11的第一表面111及第二表面112，而不贯通该铜箔层14，从而使该多个通孔13对应处的铜箔层14从该柔性绝缘层11的第二表面112一侧裸露出来。该多个通孔13可以通过激光钻孔工艺或者定深机械钻孔工艺形成。每个通孔13的横截面的形状为圆形，当然也可以根据需要设计为其他形状。
第三，请一并参阅图3-4，将该铜箔层14制作形成该导电线路图形12。该导电线路图形12覆盖每个通孔13，且导电线路图形12暴露在多个通孔13的部分构成多个第一电性连接垫121。本实施例中，可以采用影像转移工艺及蚀刻工艺将该铜箔层14制作形成导电线路图形12。以下以采用干膜进行影像转移制作导电线路图形12为例说明，制作形成导电线路图形12的步骤可包括：
首先，对该铜箔层14及该柔性绝缘层11的表面进行表面微蚀处理，以去除该铜箔层14及该柔性绝缘层11表面的污渍、油脂等，并使该铜箔层14的表面轻微腐蚀以具有一定的粗糙度，以有利于提高该铜箔层14与后续步骤中的干膜之间的结合力，防止铜箔层14与干膜之间有气泡、杂质的出现，进一步提高下一步中干膜显影的解析度。当然，也可以采用其他表面处理方式如等离子体处理等对该铜箔层14及该柔性绝缘层11进行表面处理。
其次，请参阅图3，在该铜箔层14上压合一第一干膜113，及在该柔性绝缘层11的第二表面112上压合一第二干膜114。
在该柔性绝缘层11的第二表面112上覆盖第二干膜114，是为了防止后续步骤中的蚀刻药水进入该通孔13内腐蚀裸露的铜箔层14。当然，第二干膜114也可以替换为低粘性的覆盖膜、胶带等遮挡物；另外，第二干膜114也可仅覆盖该通孔13的开口及周围的部分第二表面112上，而无需覆盖整个第二表面112，只要可以阻挡药水进入通孔13即可。
第四，请参阅图4，通过曝光、显影、蚀刻以及剥膜工艺将该铜箔层14制作形成导电线路图形12，形成柔性单面线路板10。
本实施例对该铜箔层14上的第一干膜113进行选择性曝光，对该第二表面112上的第二干膜114进行整面曝光。该铜箔层14上的第一干膜113经过曝光显影后形成图案化的干膜层，使得铜箔层14需要蚀刻去除的部分露出第一干膜113，而铜箔层14需要形成线路的部分仍被第一干膜113覆盖。利用铜蚀刻液进行蚀刻，以去除露出第一干膜113的铜箔层14，从而使得铜箔层14被图案化的干膜覆盖的部分形成导电线路图形12。每个通孔13均被导电线路图形12覆盖。
当然，也可以通过湿膜工艺将该铜箔层14制作形成导电线路图形12。另外，将该铜箔层14制作形成导电线路图形12之后，还可以包括冲孔工艺，以形成多个工具孔（图未示），该工具孔贯通柔性绝缘层11及导电线路图形12。该工具孔用于后续步骤中对线路板进行定位。
步骤2：请参阅图5，在该导电线路图形12的表面部分区域以及从该导电线路图形12露出的柔性绝缘层11的第一表面111形成防焊层15，使该导电线路图形12上未被覆盖防焊层15的部位构成多个第二电性连接垫16。每个第二电性连接垫16与一个第一电性连接垫121对应且通过导电线路图形12中的线路连接。或者说，该多个第二电性连接垫16分别由该多个通孔13露出的第一电性连接垫121延伸形成。该多个第一电性连接垫121与该多个第二电性连接垫16一一对应连接。
本实施例中，使用液态感光防焊油墨制作防焊层，其步骤为：在该导电线路图形12表面以及导电线路图形12的间隙印刷液态感光防焊油墨；预烘烤使该液态感光防焊油墨表面预固化；通过选择性UV曝光使该液态感光防焊油墨部分区域发生交联反应；通过显影流程将该液态感光防焊油墨的未发生交联反应的区域去除，以露出多个第二电性连接垫16；最后，加热固化该液态感光防焊油墨，从而在该导电线路图形12的部分区域以及导电线路图形12的间隙形成防焊层15，该导电线路图形12未覆盖防焊层15的部位为防焊层开口区。
该液态感光防焊油墨优选为软板专用的具有耐挠折性能的液态感光防焊油墨，以防该防焊层15在后续的制作流程中以及使用中发生断裂。当然，也可以使用具有耐挠折性能的热固性油墨形成该防焊层15，此时不需要曝光显影，只需要使用有图案的网版在该导电线路图形12的部分区域以及导电线路图形12的间隙印刷该热固性油墨，在需要防焊层15开口的部位通过网版遮蔽使热固性油墨不能印刷到该第二电性连接垫16即可，之后加热固化该热固性油墨即可形成该防焊层15。
可以理解的是，步骤1和步骤2的过程可为卷对卷（roll to roll, RTR）制程，该卷对卷制程可采用如下方法进行：
（一）提供一卷带式柔性单面覆铜基板，该卷带式柔性单面覆铜基板包括多个沿其长度方向依次连接的单面覆铜基板单元，每个单面覆铜基板单元均包括柔性绝缘层11以及铜箔层14，该柔性绝缘层11包括相对的所述第一表面111及所述第二表面112，该铜箔层14层覆盖于该柔性绝缘层11的第一表面111。
（二）以卷对卷方式在每个单面覆铜基板单元的该柔性绝缘层11上加工形成该多个通孔13，该多个通孔13贯通该柔性绝缘层11的第一表面111及第二表面112；
（三）以卷对卷方式将每个单面覆铜基板单元的该铜箔层14制作形成导电线路图形12，从而将该卷带式柔性单面覆铜基板制成卷带式柔性单面线路板，该卷带式柔性单面线路板包括由该多个单面覆铜基板单元制成的多个柔性单面线路板10，其中，每个通孔13均被所述导电线路图形12所覆盖，由多个通孔13从该柔性绝缘层11侧裸露出来的该部分导电线路图形12构成所述多个第一电性连接垫121。
（四）在该卷带式柔性单面线路板上形成防焊层15，以使防焊层15覆盖每个柔性单面线路板10的部分导电线路图形12表面以及从导电线路图形12露出的所述第一表面111，从该防焊层15露出的导电线路图形12构成多个第二电性连接垫16，该多个第二电性连接垫16与该多个第一电性连接垫121一一对应连接。
（五）沿每个柔性单面线路板10的边界切割卷带式柔性单面线路板，从而获得多个分离的具有防焊层15的柔性单面线路板10。
上述卷对卷制程的形成通孔13、制作导电线路图形12以及形成防焊层15的方法与步骤1和步骤2中对应的方法相同。
步骤3：请参阅图6至8，在该第二表面112、通孔13的内壁以及第一电性连接垫121表面形成一层连续的铜层18，在该柔性绝缘层11的第二表面112一侧贴合加强板115，以及在该多个第二电性连接垫16上形成表面处理层161，从而形成芯片封装基板20。
本步骤中形成铜层18、贴合加强板115以及在第二电性连接垫16上形成表面处理层161的步骤如下：
第一，请参阅图6，在该柔性绝缘层11的第二表面112、该通孔13的内壁上以及该第一电性连接垫121上通过溅镀形成一层连续的铜层18。该铜层18位于该第一电性连接垫121上的部分与该第一电性连接垫121紧密结合，从而使该铜层18与该导电线路图形12相导通。该铜层18与该导电线路图形12相导通的作用为在后续步骤中进行电镀金时形成通路。当然，该铜层18也可以通过化学镀铜等方式形成。优选地，该铜层18小于或等于25微米。
第二，请参阅图7，在该第二表面112的铜层18上贴合加强板115，该加强板115覆盖铜层18及通孔13。加强板115可通过胶片粘接于该铜层18上。该加强板115的其中一作用为保护该铜层18，以防止在该铜层18被镀金药水侵蚀、污染以及防止该铜层18上镀上金，另一作用为支撑该柔性单面线路板10。该加强板115的材质可以为增强材料的环氧树脂板、酚醛树脂板或金属板等，当然不限于上述材料，一般具有支撑作用的材料均可用于所述加强板115。
第三，请参阅图8，在该多个第二电性连接垫16上分别形成表面处理层161，以保护该第二电性连接垫16以防止其氧化。
本实施例中，形成该多个表面处理层161的方式为电镀金。该多个表面处理层161分别与对应的第二电性连接垫16电导通。可以理解，形成该表面处理层161的方法也可以取代为镀镍金、化镍浸金、镀镍钯金、镀锡等，并不以本实施例为限，当然，该表面处理层161也可以省略。
至此，芯片封装基板20制作完成。该芯片封装基板20包括该柔性绝缘层11、形成柔性绝缘层11的第一表面111的导电线路图形12及防焊层15。该柔性绝缘层11的第二表面112形成有多个通孔13，导电线路图形12覆盖该多个通孔13，该导电线路图形12从该多个通孔13的第二表面112一侧露出的部分形成多个第一电性连接垫121。该柔性绝缘层11的第二表面112、该通孔13的内壁以及该第一电性连接垫121上形成有一层连续的铜层18。该第二表面112的铜层18上贴附有加强板115，且该加强板115覆盖铜层18及通孔13，该加强板115的材质可以为增强材料的环氧树脂板、酚醛树脂板或金属板等。该防焊层15覆盖该导电线路图形12的表面部分区域以及从该导电线路图形12露出的柔性绝缘层11的第一表面111，该导电线路图形12上未被覆盖防焊层15的部位形成多个第二电性连接垫16，该多个第二电性连接垫16与该多个第一电性连接垫121一一对应连接，每个第二电性连接垫16的表面形成表面处理层161，该表面处理层161的材料可以为镍金、镍钯金、锡等。
该芯片封装基板20可进一步通过后续步骤将芯片30封装于其上，也可以被包装后运送至芯片封装工厂进行后续的芯片封装。具体的芯片封装步骤如步骤4-7所述。
步骤4：请参阅图9，提供一导线接合（wire bonding, WB）芯片30，并将芯片30与第二电性连接垫16电性连接。具体的，芯片30具有多个键合接点以及自多个键合接点延伸的多条键合导线32，键合导线32与第二电性连接垫16一一对应。多条键合导线32的一端电性连接该芯片30，另一端分别电性连接该多个第二电性连接垫16表面的表面处理层161，从而使芯片30与导电线路图形12电连接。
优选的，该芯片30通过一粘胶层31固定于该防焊层15表面，该键合导线32可通过焊接的方式连接于对应的表面处理层161。该键合导线32的材料一般为金。
步骤5：请参阅图10，采用封装胶体40将键合导线32、芯片30及芯片封装基板20外露的防焊层15和表面处理层161进行包覆封装，形成一封装体41。该键合导线32、芯片30均完全包覆于该封装胶体40内。本实施例中，该封装胶体40为黑胶，当然，该封装胶体40也可以其它封装胶体材料，并不以本实施例为限。
步骤6：请参阅图11及图12，去除该加强板115和该铜层18。
通过剥除的方式将该铜层18上的加强板115去除，之后再通过蚀刻的方式去除该铜层18，从而使所述柔性绝缘层11的第二表面112及第一电性连接垫121露出。通过蚀刻液去除该铜层18时，封装体41在蚀刻液中不能停留太长时间，以防止所述第一电性连接垫121被侵蚀。
步骤7：请参阅图13，在每个通孔13内填充焊料，并使焊料固化形成第一焊料凸块46，每个第一焊料凸块46均突出于该第二表面112，每个通孔13表面的第一焊料凸块46与该通孔13对应的第一电性连接垫121电连接，从而，形成一芯片封装结构50。
本实施例中，每个第一焊料凸块46凸出于该第二表面112部分的形状为球状，即该第一焊料凸块46为焊球状，可以理解该第一焊料凸块46的形状不限，还可以椭球状、柱体状等。该第一焊料凸块46的材料一般主要包括锡，其可通过电镀或印刷的方式形成。该第一焊料凸块46用于与另一芯片封装基板（图未示）上的焊垫电连接并封装在一起，或者与印刷电路板（图未示）上焊垫电连接并封装在一起。
由于该第二电性连接垫16与第一电性连接垫121通过导电线路图形12电性连接，所以当该芯片封装结构50封装于另一封装基板或印刷电路板上时，该芯片30可依次通过该键合导线32、表面处理层161、第二电性连接垫16、第一电性连接垫121及第一焊料凸块46，最终电连接于另一封装基板或印刷电路板。
经过本实施例的制作方法制作而成的芯片封装结构50包括柔性绝缘层11、形成柔性绝缘层11的第一表面111的导电线路图形12、防焊层15、芯片30、封装胶体40及多个第一焊料凸块46。该柔性绝缘层11的第二表面112形成有多个通孔13，导电线路图形12覆盖该多个通孔13，该导电线路图形12从该多个通孔13的第二表面112一侧露出的部分形成多个第一电性连接垫121。该多个第一焊料凸块46分别填充于该多个通孔13，该多个第一焊料凸块46分别与对应的第一电性连接垫121电连接并凸出于该第二表面112。本实施例中，该多个第一焊料凸块46凸出于第二表面112的部分呈球形，该多个第一焊料凸块46凸出于第二表面112的部分的形状还可以为椭球状、柱体状等，并不以本实施例为限。该防焊层15覆盖该导电线路图形12的表面部分区域以及从该导电线路图形12露出的柔性绝缘层11的第一表面111，该导电线路图形12上未被覆盖防焊层15的部位形成多个第二电性连接垫16，该多个第二电性连接垫16与该多个第一电性连接垫121通过导电线路图形12一一对应连接，每个第二电性连接垫16的表面形成有表面处理层161。该芯片30通过一粘胶层31固定于该防焊层15上。该芯片30具有多个键合接点以及自多个键合接点延伸的多条键合导线32，该多条键合导线32与多个第二电性连接垫16一一对应连接。封装胶体40包覆该键合导线32、芯片30及芯片封装基板20的外露的防焊层15和表面处理层161。本实施例中，该封装胶体40为黑胶。
本技术方案的芯片封装基板20及芯片封装结构50所使用的绝缘材料为聚酰亚胺等柔性材料，其可以做的较薄；另外，本技术方案的芯片封装基板20的导电线路图形12为单层，整体厚度较薄，制作方法较简单，可降低制造成本，符合市场产品轻薄化和低成本的需求。
请参阅图14，本发明第二实施例提供一种芯片封装结构60及其制作方法。该芯片封装结构60与第一实施例的芯片封装结构50结构相似，不同之处在于，芯片封装结构60中的芯片30a为覆晶封装（flip-chip）芯片，芯片30a的封装方式为覆晶封装。也就是说，该芯片封装结构60包括芯片30a、柔性绝缘层11、导电线路图形12、防焊层15及多个第一焊料凸块46。本实施例中的柔性绝缘层11、导电线路图形12、防焊层15及多个第一焊料凸块46的结构位置关系与第一实施例中的柔性绝缘层11、导电线路图形12、防焊层15及多个第一焊料凸块46相同。其不同之处在于，芯片30a具有与该多个第二电性连接垫16一一对应的接触凸块32a，该多个第二电性连接垫16表面的表面处理层161表面均形成有第二焊料凸块161a。该芯片30a的多个接触凸块32a分别与该多个第二电性连接垫16表面的第二焊料凸块161a相接触并电连接。该接触凸块32a也可以由焊料制成。该芯片30a与该防焊层15之间填充有底部填充剂40a，以使芯片30a与导电线路图形12及防焊层15牢固结合，增强芯片封装结构60的信赖度。本实施例中，省去了第一实施例的封装胶体40。
该芯片封装结构60的制作方法与第一实施例的制作方法不同之处在于步骤4和步骤5，其它步骤1-3、6-7对应相同，本实施例中采用步骤4’和步骤5’取代第一实施例制作方法的步骤4和步骤5，具体如下所述：
步骤4’：提供所述覆晶封装芯片30a，芯片30a具有分别与该多个第二电性连接垫16对应的多个接触凸块32a，在该多个第二电性连接垫16的表面处理层161的表面分别形成第二焊料凸块161a，并使该多个接触凸块32a分别与对应的第二焊料凸块161a相连接并电导通。
本实施例中，可通过电镀或印刷的方式将多个第二焊料凸块161a分别形成于对应的表面处理层161的表面，且该多个第二焊料凸块161a凸出于该防焊层15的表面。该第二焊料凸块161a可以为柱状、球状等，本实施例中为柱状，其材料一般主要为锡。该接触凸块32a的形状一般为球状，其一般也由焊料制成，其材料主要为锡。该多个接触凸块32a与对应的第二焊料凸块161a的连接可采用如下方法：首先，将覆晶封装芯片30a放置于设置了多个第二焊料凸块161a的芯片封装基板20上，并使该多个接触凸块32a分别与对应的第二焊料凸块161a相接触；然后，将该芯片30a和设置了多个第二焊料凸块161a的芯片封装基板20一起经过回焊炉，使接触凸块32a和第二焊料凸块161a熔融结合后冷却固化，从而使接触凸块32a和第二焊料凸块161a相互连接并电导通。
步骤5’：将底部填充剂40a填充于该芯片30a与芯片封装基板20之间的缝隙内，从而将该芯片30a与芯片封装基板20封装固定。将步骤5’制得的封装体再经过与第一实施例的步骤6和步骤7类似的方法去除加强板115和铜层18及形成第一焊料凸块46，获得芯片封装结构60。底部填充剂40a粘结芯片30a的表面以及防焊层15的表面，并包围接触凸块32a及第二焊料凸块161a。
该底部填充剂40a的填充是通过毛细作用，将液态的底部填充剂40a的材料从芯片30a的边缘渗透至该芯片30a与芯片封装基板20之间的内部区域。该底部填充剂40a一般采种环氧树脂，如底部填充剂材料Loctite 3536。
可以理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术构思做出其它各种相应的改变与变形，而所有这些改变与变形都应属于本发明权利要求的保护范围。

Claims (16)

1.一种芯片封装基板，包括：
柔性绝缘层，其包括相对的第一表面及第二表面，该柔性绝缘层具有多个贯通该第一表面及第二表面的通孔；
导电线路图形，形成于该柔性绝缘层的第一表面上，并覆盖该多个通孔，从该多个通孔露出的导电线路图形构成多个第一电性连接垫；
防焊层，覆盖部分该导电线路图形的以及从该导电线路图形露出的该柔性绝缘层的第一表面，该导电线路图形从该防焊层露出的部分构成多个第二电性连接垫，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接；
连续铜层，沉积于该柔性绝缘层的第二表面、该多个通孔的内壁及该多个通孔内的第一电性连接垫的表面；及
加强板，其贴合于该第二表面的连续铜层表面，且该加强板覆盖该多个通孔。
2.如权利要求1所述的芯片封装基板，其特征在于，每个第二电性连接垫的表面均沉积有表面处理层。
3.如权利要求2所述的芯片封装基板，其特征在于，该表面处理层的材料包括金或锡。
4.如权利要求1所述的芯片封装基板，其特征在于，该加强板的材料为环氧树脂板、酚醛树脂板或金属板。
5.如权利要求1所述的芯片封装基板，其特征在于，该连续铜层的厚度小于或等于25微米。
6.一种芯片封装结构的制作方法，包括步骤：
提供如权利要求1所述的芯片封装基板；
将一个芯片封装于该芯片封装基板上，使得该芯片与该芯片封装基板的多个第二电性连接垫电性连接；
去除该加强板和该连续铜层；及
形成与该多个第一电性连接垫一一电性连接的多个第一焊料凸块，每个第一焊料凸块均凸出于该第二表面。
7.如权利要求6所述的芯片封装结构的制作方法，该芯片封装基板通过如下步骤制作形成：
提供一柔性单面覆铜基板，该柔性单面覆铜基板包括该柔性绝缘层以及铜箔层，该柔性绝缘层包括相对的该第一表面及该第二表面，该铜箔层覆盖于该柔性绝缘层的第一表面；
在该柔性绝缘层上形成该多个通孔，该多个通孔贯通该柔性绝缘层的第一表面及第二表面；
通过将该铜箔层制作形成导电线路图形，从而将该柔性单面覆铜基板制成柔性单面线路板，其中，每个通孔均被该导电线路图形所覆盖，由多个通孔从该柔性绝缘层侧裸露出来的该部分导电线路图形构成该多个第一电性连接垫；及
在该柔性单面线路板的部分导电线路图形表面以及从导电线路图形露出的该第一表面形成该防焊层，使从该防焊层露出的导电线路图形构成多个第二电性连接垫，从而形成该芯片封装基板，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接。
8.如权利要求6所述的芯片封装结构的制作方法，其特征在于，该芯片封装基板通过如下步骤制作形成：
提供一卷带式柔性单面覆铜基板，该卷带式柔性单面覆铜基板包括多个沿其长度方向依次连接的单面覆铜基板单元，每个单面覆铜基板单元均包括所述柔性绝缘层以及铜箔层，该柔性绝缘层包括相对的所述第一表面及所述第二表面，该铜箔层覆盖于该柔性绝缘层的第一表面；
以卷对卷方式在每个单面覆铜基板单元的该柔性绝缘层上加工形成所述多个通孔，该多个通孔贯通该柔性绝缘层的第一表面及第二表面；
以卷对卷方式将每个单面覆铜基板单元的该铜箔层制作形成导电线路图形，从而将该卷带式柔性单面覆铜基板制成卷带式柔性单面线路板，该卷带式柔性单面线路板包括由该多个单面覆铜基板单元制成的多个柔性单面线路板，其中，每个通孔均被所述导电线路图形所覆盖，由多个通孔从该柔性绝缘层侧裸露出来的该部分导电线路图形构成所述多个第一电性连接垫；
在该卷带式柔性单面线路板上形成防焊层，以使防焊层覆盖每个柔性单面线路板的部分导电线路图形表面以及从导电线路图形露出的所述第一表面，从该防焊层露出的导电线路图形构成多个第二电性连接垫，从而形成该芯片封装基板，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接；以及
沿每个柔性单面线路板的边界切割卷带式柔性单面线路板，从而获得多个分离的柔性单面线路板。
9.如权利要求6所述的芯片封装结构的制作方法，其特征在于，该芯片为导线键合芯片，将该导线键合芯片封装于该芯片封装基板包括步骤：
提供该导线键合芯片，并将该导线键合芯片固定于该防焊层上，使该导线键合芯片的多条键合导线与所述多个第二电性连接垫一一对应连接；及
采用封装胶体将该导线键合芯片包覆封装于该芯片封装基板上，使得封装胶体包覆该多条键合导线、该芯片封装基板的防焊层和所述多个第二电性连接垫。
10.如权利要求6所述的芯片封装结构的制作方法，其特征在于，该芯片为覆晶封装芯片，将该覆晶封装芯片封装于该芯片封装基板包括步骤：
在每个第二电性连接垫表面形成第二焊料凸块；
提供所述覆晶封装芯片，该覆晶封装芯片具有与该多个第二电性连接垫一一对应的多个接触凸块；
使该多个接触凸块分别与对应的第二焊料凸块相连接并电导通；及
将底部填充剂填充于该芯片与该芯片封装基板之间，从而将该芯片固定于该芯片封装基板。
11.如权利要求10所述的芯片封装结构的制作方法，其特征在于，使该多个接触凸块分别与对应的第二焊料凸块相连接并电导通包括步骤：
将覆晶封装芯片放置于该芯片封装基板上，并使该多个接触凸块分别与对应的第二焊料凸块相接触；以及
回焊该覆晶封装芯片和该芯片封装基板，使每个接触凸块和对应的第二焊料凸块熔融结合并冷却固化，从而使接触凸块和第二焊料凸块相互连接并电导通。
12.如权利要求7至10任一项所述的芯片封装结构的制作方法，其特征在于，每个第二电性连接垫的表面均形成有表面处理层，该表面处理层通过电镀金、镀镍金、化镍浸金、镀镍钯金或镀锡的方法形成。
13.一种芯片封装结构，包括：
柔性绝缘层，包括相对的第一表面及第二表面，该柔性绝缘层具有多个贯通该第一表面及第二表面的通孔；
导电线路图形，形成于该柔性绝缘层的第一表面上，并覆盖该多个通孔，从该多个通孔露出的导电线路图形构成多个第一电性连接垫；
防焊层，覆盖部分该导电线路图形以及从该导电线路图形露出的该柔性绝缘层的第一表面，该导电线路图形从该防焊层露出的部分构成多个第二电连接垫，该多个第二电性连接垫与该多个第一电性连接垫一一对应连接；
与该多个第二电性连接垫电性连接的芯片，该芯片固定于该防焊层上；及
与该多个第一电性连接垫一一电性连接的多个第一焊料凸块，该多个第一焊料凸块分别从该多个第一通孔内向第二表面延伸并凸出于该第二表面。
14.如权利要求13所述的芯片封装结构，其特征在于，该芯片封装结构进一步包括封装胶体，该芯片为导线键合芯片，该导线键合芯片固定于该防焊层上，该导线键合芯片的多条键合导线与该多个第二电性连接垫一一对应连接，该封装胶体包覆封装该导线键合芯片、该多条键合导线、该防焊层和所述多个第二电性连接垫。
15.如权利要求13所述的芯片封装结构，其特征在于，该芯片为覆晶封装芯片，该覆晶封装芯片具有与该多个第二电性连接垫一一对应的多个接触凸块，每个第二电性连接垫上均形成有第二焊料凸块，该多个接触凸块分别与对应的第二焊料凸块相连接并电导通，该覆晶封装芯片与该防焊层之间填充有底部填充剂以固定该芯片。
16.如权利要求13至15任一项所述的芯片封装结构，其特征在于，每个第二电性连接垫表面均沉积有表面处理层，该表面处理层的材料包括金或锡。
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CN110769665A (zh) * 2018-07-27 2020-02-07 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769664A (zh) * 2018-07-27 2020-02-07 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769672A (zh) * 2018-07-27 2020-02-07 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769671B (zh) * 2018-07-27 2024-04-26 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769668B (zh) * 2018-07-27 2024-04-23 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769665B (zh) * 2018-07-27 2023-12-05 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769670B (zh) * 2018-07-27 2023-12-05 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769667A (zh) * 2018-07-27 2020-02-07 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769664B (zh) * 2018-07-27 2024-02-06 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN110769672B (zh) * 2018-07-27 2024-04-23 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
CN111735982A (zh) * 2020-06-30 2020-10-02 上海矽睿科技有限公司 一种加速度计封装的方法
CN116246962A (zh) * 2021-12-07 2023-06-09 礼鼎半导体科技(深圳)有限公司 封装结构及其制造方法
CN116246962B (zh) * 2021-12-07 2024-10-22 礼鼎半导体科技(深圳)有限公司 封装结构及其制造方法

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