JP4906462B2 - 電子部品内蔵基板および電子部品内蔵基板の製造方法 - Google Patents
電子部品内蔵基板および電子部品内蔵基板の製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
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- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Description
101 コア基板
102 ビアプラグ
103A,104B,108,113 絶縁層
104,105,106,109,110,111,112 導電パターン
107,112,114 ソルダーレジスト層
115 はんだバンプ
200 絶縁層
200A,200B,200C 樹脂層
201 ポスト
201a,202c シード層
202,203 導電パターン
202A,203A ビアプラグ
202B,203B パターン配線
301 電子部品
302 バンプ
303 はんだ層
304 アンダーフィル
305 電子部品
306 バンプ
400 電子部品内蔵基板
Claims (10)
- 第1の導電パターンが形成された基板と、
前記基板に実装された電子部品と、
硬度調整のための添加材料の添加率が異なる複数の樹脂層が積層されて構成される、前記電子部品を埋設する絶縁層と、
前記絶縁層上に形成された第2の導電パターンと、
前記第1の導電パターンと前記第2の導電パターンを接続する導電性のポストと、を有し、
前記絶縁層は、前記第1の導電パターン側に形成される第1の樹脂層と、前記第2の導電パターン側に形成される第3の樹脂層との間に第2の樹脂層が形成されて構成され、前記第2の樹脂層の前記添加材料の添加率は、前記第1の樹脂層と前記第3の樹脂層の添加率より大きいことを特徴とする電子部品内蔵基板。 - 前記添加材料は、SiO2を主成分とすることを特徴とする請求項1記載の電子部品内蔵基板。
- 前記第1の樹脂層の前記添加材料の添加率は、前記第3の樹脂層の添加率よりも大きいことを特徴とする請求項1または2記載の電子部品内蔵基板。
- 前記第1の樹脂層に添加される前記添加材料は、ガラスクロス繊維を含むことを特徴とする請求項1乃至3いずれか一項に記載の電子部品内蔵基板。
- 前記第2の樹脂層の厚さが、前記第1の樹脂層及び前記第3の樹脂層の厚さよりも厚いことを特徴とする請求項1乃至4いずれか一項に記載の電子部品内蔵基板。
- 第1の導電パターンが形成された基板に電子部品を実装する第1の工程と、
硬度調整のための添加材料の添加率が異なる複数の樹脂層よりなる、前記電子部品を埋設する絶縁層と、前記第1の導電パターンに接続される導電性のポストとを形成する第2の工程と、
前記絶縁層上に、前記ポストに接続される第2の導電パターンを形成する第3の工程と、を有し、
前記絶縁層は、前記第1の導電パターン側に形成される第1の樹脂層と、前記第2の導電パターン側に形成される第3の樹脂層との間に第2の樹脂層が形成されて構成され、前記第2の樹脂層の前記添加材料の添加率は、前記第1の樹脂層と前記第3の樹脂層の添加率より大きいことを特徴とする電子部品内蔵基板の製造方法。 - 前記添加材料は、SiO2を主成分とすることを特徴とする請求項6記載の電子部品内蔵基板の製造方法。
- 前記第2の工程は、
前記第1の樹脂層を形成し、該第1の樹脂層上にセミアディティブ法により前記ポストを形成する工程と、
前記ポストを埋設する前記第2の樹脂層を形成する工程と、
前記第3の樹脂層を形成する工程と、を有し、
前記第3の工程は、
前記第3の樹脂層上にセミアディティブ法により前記第2の導電パターンを形成する工程を有することを特徴とする請求項6または7記載の電子部品内蔵基板の製造方法。 - 前記第1の樹脂層に添加される前記添加材料は、ガラスクロス繊維を含むことを特徴とする請求項6乃至8いずれか一項に記載の電子部品内蔵基板の製造方法。
- 前記第2の樹脂層の厚さが、前記第1の樹脂層及び前記第3の樹脂層の厚さよりも厚いことを特徴とする請求項6乃至9いずれか一項に記載の電子部品内蔵基板の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006277896A JP4906462B2 (ja) | 2006-10-11 | 2006-10-11 | 電子部品内蔵基板および電子部品内蔵基板の製造方法 |
KR1020070100209A KR20080033069A (ko) | 2006-10-11 | 2007-10-05 | 전자 부품 내장 기판 및 그 제조 방법 |
US11/907,179 US7994431B2 (en) | 2006-10-11 | 2007-10-10 | Substrate with built-in electronic component and method for manufacturing the same |
TW096137963A TW200818440A (en) | 2006-10-11 | 2007-10-11 | Substrate with built-in electronic component and method for manufacturing the same |
CNA2007101525666A CN101162716A (zh) | 2006-10-11 | 2007-10-11 | 具有内置式电子元件的基板及其制造方法 |
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JP2006277896A JP4906462B2 (ja) | 2006-10-11 | 2006-10-11 | 電子部品内蔵基板および電子部品内蔵基板の製造方法 |
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JP2008098366A JP2008098366A (ja) | 2008-04-24 |
JP4906462B2 true JP4906462B2 (ja) | 2012-03-28 |
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US (1) | US7994431B2 (ja) |
JP (1) | JP4906462B2 (ja) |
KR (1) | KR20080033069A (ja) |
CN (1) | CN101162716A (ja) |
TW (1) | TW200818440A (ja) |
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KR101009158B1 (ko) * | 2008-07-03 | 2011-01-18 | 삼성전기주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
US8298914B2 (en) * | 2008-08-19 | 2012-10-30 | International Business Machines Corporation | 3D integrated circuit device fabrication using interface wafer as permanent carrier |
JP5477372B2 (ja) * | 2009-03-11 | 2014-04-23 | 日本電気株式会社 | 機能素子内蔵基板、及びその製造方法、並びに電子機器 |
JP5483921B2 (ja) * | 2009-04-22 | 2014-05-07 | 株式会社メイコー | プリント基板の製造方法 |
US8786062B2 (en) | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8569894B2 (en) * | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
WO2011132274A1 (ja) * | 2010-04-21 | 2011-10-27 | 株式会社メイコー | 部品内蔵基板及びこれを用いた多層基板並びに部品内蔵基板の製造方法 |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
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CN103579128B (zh) * | 2012-07-26 | 2016-12-21 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及其制作方法 |
US9443797B2 (en) | 2012-09-14 | 2016-09-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device having wire studs as vertical interconnect in FO-WLP |
US9385052B2 (en) | 2012-09-14 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages |
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JP5639242B2 (ja) * | 2013-04-12 | 2014-12-10 | 太陽誘電株式会社 | 電子部品内蔵基板 |
JP2015028986A (ja) * | 2013-07-30 | 2015-02-12 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
US9893017B2 (en) | 2015-04-09 | 2018-02-13 | STATS ChipPAC Pte. Ltd. | Double-sided semiconductor package and dual-mold method of making same |
JP6652443B2 (ja) * | 2016-05-06 | 2020-02-26 | 株式会社日本マイクロニクス | 多層配線基板及びこれを用いたプローブカード |
US10600748B2 (en) | 2016-06-20 | 2020-03-24 | Samsung Electronics Co., Ltd. | Fan-out semiconductor package |
US11211341B2 (en) * | 2019-12-19 | 2021-12-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of fabrcating the same |
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JPS61133696A (ja) * | 1984-12-03 | 1986-06-20 | 日立化成工業株式会社 | 配線板の製造法 |
JPH01225196A (ja) * | 1988-03-03 | 1989-09-08 | Marcon Electron Co Ltd | 積層混成集積回路の製造方法 |
JPH0486833A (ja) * | 1990-07-31 | 1992-03-19 | Toshiba Corp | 画像形成装置 |
JP2000301534A (ja) * | 1999-02-19 | 2000-10-31 | Hitachi Chem Co Ltd | プリプレグ、金属張積層板及びこれらを用いた印刷配線板 |
TW511405B (en) * | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
US6855892B2 (en) * | 2001-09-27 | 2005-02-15 | Matsushita Electric Industrial Co., Ltd. | Insulation sheet, multi-layer wiring substrate and production processes thereof |
JP2004221417A (ja) * | 2003-01-16 | 2004-08-05 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JPWO2004086833A1 (ja) * | 2003-03-27 | 2006-06-29 | 日本ゼオン株式会社 | プリント配線板、その製造方法及び支持体付き硬化性樹脂成形体 |
JP2006041438A (ja) * | 2004-07-30 | 2006-02-09 | Shinko Electric Ind Co Ltd | 半導体チップ内蔵基板及びその製造方法 |
JP4792749B2 (ja) * | 2005-01-14 | 2011-10-12 | 大日本印刷株式会社 | 電子部品内蔵プリント配線板の製造方法 |
JP4718192B2 (ja) | 2005-01-17 | 2011-07-06 | 新光電気工業株式会社 | リーダ/ライタ |
JP3914239B2 (ja) * | 2005-03-15 | 2007-05-16 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
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TW200818440A (en) | 2008-04-16 |
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KR20080033069A (ko) | 2008-04-16 |
US7994431B2 (en) | 2011-08-09 |
JP2008098366A (ja) | 2008-04-24 |
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