CN106920779B - 柔性半导体封装件的组合结构及其运输方法 - Google Patents

柔性半导体封装件的组合结构及其运输方法 Download PDF

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CN106920779B
CN106920779B CN201710137708.5A CN201710137708A CN106920779B CN 106920779 B CN106920779 B CN 106920779B CN 201710137708 A CN201710137708 A CN 201710137708A CN 106920779 B CN106920779 B CN 106920779B
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semiconductor packaging
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CN106920779A (zh
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杜茂华
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明的示例性实施例公开了一种柔性半导体封装件的组合结构及柔性半导体封装件的运输方法，所述柔性半导体封装件的组合结构包括：柔性半导体封装件；胶接件，设置在柔性半导体封装件上；刚性基板，设置在胶接件上。通过在柔性半导体封装件表面增加刚性基板，使可变形的柔性半导体封装件得到保护，从而避免由于在加工和运输过程中柔性半导体封装件的变形，导致的柔性半导体封装件失效，进而降低成品的良率。

Description

柔性半导体封装件的组合结构及其运输方法
技术领域
本发明涉及一种柔性半导体封装件的组合结构和柔性半导体封装件的运输方法。
背景技术
可穿戴电子装置是穿戴在例如人体(例如，腕部、颈部、头部等)上使用的电子装置。因为可穿戴电子装置具有很大便携性，所以可穿戴电子装置的使用正在增加。而人体的大部分表面是不平坦的，因此要求电子装置具有较大的灵活性，从而能够在一定程度上适应不同的工作环境，以满足客户对于可穿戴电子装置的形变的要求。然而由于在可穿戴电子装置中使用的半导体封装件是柔性的，在组装工艺和运输过程中半导体封装件很容易发生变形，进而导致半导体封装件失效，降低成品的良率。
发明内容
本发明的示例性实施例公开了一种柔性半导体封装件的组合结构，所述柔性半导体封装件的组合结构包括：柔性半导体封装件；胶接件，设置在柔性半导体封装件上；刚性基板，设置在胶接件上。
在本发明的示例性实施例中，柔性半导体封装件包括：柔性基底；至少一个芯片，设置在柔性基底的上表面上；导电件，将至少一个芯片电连接到柔性基底；柔性包封件，设置在柔性基底的上表面和下表面上，以保护至少一个芯片和导电件；焊料凸起，位于柔性基底的下表面上，穿过柔性包封件连接到柔性基底。
在本发明的示例性实施例中，柔性半导体封装件能够向内或向外弯曲。
在本发明的示例性实施例中，柔性包封件中二氧化硅的含量按重量百分比低于50％，弹性模量低于2GPa，延伸率大于10％。
在本发明的示例性实施例中，柔性基底包含PI、PET、PEN、PEEK、玻璃纤维增强环氧树脂以及半固化片。
在本发明的示例性实施例中，刚性基板为透明玻璃基板。
本发明的示例性实施例公开了一种运输方式，所述运输方式包括：将柔性半导体封装件通过胶接件贴合到刚性基板上；在板级组装后，通过紫外光或激光照射等的拆胶方法将刚性基板与柔性半导体封装件分离。
根据本发明的示例性实施例意在提供一种低成本的、高密度、高传输带宽、高散热、高可靠性的封装堆叠结构。通过在柔性半导体封装件表面增加刚性基板，使可变形的柔性半导体封装件在组装工艺中得到保护，从而避免由于在加工和运输过程中柔性半导体封装件很容易发生变形，导致的封装件失效，进而降低成品的良率。
附图说明
图1是示出根据本发明的示例性实施例的柔性半导体封装件的组合结构的剖视图。
图2是示出根据本发明的示例性实施例的柔性半导体封装件的剖视图。
图3是示出根据本发明的示例性实施例的柔性半导体封装件的剖视图。
具体实施方式
在下文中将参照附图更充分地描述各种示例实施例，附图中示出了一些示例实施例。然而，本发明构思的示例实施例可以以许多不同的形式来实现并且不应该被解释为受限于这里所阐述的示例实施例。在附图中，为了清晰起见，可以夸大层和区域的尺寸和相对尺寸。此外，为了提高清楚性和简便性，可以省略对公知功能和结构的描述。
在本发明的实施例中，将胶接件设置(例如，贴合)在柔性半导体封装件上；将刚性基板设置在胶接件上以使刚性基板通过胶接件贴合到柔性半导体封装件上，结果，得到柔性半导体封装件的组合结构；当完成传送和/或组装工艺之后，通过拆胶方法来使柔性半导体封装件的组合结构中的刚性基板与柔性半导体封装件分离。
根据本发明的实施例的柔性半导体封装件的组合结构可以临时地保护柔性半导体封装件在运送和组装过程中不会发生过度的弯曲和变形，并且降低柔性半导体封装件损坏的危险，从而利于组装和运输。
当完成传送和组装工艺之后，通过诸如紫外光或激光照射等的拆胶方法来使刚性基板与柔性半导体封装件分离。由于柔性半导体封装件主要由低模量材料组成，所以与刚性基板分离后的柔性半导体封装件可以根据需要进行弯曲变形。因此，可以通过在柔性半导体封装件的表面增加刚性基板，使柔性半导体封装件在组装工艺中得到保护，以提高良率和出货的稳定性。
在下文中，将参照附图1来详细地描述柔性半导体封装件的组合结构1000的示例。
图1是示出根据本发明的示例性实施例的柔性半导体封装件的组合结构1000的剖视图。
根据本发明的示例性实施例，柔性半导体封装件的组合结构1000包括柔性半导体封装件100、胶接件110和刚性基板120。
柔性半导体封装件100可以包括基底10、芯片20、导电件30、包封件40和焊料凸起50。柔性半导体封装件100可以用于任意可穿戴电子装置，例如，诸如智能手表或手环等的腕戴电子装置、项链型电子装置、眼镜型电子装置等。
基底10可以是本领域常用的柔性基底，例如，基底10可以包括诸如PI、PEN、PEEK、PET、玻璃纤维增强环氧树脂以及半固化片(prepreg)的材料，但本发明不限于此。基底10可以具有小于200μm的厚度以保证半导体封装件的柔性和良好的曲面贴合性能。
芯片20设置在基底10上，芯片20的表面上可以具有芯片焊盘。芯片20可以通过芯片焊盘和导电件30电连接到基底10。单个芯片20被构造为具有比基底10的面积的一半小的面积以及具有小于200μm且大于10μm的厚度，以在柔性半导体封装件的弯曲过程中实现芯片20和基底10的良好的贴合。
导电件30将芯片20电连接到基底10。导电件30可以是具有凹部和凸部的弯曲形状的键合引线。如此，具有弯曲形状的导电件30可以在柔性半导体封装件100向内或向外弯曲时不会由于过度拉长而断裂，从而提高柔性半导体封装件100的可靠性。在另一示例性实施例中，导电件30可以是诸如焊料凸起或铜凸起的凸起等，芯片20通过芯片焊盘和导电件30以倒装方式连接到基底10。在这种情况下，导电件30可以包括导电环氧树脂。
包封件40可以设置在基底10的上表面上并且还可以设置在基底10的下表面上，即，包封件40可以设置在基底10的两侧处以保护导电件30和芯片20并降低芯片损坏的风险。包封件40设置在基底10的两侧上以实现应力平衡，从而使热膨胀系数不匹配导致的内应力最小化以确保柔性半导体封装件100的柔性。在示例性实施例中，柔性半导体封装件100可以如图2中示出的向外弯曲成凸形，也可以如图3中示出的向内弯曲成凹形。如图2和图3中示出的，在柔性半导体封装件100处于弯曲的状态时，芯片表面可以不处于水平平面上。由于具有柔性的基底和柔性的包封件的柔性半导体封装件100可以根据需要进行弯曲变形，因此可以改善曲面贴合性能。
包封件40可以是本领域常用的柔性包封件，优选地，包封件40可以包括SiO2含量小于50wt％，并且弹性模量小于2GPa、延伸率大于10％的低模量包封材料。在另一示例性实施例中，包封件40可以是塑封料。另外，包封件40可以使芯片20免受外部环境(例如，湿气和/或空气)的影响。
焊料凸起50可以设置在基底10的下表面上并且穿过柔性的包封件40连接到基底10。可以利用本领域常用方法形成多个焊料凸起50。在本示例性实施例中，焊料凸起50可以是焊球。
胶接件110设置在位于基底10的上表面上的包封件40上。在示例性实施例中，胶接件110可以是诸如光敏胶(UV glue)的光学胶接件。当胶接件110是光敏胶时，可以通过紫外光或激光照射来降低光敏胶的粘结力以使刚性基板120与柔性半导体封装件100分离。
刚性基板120可以是透明的刚性材料，例如，包括不吸收紫外线的SiO2、硼酸盐或磷酸盐等的透明玻璃。刚性基板120可以临时地保护柔性半导体封装件100在组装过程中不会发生过度的弯曲和变形，因此有利于组装。当完成传送和板级组装之后，通过紫外线或激光照射等的拆胶方法来将刚性基板120与柔性半导体封装件100分离，从而可以避免由于在加工和运输过程中由于柔性半导体封装件变形导致的柔性半导体封装件失效，进而提高成品的良率。因此，可以通过在柔性半导体封装件表面增加刚性基板，使柔性半导体封装件在组装工艺中得到保护，以提高良率和出货的稳定性。
虽然已经参照附图描述了一个或更多个实施例，但是本领域的普通技术人员将理解的是，在不脱离由权利要求限定的精神和范围的情况下，可以在形式和细节上进行各种改变。

Claims (6)

1.一种柔性半导体封装件的组合结构，所述柔性半导体封装件的组合结构包括：
柔性半导体封装件；
胶接件，设置在柔性半导体封装件上；
刚性基板，设置在胶接件上，所述刚性基板为透明玻璃基板，
胶接件是光敏胶并且在被紫外光或激光照射的情况下使刚性基板与柔性半导体封装件分离。
2.根据权利要求1所述的柔性半导体封装件的组合结构，所述柔性半导体封装件包括：
柔性基底；
至少一个芯片，设置在柔性基底的上表面上；
导电件，将所述至少一个芯片电连接到柔性基底；
柔性包封件，设置在柔性基底的上表面和下表面上，以保护所述至少一个芯片和导电件；
焊料凸起，位于柔性基底的下表面上，穿过柔性包封件连接到柔性基底。
3.根据权利要求1所述的柔性半导体封装件的组合结构，所述柔性半导体封装件能够向内或向外弯曲。
4.根据权利要求2所述的柔性半导体封装件的组合结构，所述柔性包封件中二氧化硅的含量按重量百分比低于50％，弹性模量低于2GPa，延伸率大于10％。
5.根据权利要求2所述的柔性半导体封装件的组合结构，所述柔性基底包含PI、PET、PEN、PEEK、玻璃纤维增强环氧树脂以及半固化片。
6.一种运输柔性半导体封装件的方法，所述方法包括：
将柔性半导体封装件通过作为胶接件的光敏胶贴合到刚性基板上；
在组装后，通过紫外光或激光照射使刚性基板与柔性半导体封装件分离，
其中，所述刚性基板为透明玻璃基板。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2566030B (en) 2017-08-30 2023-01-04 Pragmatic Printing Ltd Integrated circuit handling process and apparatus
CN108847412B (zh) * 2018-06-01 2019-05-21 清华大学 基于系统级封装的柔性电子器件
CN109192660A (zh) * 2018-09-12 2019-01-11 三星半导体(中国)研究开发有限公司 柔性封装件
US11574820B2 (en) * 2020-06-08 2023-02-07 Micron Technology, Inc. Semiconductor devices with flexible reinforcement structure

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3234666B2 (ja) 1993-03-02 2001-12-04 株式会社東芝 半導体集積回路装置
US6027958A (en) 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
JPH1154658A (ja) 1997-07-30 1999-02-26 Hitachi Ltd 半導体装置及びその製造方法並びにフレーム構造体
US5901041A (en) 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
US6111324A (en) * 1998-02-05 2000-08-29 Asat, Limited Integrated carrier ring/stiffener and method for manufacturing a flexible integrated circuit package
TW460927B (en) 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
KR20020057358A (ko) * 2001-01-04 2002-07-11 마이클 디. 오브라이언 멀티칩 모듈 패키지 및 제조방법
EP1256982A1 (fr) * 2001-05-11 2002-11-13 Valtronic S.A. Module électronique et son procede d'assemblage
US7128442B2 (en) 2003-05-09 2006-10-31 Kian Shin Lee Illumination unit with a solid-state light generating source, a flexible substrate, and a flexible and optically transparent encapsulant
TWM277958U (en) * 2004-12-31 2005-10-11 Ind Tech Res Inst An flexible displaying device for electronic information includes a device housing
CN100481431C (zh) * 2006-08-15 2009-04-22 南茂科技股份有限公司 减少软板形变的薄膜覆晶封装构造
CN101290921A (zh) * 2007-04-17 2008-10-22 南茂科技股份有限公司 防止薄膜变形的薄膜覆晶封装基板
US8691702B2 (en) 2011-03-14 2014-04-08 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
CN202153541U (zh) * 2011-08-18 2012-02-29 京东方科技集团股份有限公司 一种柔性显示器
CN103579128B (zh) * 2012-07-26 2016-12-21 碁鼎科技秦皇岛有限公司 芯片封装基板、芯片封装结构及其制作方法
TWI492373B (zh) * 2012-08-09 2015-07-11 Au Optronics Corp 可撓式顯示模組的製作方法
CN103354239B (zh) * 2013-07-16 2017-02-08 南昌欧菲光电技术有限公司 影像感测器组件
KR101565016B1 (ko) 2013-10-22 2015-11-03 앰코 테크놀로지 코리아 주식회사 휨 개선을 위한 반도체 패키지 구조 및 방법
KR101906695B1 (ko) * 2014-03-07 2018-10-10 플라즈마-썸, 엘엘씨 반도체 웨이퍼를 플라즈마 다이싱하기 위한 방법 및 장치
KR102222484B1 (ko) * 2014-05-27 2021-03-04 에스케이하이닉스 주식회사 윙부를 가지는 플렉시블 적층 패키지
CN105336875B (zh) 2014-07-10 2017-10-13 上海和辉光电有限公司 柔性显示器件及其离型方法
CN104167429B (zh) * 2014-08-01 2017-05-31 京东方科技集团股份有限公司 一种柔性显示面板及其制备方法、显示装置
KR102284652B1 (ko) 2014-08-28 2021-08-02 삼성전자 주식회사 반도체 패키지
KR20160036702A (ko) 2014-09-25 2016-04-05 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9778688B2 (en) * 2014-11-12 2017-10-03 Intel Corporation Flexible system-in-package solutions for wearable devices
JP2016141044A (ja) * 2015-02-02 2016-08-08 三菱化学株式会社 フレキシブル基板及びその製造方法

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