CN109192660A - 柔性封装件 - Google Patents

柔性封装件 Download PDF

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Publication number
CN109192660A
CN109192660A CN201811060732.4A CN201811060732A CN109192660A CN 109192660 A CN109192660 A CN 109192660A CN 201811060732 A CN201811060732 A CN 201811060732A CN 109192660 A CN109192660 A CN 109192660A
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China
Prior art keywords
flexible
package part
chip
flexible package
buffer layer
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Pending
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CN201811060732.4A
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English (en)
Inventor
杜茂华
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Application filed by Samsung Semiconductor China R&D Co Ltd, Samsung Electronics Co Ltd filed Critical Samsung Semiconductor China R&D Co Ltd
Priority to CN201811060732.4A priority Critical patent/CN109192660A/zh
Priority to KR1020180167892A priority patent/KR20200030430A/ko
Publication of CN109192660A publication Critical patent/CN109192660A/zh
Priority to US16/407,618 priority patent/US20200083128A1/en
Pending legal-status Critical Current

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Abstract

本发明提供一种柔性封装件，该柔性封装件包括：柔性基板；至少一个芯片，贴合在柔性基板的上表面上；导电件，电连接所述至少一个芯片与柔性基板；缓冲层，覆盖所述至少一个芯片的侧表面；以及柔性包封件，封装柔性基板和所述至少一个芯片，其中，缓冲层的延伸率大于柔性包封件的延伸率。根据本发明的示例性实施例的柔性封装件具有改善的可变形性，并且可以防止在其弯曲时出现断裂。

Description

柔性封装件
技术领域
本发明适用于半导体封装领域，具体地讲，涉及一种柔性封装件。
背景技术
可穿戴电子装置是穿戴在例如人体(例如，腕部、颈部、头部等)上的电子装置，目前正在广泛应用。由于人体的皮肤具有一定轮廓而不是平坦的，所以具有刚性封装件的可穿戴电子装置不适合佩戴在人体上。因此，在可穿戴电子装置中通常需要使用柔性封装件。
在现有的柔性封装技术中，通过使用高延伸率的包封件(通常为诸如环氧树脂模塑料(EMC)的塑封料)，使柔性封装件达到可弯曲效果，但是由于芯片是刚性体，所以芯片与密封芯片的塑封料的交接区形成了变形集中区，容易在弯曲时发生断裂。如果大幅增加塑封料的延伸率，则会提高塑封料的热膨胀系数(CTE)，从而降低封装件的可靠性。
发明内容
本发明的示例性实施例的一个目的在于：在不减小芯片保护性能的情况下，提供一种具有优异的弯曲性能的柔性封装件。
根据一方面，本发明的示例性实施例提供了一种柔性封装件，该柔性封装件包括：柔性基板；至少一个芯片，贴合在柔性基板的上表面上；导电件，电连接所述至少一个芯片与柔性基板；缓冲层，覆盖所述至少一个芯片的侧表面；以及柔性包封件，封装柔性基板和所述至少一个芯片，其中，缓冲层的延伸率大于柔性包封件的延伸率。
根据本发明的示例性实施例，缓冲层的延伸率可以大于100％。
根据本发明的示例性实施例，缓冲层可以覆盖所述至少一个芯片中的每个芯片的侧表面。
根据本发明的示例性实施例，缓冲层可以完全覆盖每个芯片的所有侧表面，且缓冲层的高度与每个芯片的高度相同。
根据本发明的示例性实施例，缓冲层在与柔性基板的延伸方向平行的方向上的厚度可以小于300μm。
根据本发明的示例性实施例，缓冲层的材料可以为硅胶。
根据本发明的示例性实施例，柔性包封件可以设置在柔性基板的上方和下方。
根据本发明的示例性实施例，柔性包封件的材料可以为环氧树脂模塑料，在环氧树脂模塑料中二氧化硅的含量按重量百分比计低于50％，环氧树脂模塑料具有低于2GPa的弹性模量和大于10％的延伸率。
根据本发明的示例性实施例，所述至少一个芯片中的每个芯片的厚度可以小于200μm，且每个芯片的面积可以小于柔性封装件的面积的50％。
根据本发明的示例性实施例，柔性封装件可以是可弯曲的。
根据本发明的示例性实施例，柔性基板的材料可以为PI、PET、PEN、PEEK或半固化片。
根据本发明的示例性实施例，导电件可以为焊线、凸点或导电胶。
根据本发明的示例性实施例的柔性封装件可以具有改善的可变形性和可靠性，和/或可以防止在其弯曲时出现断裂。
附图说明
通过下面参照附图结合示例性实施例进行的详细描述，本发明的其他特征将会变得更加清楚，其中：
图1是示出现有技术中的柔性封装件的剖视图；
图2是示出现有技术中的柔性封装件的应力分布图；
图3是示出现有技术中的柔性封装件中出现断裂的截面图；
图4是示出根据本发明的示例性实施例的柔性封装件的剖视图；
图5是示出根据本发明的另一个示例性实施例的柔性封装件的剖视图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。
在附图中，为了清晰起见，会夸大层、膜、面板、区域等的厚度。在整个说明书中同样的附图标记表示相同的元件。将理解，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是示出现有技术中的柔性封装件100的剖视图。图2是示出现有技术中的柔性封装件100的应力分布图。图3是示出现有技术中的柔性封装件100中出现断裂的截面图。
在现有技术的柔性封装件100中，如图1所示，芯片20被固定在基板10上，并通过导电件30(例如，焊线)与基板10连接，芯片20由包封件40保护，包封件40通常为塑封料并且具有低模量和高延展性的特点。在弯曲时，包封件40由于具有高延展性而容易弯曲，但是芯片20是刚性体而难以变形，因此在芯片20和包封件40的交界处形成了应力集中区，如图2中A区所示；在受到过量弯曲时，在芯片20和包封件40的交界处会发生撕裂伤，如图3中B区所示，最终导致柔性封装件100整体断裂。
因此，现有技术面临的问题是：期望提高塑封料的延伸率，使其能抗更高的变形且能够提高封装件的弯曲能力，然而，过度提高塑封料的延伸率会降低塑封料的模量并导致CTE过高，造成芯片保护不足以及由于CTE过量而引起的热匹配失效，形成了技术矛盾。
图4是示出根据本发明的示例性实施例的柔性封装件400的剖视图。
根据本发明的示例性实施例的柔性封装件400可以包括基板10、芯片20、导电件30、包封件40、焊球50和缓冲层60。柔性封装件400可以用于任意可穿戴电子装置，例如，智能手表或手环等的腕戴电子装置、项链型电子装置、眼镜型电子装置等。
参照图4，在根据本发明的示例性实施例的柔性封装件400中，至少一个芯片20可以贴合在基板10的上表面上，导电件30可以连接所述至少一个芯片20与基板10，缓冲层60可以覆盖所述至少一个芯片20的侧表面，包封件40可以设置在基板10的上方和下方并且包封基板10和所述至少一个芯片20，其中，缓冲层60的延伸率可以大于包封件40的延伸率，并且缓冲层60的延伸率可以大于100％。
以下将详细描述根据本发明的示例性实施例的柔性封装件400中的各个组件。
在本发明的示例性实施例中，缓冲层60可以覆盖或围绕所述至少一个芯片20的至少一个侧表面，例如，完全覆盖每个芯片20的所有侧表面。可选地，不在每个芯片20的上表面或下表面设置缓冲层60，但不限于此。在与基板10垂直的竖直方向上，缓冲层60的高度可以与每个芯片20的高度相同。在与基板10的延伸方向平行的方向上，缓冲层60的厚度可以小于300μm。缓冲层60的延伸率可以大于包封件40的延伸率，优选地，缓冲层60的延伸率大于100％。例如，缓冲层60的材料可以为硅胶，但不限于此。可选择地，缓冲层60的材料可以是具有较高延伸率的其他材料。
因此，超高延伸率的缓冲层60可覆盖在每个芯片20的周围(例如，每个芯片20的侧表面)，即，可在每个芯片20与包封件40之间设置缓冲层60，从而在使柔性封装件400高弯曲变形时，缓冲层60由于其超高延伸率(例如>100％)可以承受高应变，可以防止在芯片20与包封件40之间发生断裂。
基板10通常可以是柔性基板，例如，基板10的材料可以为PI、PEN、PEEK、PET或半固化片(prepreg)，但本发明不限于此。基板10可以具有小于200μm的厚度以保证柔性封装件400的柔性和良好的曲面贴合性能。
至少一个芯片20可以贴合在基板10的上表面上，每个芯片20的表面可以具有焊盘(未示出)。如图4所示，芯片20可以通过芯片上的焊盘和导电件30(例如，焊线)电连接到基板10。当芯片20为多个时，多个芯片20可以具有相同的尺寸或不同的尺寸。每个芯片20的厚度可以小于200μm。在与基板10延伸的平面平行的平面(例如，水平平面)上，每个芯片20的面积可以小于柔性封装件400的面积的50％，以在柔性封装件400的弯曲过程中实现芯片20和基板10的良好的贴合，从而较好地实现柔性封装件400的弯曲。可选地，每个芯片20的面积可以小于基板10的面积的50％。
导电件30可以为焊线、凸点或导电胶。如图4所示，当导电件30为具有凹部和凸部的弯曲形状的焊线时，具有弯曲形状的导电件30可以在柔性封装件400向内或向外弯曲时不会由于过度拉长而断裂，从而提高柔性封装件400的可靠性。在另一示例性实施例中，导电件30可以是诸如焊球或凸起的凸点等(未示出)，每个芯片20可通过芯片上的焊盘和诸如焊球或凸点的导电件30以倒装方式连接到基板10。在另一示例性实施例中，导电件30以导电胶的形式电连接每个芯片20和基板10。
包封件40可以设置在基板10的上方和下方且封装基板10和至少一个芯片20，例如，包封件40可以设置在基板10的上表面上并且还可以设置在基板10的下表面上。即，包封件40可以设置在基板10的上下两侧上，以封装并保护基板10、芯片20、导电件30和缓冲层60，并且降低芯片20损坏的风险。包封件40可以设置在基板10的上下两侧上以实现应力平衡，从而使热膨胀系数不匹配导致的内应力最小化，以确保柔性封装件400的柔性。在本示例性实施例中，包封件40可以在基板的上下两侧封装基板10，而暴露基板10的左右两侧。可选择地，包封件40可以完全密封基板10，即，密封基板10的上下两侧和左右两侧。
包封件40通常可以是柔性包封件。柔性包封件的材料可以为诸如环氧树脂模塑料(EMC)的塑封料。优选地，在环氧树脂模塑料中的二氧化硅的含量按重量百分比计低于50％，环氧树脂模塑料的弹性模量低于2GPa且其延伸率大于10％。另外，包封件40可以阻挡外部的湿气或空气，使芯片20免受外部环境的影响。
多个焊球50可以设置在基板10的下表面上并且穿过柔性包封件40连接到基板10，从而可以与外部装置实现连接。
在示例性实施例中，柔性封装件400是可弯曲的。具体地，柔性封装件400可以如图4中示出的向外(即，向下)弯曲成凸形。
图5是示出根据本发明的另一个示例性实施例的柔性封装件500的剖视图。在图5中，柔性封装件500可以向内(即，向上)弯曲成凹形。除了与图4中的柔性封装件400的弯曲形状不同之外，图5中的柔性封装件500具有与图4中的柔性封装件400相同的元件，这里将不再进行重复的描述。
如图4和图5中示出的，柔性封装件400或500可以向外弯曲成凸形或向内弯曲成凹形。在柔性封装件400或500处于弯曲的状态时，每个芯片20的表面可以不处于水平平面上。根据本发明的示例性实施例的具有柔性基板10和柔性包封件40的柔性封装件400或500可以根据需要进行弯曲变形，并且可以具有改善的曲面贴合性能，而不会发生柔性封装件400或500的断裂。
根据本发明的示例性实施例的制造图4或图5所示的柔性封装件400或500的方法可以包括：准备基板10；以预定间隔将至少一个芯片20贴合在基板10的上表面；在完成贴装后，在每个芯片20的四周(即，所有侧表面)通过点胶涂覆缓冲材料(例如，硅胶)，使涂覆的缓冲材料具有与每个芯片20相同的高度且具有小于300μm的厚度；通过加热或紫外光固化的方式来固化缓冲材料，从而形成缓冲层60；通过导电件(例如，焊线)30将每个芯片20连接到基板10；将包封件40设置在基板10的上方和下方，并且使包封件40包封基板10、芯片20和导电件30。之后，采用本领域常用的弯曲工艺或技术，可以将柔性封装件向外弯曲形成如图4所示的柔性封装件400；可选择地，可以将柔性封装件向内弯曲形成如图5所示的柔性封装件500。在另一个示例性实施例中，柔性封装件可以是根据人体的皮肤或佩戴的位置而变形的柔性封装件，并不限于图4或图5所示的弯曲形状和弧度。
在本发明的示例性实施例中，参照图4和图5，通过使用具有柔性的基板10、具有柔性的包封件(例如，EMC)40、以及在至少一个芯片20与包封件40之间设置的具有超高延伸率的缓冲层(例如，硅胶)60，可以形成具有优异的弯曲性能的柔性封装件400或500。可选地，包封件40可设置在基板10的上下两侧上以实现应力平衡，从而使由热膨胀系数不匹配导致的内应力最小化，以确保柔性封装件400或500的柔性。此外，优选地，包封件40可以为具有柔性的环氧树脂模塑料，在环氧树脂模塑料中二氧化硅的含量按重量百分比计低于50％，而且环氧树脂模塑料的弹性模量低于2GPa且其延伸率大于10％。此外，缓冲层60的延伸率可以大于100％且大于包封件40的延伸率，从而通过具有超高延伸率的缓冲层60在芯片20与包封件40的交界处形成过渡区，防止柔性封装件400或500断裂并提高柔性封装件400或500的可变形性。
虽然已经参照附图描述了一个或更多个实施例，但是本领域的普通技术人员将理解的是，在不脱离由权利要求限定的精神和范围的情况下，可以在形式和细节上进行各种改变。

Claims (10)

1.一种柔性封装件，其特征在于，所述柔性封装件包括：
柔性基板；
至少一个芯片，贴合在柔性基板的上表面上；
导电件，电连接所述至少一个芯片与柔性基板；
缓冲层，覆盖所述至少一个芯片的侧表面；以及
柔性包封件，封装柔性基板和所述至少一个芯片，
其中，缓冲层的延伸率大于柔性包封件的延伸率。
2.根据权利要求1所述的柔性封装件，其特征在于，缓冲层的延伸率大于100％。
3.根据权利要求1所述的柔性封装件，其特征在于，缓冲层覆盖所述至少一个芯片中的每个芯片的侧表面。
4.根据权利要求3所述的柔性封装件，其特征在于，缓冲层完全覆盖每个芯片的所有侧表面，且缓冲层的高度与每个芯片的高度相同。
5.根据权利要求1所述的柔性封装件，其特征在于，缓冲层在与柔性基板的延伸方向平行的方向上的厚度小于300μm。
6.根据权利要求1所述的柔性封装件，其特征在于，缓冲层的材料为硅胶。
7.根据权利要求1所述的柔性封装件，其特征在于，柔性包封件设置在柔性基板的上方和下方。
8.根据权利要求1所述的柔性封装件，其特征在于，柔性包封件的材料为环氧树脂模塑料，在环氧树脂模塑料中二氧化硅的含量按重量百分比计低于50％，环氧树脂模塑料具有低于2GPa的弹性模量和大于10％的延伸率。
9.根据权利要求1所述的柔性封装件，其特征在于，所述至少一个芯片中的每个芯片的厚度小于200μm，且每个芯片的面积小于柔性封装件的面积的50％。
10.根据权利要求1所述的柔性封装件，其特征在于，柔性封装件是可弯曲的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109887941A (zh) * 2019-02-20 2019-06-14 上海奕瑞光电子科技股份有限公司 柔性x射线探测器

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1032285A (ja) * 1996-07-17 1998-02-03 Hitachi Ltd 折り曲げ可能な配線基板、半導体装置およびその製造方法
CN1210621A (zh) * 1996-12-04 1999-03-10 精工爱普生株式会社 电子部件和半导体装置、其制造方法和装配方法、电路基板与电子设备
US6169328B1 (en) * 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US20040163843A1 (en) * 2003-02-22 2004-08-26 Dong-Kil Shin Multi-chip package with soft element and method of manufacturing the same
CN1955985A (zh) * 2005-10-28 2007-05-02 富士通株式会社 Rfid标签和rfid标签的制造方法
CN101114621A (zh) * 2006-07-24 2008-01-30 力成科技股份有限公司 集成电路封装构造及其抗翘曲基板
WO2009075574A1 (en) * 2007-12-10 2009-06-18 Polymer Vision Limited An electronic device comprising a flexible area with a specific bending region
CN101826495A (zh) * 2009-03-06 2010-09-08 华东科技股份有限公司 窗口型半导体封装构造
CN105810598A (zh) * 2016-04-05 2016-07-27 华中科技大学 一种可拉伸柔性电子器件的制备方法及产品
CN106488643A (zh) * 2015-08-31 2017-03-08 苹果公司 具有阻尼层的印刷电路板组件
CN106783813A (zh) * 2015-11-24 2017-05-31 爱思开海力士有限公司 包括芯片的柔性封装
CN206212410U (zh) * 2016-10-18 2017-05-31 常州瑞讯电子有限公司 带缓冲区的柔性电路板
CN106920779A (zh) * 2017-03-09 2017-07-04 三星半导体(中国)研究开发有限公司 柔性半导体封装件的组合结构及其运输方法
US20170231089A1 (en) * 2014-09-29 2017-08-10 Imec Vzw Smart textile product and method for fabricating the same
CN107210236A (zh) * 2015-02-06 2017-09-26 旭硝子株式会社 膜、其制造方法以及使用该膜的半导体元件的制造方法

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6169328B1 (en) * 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
JPH1032285A (ja) * 1996-07-17 1998-02-03 Hitachi Ltd 折り曲げ可能な配線基板、半導体装置およびその製造方法
CN1210621A (zh) * 1996-12-04 1999-03-10 精工爱普生株式会社 电子部件和半导体装置、其制造方法和装配方法、电路基板与电子设备
US20040163843A1 (en) * 2003-02-22 2004-08-26 Dong-Kil Shin Multi-chip package with soft element and method of manufacturing the same
CN1955985A (zh) * 2005-10-28 2007-05-02 富士通株式会社 Rfid标签和rfid标签的制造方法
CN101114621A (zh) * 2006-07-24 2008-01-30 力成科技股份有限公司 集成电路封装构造及其抗翘曲基板
WO2009075574A1 (en) * 2007-12-10 2009-06-18 Polymer Vision Limited An electronic device comprising a flexible area with a specific bending region
CN101826495A (zh) * 2009-03-06 2010-09-08 华东科技股份有限公司 窗口型半导体封装构造
US20170231089A1 (en) * 2014-09-29 2017-08-10 Imec Vzw Smart textile product and method for fabricating the same
CN107210236A (zh) * 2015-02-06 2017-09-26 旭硝子株式会社 膜、其制造方法以及使用该膜的半导体元件的制造方法
CN106488643A (zh) * 2015-08-31 2017-03-08 苹果公司 具有阻尼层的印刷电路板组件
CN106783813A (zh) * 2015-11-24 2017-05-31 爱思开海力士有限公司 包括芯片的柔性封装
CN105810598A (zh) * 2016-04-05 2016-07-27 华中科技大学 一种可拉伸柔性电子器件的制备方法及产品
CN206212410U (zh) * 2016-10-18 2017-05-31 常州瑞讯电子有限公司 带缓冲区的柔性电路板
CN106920779A (zh) * 2017-03-09 2017-07-04 三星半导体(中国)研究开发有限公司 柔性半导体封装件的组合结构及其运输方法

Cited By (1)

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CN109887941A (zh) * 2019-02-20 2019-06-14 上海奕瑞光电子科技股份有限公司 柔性x射线探测器

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