JP5795196B2 - 半導体パッケージ - Google Patents
半導体パッケージInfo
- Publication number
- JP5795196B2 JP5795196B2 JP2011129230A JP2011129230A JP5795196B2 JP 5795196 B2 JP5795196 B2 JP 5795196B2 JP 2011129230 A JP2011129230 A JP 2011129230A JP 2011129230 A JP2011129230 A JP 2011129230A JP 5795196 B2 JP5795196 B2 JP 5795196B2
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- Japan
- Prior art keywords
- wiring pattern
- package
- recognition mark
- connection
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
以下、一実施形態を図1〜図7に従って説明する。なお、以下の説明では、POP構造の半導体装置70(図4参照)のうち、被搭載側の半導体パッケージを下側パッケージ1と称し、搭載側の半導体パッケージを上側パッケージ50と称する。
図1(b)に示すように、下側パッケージ1は、配線基板2と、その配線基板2にフリップチップ実装された半導体素子3と、それら配線基板2と半導体素子3との隙間を充填するように設けられたアンダーフィル樹脂4とを有している。
基板本体10は、コア基板11と、そのコア基板11に積層された複数の絶縁層12,13と、その複数の絶縁層12,13に形成された配線14,15及びビア16,17等を有している。基板本体10に設けられた配線14,15及びビア16,17は、配線パターン20及び配線パターン30を電気的に接続している。なお、配線14,15及びビア16,17の材料としては、例えば銅(Cu)を用いることができる。また、絶縁層12,13の材料としては、例えばエポキシ系樹脂やポリイミド樹脂などの絶縁樹脂を用いることができる。
次に、上側パッケージ50の構造を説明する。
図3(b)に示すように、上側パッケージ50は、配線基板60と、その配線基板60にフリップチップ実装された第1の半導体素子52と、第1の半導体素子52の上に接着された第2の半導体素子53とを有している。また、上側パッケージ50は、第1の半導体素子52と配線基板60との隙間を充填するように設けられたアンダーフィル樹脂54と、第1の半導体素子52及び第2の半導体素子53等を封止する封止樹脂55とを有している。なお、図3(a)に示すように、第1の半導体素子52の平面形状は、第2の半導体素子53の平面形状よりも大きく形成されている。
次に、半導体装置70の構造について説明する。
図4に示すように、半導体装置70は、上述した下側パッケージ1と、その下側パッケージ1に積層接合された上側パッケージ50とを有している。
次に、半導体装置70(特に、下側パッケージ1)の作用について説明する。
半導体装置70は、下側パッケージ1において、接続用パッド22のうち少なくとも2つの接続用パッド22Aに、その接続用パッド22Aよりも小さい平面形状を有する認識マーク23が形成されている。これにより、下側パッケージ1と上側パッケージ50との間を接続する端子として機能する接続用パッド22Aに認識マーク機能を持たせることができ、認識マークを形成するための専用領域を別途設ける必要がなくなる。また、接続用パッド22Aの領域内に認識マーク23を形成するようにしたため、接続用パッド22Aの平面形状を、その他の接続用パッド22の平面形状と同様の円形形状とすることができる。すなわち、認識マーク機能を持つ接続用パッド22Aの平面形状を、配線の高密度化に対応可能な形状(例えば、円形形状)に形成することができる。
次に、半導体装置70の製造方法について説明する。
まず、下側パッケージ1の製造方法について説明する。図5及び図6に示す下側パッケージ1の製造方法では、図5(a)に示すコア基板11を用いる。なお、このコア基板11は、例えば銅張積層板(Copper Clad Laminated:CCL)にスルーホール10Xを形成し、スルーホール10Xの側面にめっきを施すことで両面を導通させた後、サブトラクティブ法により配線14,15を形成することによって製造される。
次に、図6(b)に示すように、絶縁層12の上面に、認識マーク23(図2参照)の形状に対応した開口部81Xを有するレジスト層81を形成する。例えば配線パターン20及び絶縁層12を覆うようにレジスト層81を形成後、フォトリソグラフィ法によりレジスト層81を露光・現像して配線パターン20の上面の一部を露出させる開口部81Xを形成する。このときの開口部81Xは、平面形状が四角形となる。なお、レジスト層81の材料としては、所望の解像性があり、耐エッチング性がある材料であれば、特に限定されない。
次いで、図6(d)に示すように、絶縁層12上に、配線パターン20の上面の一部を露出させる開口部40Xを有するソルダレジスト層40を形成する。例えば配線パターン20及び絶縁層12を覆うようにソルダレジスト層40を形成後、フォトリソグラフィ法によりソルダレジスト層40を露光・現像して配線パターン20の上面の一部を露出させる開口部40Xを形成する。ここで、開口部40Xは、上記レジスト層81の開口部81Xよりも平面形状が大きくなるように形成される。そして、この開口部40Xによって、配線パターン20の一部が半導体素子用パッド21又は接続用パッド22,22Aとしてソルダレジスト層40から露出される。さらに、このとき、接続用パッド22Aでは、上記凹部20Xの全てが開口部40Xから露出され、その凹部20Xによって認識マーク23が形成される。
まず、下側パッケージ1がキャリア(図示略)に収納され、その収納された下側パッケージ1の表面(上面)が、固定点に配設されたカメラ(図示略)により撮影される。このとき、カメラにより撮影された撮影画像が画像処理され、下側パッケージ1の接続用パッド22Aに形成された認識マーク23の位置が検出され、2つの認識マーク23の配置位置から下側パッケージ1の品種が識別される。この識別によって下側パッケージ1が所望の品種(製品)でないと判別された場合には、その下側パッケージ1に上側パッケージ50を搭載しないようにする。また、必要に応じてエラーメッセージを発する。
(1)下側パッケージ1において、接続用パッド22のうち少なくとも2つの接続用パッド22Aに、その接続用パッド22Aよりも小さい平面形状を有する認識マーク23を形成するようにした。これにより、接続用パッド22Aに認識マーク機能を持たせることができ、認識マークを形成するための専用領域を別途設ける必要がなくなる。また、接続用パッド22Aの領域内に認識マーク23を形成するようにしたため、接続用パッド22Aの平面形状を、その他の接続用パッド22の平面形状と同様の円形形状とすることができる。すなわち、認識マーク機能を持つ接続用パッド22Aの平面形状を、配線の高密度化に対応可能な形状(例えば、円形形状)に維持することができる。
なお、上記実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・上記実施形態では、認識マーク23の平面形状を四角形状にしたが、これに限定されない。例えば図8に示すように、認識マーク23の平面形状を十字状(図8(a)参照)や三角形状(図8(b)参照)となるように形成してもよい。また、認識マーク23の平面形状を円形形状(図8(c)参照)となるように形成してもよい。このとき、認識マーク23と接続用パッド22,22Aとの平面形状が共に円形形状になるため、それら認識マーク23と接続用パッド22,22Aとを判別可能な面積差となるように、認識マーク23を接続用パッド22,22Aよりも小さく形成する。以上のように、接続用パッド22,22Aと判別することのできる形状であれば、認識マーク23の形状は特に限定されず、他にも例えば認識マーク23の平面形状を×字形状や−字形状となるように形成することができる。
2 配線基板
12 絶縁層
20 配線パターン
20X 凹部
22 接続用パッド
22A 接続用パッド
23 認識マーク
50 上側パッケージ(搭載用部品)
64 外部接続端子
70 半導体装置
Claims (3)
- 最上層の配線パターンと、
前記配線パターンを被覆し、前記配線パターンの一部を接続用パッドとして露出する開口部を有するソルダレジスト層と、
半導体パッケージに搭載される搭載用部品の接続端子と電気的に接続される複数の前記接続用パッドと、
前記接続用パッドのうち少なくとも2つの第1接続用パッドの領域内に形成され、前記第1接続用パッドよりも小さい平面形状を有する認識マークと、を有し、
前記第1接続用パッドとして露出される前記配線パターンの一部に凹部又は凸部が形成されることで前記認識マークが形成されていることを特徴とする半導体パッケージ。 - 前記認識マークは、前記第1接続用パッドとして露出される前記配線パターンの一部が除去され該配線パターンの下層の絶縁層が露出されることで形成されていることを特徴とする請求項1に記載の半導体パッケージ。
- 前記第1接続用パッドの平面形状は円形形状であり、
前記認識マークの平面形状は、前記第1接続用パッドと異なる形状であることを特徴とする請求項1又は2に記載の半導体パッケージ。
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JP2011129230A JP5795196B2 (ja) | 2011-06-09 | 2011-06-09 | 半導体パッケージ |
US13/483,464 US9406620B2 (en) | 2011-06-09 | 2012-05-30 | Semiconductor package |
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JP2011129230A JP5795196B2 (ja) | 2011-06-09 | 2011-06-09 | 半導体パッケージ |
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US11131431B2 (en) | 2014-09-28 | 2021-09-28 | Jiaxing Super Lighting Electric Appliance Co., Ltd | LED tube lamp |
US9343386B2 (en) * | 2013-06-19 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment in the packaging of integrated circuits |
CN103390563B (zh) * | 2013-08-06 | 2016-03-30 | 江苏长电科技股份有限公司 | 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法 |
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