CN113496983A - 半导体封装载板及其制法与半导体封装制程 - Google Patents

半导体封装载板及其制法与半导体封装制程 Download PDF

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Publication number
CN113496983A
CN113496983A CN202110285458.6A CN202110285458A CN113496983A CN 113496983 A CN113496983 A CN 113496983A CN 202110285458 A CN202110285458 A CN 202110285458A CN 113496983 A CN113496983 A CN 113496983A
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insulating layer
layer
circuit
conductive
semiconductor package
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CN202110285458.6A
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周保宏
余俊贤
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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Abstract

一种半导体封装载板及其制法与半导体封装制程，包括：绝缘层与嵌埋于该绝缘层中相互叠设的线路层与导电柱所形成的薄型化线路结构、以及形成于该绝缘层上的支撑结构，且该支撑结构设有外露出该导电柱的穿孔，以于后续进行封装作业前，可先进行该封装载板的电性检测与筛选，以令后续封装作业不会误用到功能有瑕疵的封装载板，故能避免耗损功能正常的电子元件。

Description

半导体封装载板及其制法与半导体封装制程
技术领域
本发明有关一种半导体封装基板，尤指一种薄化产品的半导体封装载板及其制法与半导体封装制程。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。为了提高多层电路板的布线精密度，业界遂发展出一种增层技术(Build-up)，也就是在一核心板(Core board)的两表面上分别以线路增层技术交互堆叠多层的介电层及线路层，并于该介电层中开设导电盲孔(Conductive via)以供上下层线路之间电性连接。
然而，由于该核心板的厚度约30至50微米(um)，致使封装基板难以符合薄化需求，故为了满足微型化(miniaturization)的需求，发展出无核心层(coreless)的封装技术。
图1A至图1B为现有半导体封装件的制法的剖面示意图，如第TW201913906号专利公开案。
如图1A所示，提供一封装基板1，其具有线路层11及一支撑件12，该支撑件12具有多个外露部分该线路层11的开口120，且该支撑件12为绝缘板材、半导体板材或金属板材。
于后续对该封装基板1进行电性检测时，将一检测探针经由该开口120电性连接该线路层11。
如图1B所示，待确认该封装基板1的线路层11呈现正常状态后，进行封装制程，设置至少一半导体芯片10于该封装基板1上，并使该半导体芯片10电性连接该线路层11，且以一包覆层13包覆该半导体芯片10。于封装制程后，可采用化学蚀刻方式移除支撑件12。
应可理解地，当检测该封装基板1的线路层11呈现不正常的状态时，则报废该不良的封装基板1，而不会对该不良的封装基板1进行封装制程。
然而，现有半导体封装件的制法中，该支撑件12为绝缘板材、半导体板材或金属板材，故其不易形成该开口120，且该开口120的对位误差过大，致使于后续对该封装基板1进行电性检测时，该检测探针容易插错开口120而误触该线路层11，故于封装作业前针对该封装基板1进行电性检测与筛选的作业容易发生错误，造成于封装制程时(如图1B所示)，容易将功能正常的半导体芯片10接置于功能有瑕疵的封装基板1上，导致必须将原本功能正常的半导体芯片10与功能有瑕疵的封装基板1一并报废，因而大幅增加该半导体封装件1的整体制作成本。
另外，第TW I531038号专利亦配置有一具有开口的支撑载板，但其仍有开口的对位误差过大的问题。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种半导体封装载板及其制法与半导体封装制程，能降低该电子封装件的整体制作成本，且提高后续生产效率。
本发明第一方面提供一种半导体封装载板，包括：线路结构，包含：多个线路层，各具有相对的第一电性面与第二电性面；多个导电柱，各具有相对的第一端面与第二端面，并以其第二端面立设于该线路层的第一电性面上；多个绝缘层，各具有相对的第一表面与第二表面，且用以包覆该线路层与该导电柱，以令其中一侧的导电柱的第一端面外露于该绝缘层的第一表面，且令另一侧的线路层的第二电性面外露于该绝缘层的第二表面；以及支撑结构，其设于该线路结构的其中一侧的绝缘层的第一表面上，且该支撑结构形成有至少一穿孔以外露出该导电柱的第一端面，其中，该支撑结构为一感光型绝缘材，且该支撑结构为可移除抛弃式结构。
本发明第二方面提供一种半导体封装载板的制法，包括：提供一承载板；于该承载板上形成线路层与导电柱，该线路层具有相对的第一电性面与第二电性面，且该导电柱具有相对的第一端面与第二端面，其中，该线路层以其第二电性面贴覆于该承载板上，该导电柱以其第二端面立设于该线路层的第一电性面上；于该承载板上形成一具有相对的第一表面与第二表面的绝缘层，以令该绝缘层包覆该线路层与该导电柱，其中，该导电柱的第一端面外露出于该绝缘层的第一表面，该线路层的第二电性面外露出于该绝缘层的第二表面，使该绝缘层、该线路层及该导电柱形成为薄型化的线路结构；形成支撑结构于该绝缘层的第一表面上，该支撑结构为一感光型绝缘材，且该支撑结构形成有至少一穿孔以露出该导电柱的第一端面，该支撑结构为可移除抛弃式结构；以及移除该承载板，以露出该绝缘层的第二表面与该线路层的第二电性面，其中，该线路结构与该支撑结构形成为薄型化的封装载板。
前述的制法中，该支撑结构的穿孔以微影方式形成。
前述的半导体封装载板及其制法中，该支撑结构为一感光型介电材或感光型干膜。
本发明第三方面提供一种半导体封装制程，包括：提供一前述第一方面所述的半导体封装载板；将至少一电子元件结合至该绝缘层的第二表面上，以令该电子元件电性连接该线路层；形成一封装层于该绝缘层的第二表面上，以令该封装层包覆该电子元件；以及完全移除该支撑结构，以露出该绝缘层的第一表面与该导电柱的第一端面。
前述的半导体封装制程中，移除该支撑结构的方法包括有化学方式、激光、等离子、喷砂或机械研磨。
前述的半导体封装制程中，还包括于完全移除该支撑结构后，形成导电元件于该绝缘层的第一表面上，以令该导电元件电性连接该导电柱的第一端面。
由上可知，本发明的半导体封装载板及其制法与封装制程，主要借由以感光型绝缘材作为该支撑结构，以利于形成穿孔，且该穿孔的对位极为精准而无对位误差过大的问题，以于进行半导体封装作业的前，可先针对该封装载板进行电性检测作业，以先筛选出功能正常的封装载板，故相较于现有技术，本发明能避免于封装作业时误用到功能有瑕疵的封装载板，故不会发生耗损功能正常的电子元件的问题，因而能降低该电子封装件的整体制作成本，且提高后续生产效率。
此外，借由该支撑结构的暂时性刚性支撑设计，促使能尽量的薄型化该线路结构，且借由该线路结构与该支撑结构结合后的总厚度能满足一般性封装的规范要求，故除了于进行封装制程前，该封装载板不会发生翘曲现象之外，且仅需运用一般性的封装设备即能完成薄型化电子封装件的封装作业，而无需耗费巨资来修改或添购符合薄型化封装规范的封装设备。
附图说明
图1A至图1B为现有半导体封装件的制法的剖视示意图；
图2A至图2F为本发明的半导体封装载板的制法的剖视示意图；以及
图3A至图3D为图2F的后续封装制程的剖视示意图。
其中，附图标记说明如下：
1：封装基板
10：半导体芯片
11：线路层
12：支撑件
120：开口
13：包覆层
2：半导体封装载板
2a：支撑结构
2b：线路结构
20：承载板
200：板体
201：铜层
21：线路层
21a：第一电性面
21b：第二电性面
22：导电柱
22a：第一端面
22b：第二端面
23：绝缘层
23a，23a’，23a”：第一表面
23b：第二表面
260：穿孔
4：电子封装件
40：电子元件
400：导电体
41：封装层
42：导电元件
t：厚度。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2F为本发明的半导体封装载板2的制法的剖面示意图。
于本实施例中，该半导体封装载板2为无核心层(coreless)形式，其作为芯片尺寸覆晶封装(flip-chip chip scale package，简称FCCSP)用的载板。
如图2A所示，提供一承载板20，且借由图案化制程形成一线路层21于该承载板20上，该线路层21具有相对的第一电性面21a与第二电性面21b，且该线路层21以其第二电性面21b贴覆在该承载板20上，再借由图案化制程，电镀形成多个导电柱22于该线路层21上，该导电柱22具有相对的第一端面22a与第二端面22b，且该导电柱22以其第二端面22b立设于该线路层21的第一电性面21a上。
于本实施例中，该承载板20为如绝缘板、陶瓷板、铜箔基板或玻璃板等基材，但无特别限制。具体地，本实施例以铜箔基板作说明，其板体200两侧表面具有铜层201。
如图2B所示，形成一绝缘层23于该承载板20上，使该绝缘层23包覆该线路层21与该多个导电柱22，其厚度t(如图2C所示)可小于或等于60微米(um)，如20至60微米不等。
于本实施例中，该绝缘层23具有相对的第一表面23a’与第二表面23b，且该绝缘层23以其第二表面23b结合至该承载板20上。
此外，该绝缘层23以铸模方式、涂布方式或压合方式形成于该承载板20上，且形成该绝缘层23的材质为介电材料，该介电材料可为环氧树脂(Epoxy)，抑或者为铸模化合物(Molding Compound)或底层涂料(Primer)，如环氧模压树脂(Epoxy Molding Compound，简称EMC)，其中，该环氧模压树脂含有充填物(filler)，且该充填物含量为70至90wt％。
如图2C所示，移除该绝缘层23的第一表面23a’的部分材质，使该绝缘层23的第一表面23a”与该导电柱22的第一端面22a二者齐平(即共平面)，且该导电柱22的第一端面22a外露于该绝缘层23的第一表面23a”。
此外，于另一实施例中，可选择性地移除该导电柱22的第一端面22a的部分材料(如蚀刻或其它等减成制法)，以令该导电柱22的第一端面22a能凹入且低于该绝缘层23的第一表面23a”。
如图2D所示，亦可于该绝缘层23的第一表面23a”上再增设至少一线路层21、至少一导电柱22及至少一绝缘层23，以令该些线路层21(如图所示为三层)、导电柱22(如图所示为三层)及绝缘层23(如图所示为三层)作为薄型化的线路结构2b。应可理解地，薄型化的该线路结构2b可视实际需求由单层的线路层21、导电柱22及绝缘层23所构成，或由多个层的线路层21、导电柱22及绝缘层23所构成。
于本实施例中，最外侧的绝缘层23的第一表面23a与最外侧的导电柱22的第一端面22a二者齐平(即共平面)，且最外侧的导电柱22的第一端面22a外露于最外侧的绝缘层23的第一表面23a。应可理解地，该导电柱22的第一端面22a亦可设为内凹或凸出该绝缘层23的第一表面23a，亦即该导电柱22的第一端面22a可视实际需求设为齐平、或内凹、或凸出于该绝缘层23的第一表面23a。
此外，可选择性地形成一表面处理层(图未示)于最外侧的导电柱22的第一端面22a上，且令该表面处理层的表面可内凹、或齐平、或突出于最外侧的绝缘层23的第一表面23a。例如，形成该表面处理层的材质可为铜面保护剂、有机保焊剂(OrganicSolderability Preservative，简称OSP)、电镀镍钯金、化学镍钯金(ENEPIG)、电镀镍金(Ni/Au)、镀锡、镀银或上述组合等的其中一者。
如图2E所示，形成一绝缘材的支撑结构2a于该线路结构2b的第一表面23a上，且该支撑结构2a为可移除抛弃式结构。
于本实施例中，该支撑结构2a可由感光型绝缘材、感光型干膜、或环氧树脂基材，如双马来酰亚胺三嗪(Bismaleimide Triazine，简称BT)、FR-4、FR-5等绝缘材(其中以感光型绝缘材为最佳的选择)，经由例如以铸模方式、涂布方式或压合方式形成于该绝缘层23的第一表面23a上。
此外，该支撑结构2a上相对于该导电柱22的部位形成有至少一穿孔260，以外露出最外侧的导电柱22的第一端面22a(或其上的表面处理层)。于本实施例中，该穿孔260可借由曝光显影、或激光、或等离子、或喷砂等方式形成。
如图2F所示，移除全部该承载板20，以令该绝缘层23的第二表面23b完全露出，并且使该线路层21的第二电性面21b外露于该绝缘层23的第二表面23b。
于本实施例中，以蚀刻方式(或以其他减成制法)移除该承载板20及该金属层201，故会略蚀刻到该线路层21的第二电性面21b的局部区域，使该线路层21的第二电性面21b凹入及低于该绝缘层23的第二表面23a。
此外，也可选择性地再执行整平制程，以令该绝缘层23的第二表面23b与该线路层21的第二电性面21b二者的表面齐平。
另外，于另一实施例中，也可选择性地再执行图案化电镀制程，以于该线路层21的第二电性面21b上形成导电凸块(图中未示出)，而有利后续芯片封装制程的进行。
据此，即可以获取一总厚度大于或等于100微米的半导体封装载板2(即具有穿孔260的支撑结构2a与薄型化的线路结构2b二者的结合体)，以符合封装厂现有一般性的半导体封装设备的规格需求(因为当该半导体封装载板2的厚度太薄时，则需要再耗费巨资来修改或添购符合薄型化封装规范的半导体封装设备)。
此外，于进行该半导体封装载板2的电性检测时，将测试设备的其中一部分接点端子(图略)插入该些穿孔260中以接触其中一侧的导电柱22的第一端面22a(或其上的表面处理层)，以及将该测试设备的另一部分接点端子(图略)接触另外一侧的线路层21的第二电性面21b上，而得以检测出该线路层21与导电柱22的电性状态，并进而能预先淘汰掉功能有瑕疵的半导体封装载板2。
因此，本发明的制法以感光型绝缘材作为该支撑结构2a，以利于形成穿孔260，且该穿孔260的对位极为精准而无对位误差过大的问题，不仅能提供薄型化线路结构2b的暂时支撑刚性，且可借由该穿孔260外露出该导电柱22，因而得以针对该薄型化半导体封装载板2预先进行电性检测与筛选，以避免后续的半导体封装制程误用该功能有瑕疵的半导体封装载板2而导致功能正常的电子元件无端损耗且徒增生产成本的问题，故本发明可完全革除现有相关产品无法进行电性检测筛选等的缺失，且又能令具有薄型化线路结构2b的薄型化半导体封装载板2完全符合封装厂现有封装设备的规格要求，因而能避免封装厂需要再耗费巨资来修改或添购符合薄型化封装规范的封装设备。
于后续封装制程中，以半导体封装载板2为例，进行如图3A至图3D所示的后续封装制程。
如图3A所示，将至少一电子元件40设于业经电性检测与筛选过的功能正常的半导体封装载板2的该绝缘层23的第二表面23b上。
于本实施例中，该电子元件40为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件40为半导体芯片，其借由多个包含如铜凸块、焊锡凸块等的导电体400以覆晶方式电性连接于该半导体封装载板2的线路层21。或者，该电子元件40亦可借由多个如焊线的导电体(图略)以打线方式电性连接于该线路层21；亦或，该电子元件40可直接接触该线路层21。然而，有关该电子元件40电性连接该线路层21的方式不限于上述。
如图3B所示，形成一封装层41于该绝缘层的第二表面23b上，以令该封装层41包覆该电子元件40，故可借由该封装层41提供的包覆与支撑刚性，使该封装成品不会发生变形损坏等问题。
于本实施例中，该封装层41可为压合制程用的薄膜、模压制程用的封装胶体或印刷制程用的胶材等以包覆该电子元件40与该多个导电体400，且形成该封装层41的材质为聚酰亚胺(PI)、环氧树脂(epoxy)或模封的封装材。或者，该封装层41可为底胶，其可形成于该半导体封装载板2与该电子元件40之间以包覆该多个导电体400。应可理解地，有关该电子元件40的封装方式并不限于上述。
如图3C所示，借由化学方式、或激光、或等离子、或喷砂、或机械研磨等完全移除该支撑结构2a，以外露出该绝缘层23的第一表面23a及该导电柱22的第一端面22a(或其上的表面处理层)。
据此，即可形成薄型化的电子封装件4，其中，借由薄型化的该线路结构2b与提供暂时支撑刚性的支撑结构2a二者结合的总厚度能符合封装厂一般性的封装设备规范，故可不必耗费巨资来修改或添购符合薄型化封装规范的封装设备，即能顺利完成薄型化电子封装件4的封装制程，并且再借由该封装层41所提供的包覆与支撑刚性，因而即使完全移除该支撑结构2a，最终薄型化的该电子封装件4依然能保有适当的刚性而不会发生变形与损坏等问题。
如图3D所示，可形成多个如焊球的导电元件42于该绝缘层23的第一表面23a上，使该导电元件42电性连接该导电柱22的第一端面22a(或其上的表面处理层)，以便能进一步与电路板(PCB)进行结合。
因此，本发明的制法中，主要借由以感光型绝缘材作为该支撑结构2a，以利于形成穿孔260，且该穿孔260的对位极为精准而无对位误差过大的问题，以于进行电子元件40的封装作业前，先借由该穿孔260进行薄型化的该半导体封装载板2的电性检测与筛选，以预先淘汰掉功能有瑕疵的该半导体封装载板2，故能避免将功能正常的电子元件40接置于功能有瑕疵的半导体封装载板2上，因而不会发生让功能正常的电子元件40无端地耗损等问题，以有效降低该薄型化电子封装件4的整体制作成本。
此外，借由该支撑结构2a加强该半导体封装载板2的整体结构刚性，以于进行封装制程前，该薄型化的线路结构2b不会发生翘曲变形现象，且借由该支撑结构2a与薄型化线路结构2b二者结合后的总厚度能满足封装厂一般性封装设备的规范要求，致使本发明的薄型化半导体封装载板2能提供作为电子元件40的封装载板，且仅需运用一般性封装设备即能完成薄型化电子封装件4的封装制程，因而能节省高昂的薄型化封装设备的修改或添购成本。
本发明的实施例可提供一种半导体封装载板2(如图2F所示)包括：一线路结构2b以及一支撑结构2a，且该线路结构2b包含有多个线路层21、多个导电柱22及多个绝缘层23。
所述的线路层21具有相对的第一电性面21a与第二电性面21b。
所述的导电柱22具有相对的第一端面22a与第二端面22b，并以其第二端面22b立设于该线路层21的第一电性面21a上。
所述的绝缘层23包覆该线路层21与该导电柱22，且该绝缘层23具有相对的第一表面23a与第二表面23b，以令其中一侧的导电柱22的第一端面22a外露于该绝缘层23的第一表面23a，且令另一侧的线路层21的第二电性面21b外露于该绝缘层23的第二表面23b。
所述的支撑结构2a设于该线路结构2b的其中一侧的绝缘层23的第一表面23a上，且该支撑结构2a形成有至少一对应该导电柱22的穿孔260，以外露出该导电柱22的第一端面22a，其中，该支撑结构2a为一感光型绝缘材，且该支撑结构2a为可移除抛弃式结构。
于一实施例中，该支撑结构2a为一感光型介电材或感光型干膜。
综上所述，本发明的半导体封装载板2及其制法中，主要借由该感光型绝缘材支撑结构2a具有穿孔260的设计，以于进行半导体封装作业前，能先进行该半导体封装载板2的电性检测，以预先淘汰掉功能有瑕疵的半导体封装载板2避免于封装作业时误用到功能有瑕疵的半导体封装载板2，故能避免无端耗损功能正常电子元件40的问题，因而能有效降低该薄型化电子封装件4的整体制作成本，且能提高后续生产效率。
此外，借由该支撑结构2a的暂时性刚性支撑设计，促使能尽量的薄型化该线路结构2b，且借由该线路结构2b与该支撑结构2a结合后的总厚度能满足一般性封装设备的规范要求，故除了于进行封装制程前，该薄型化的半导体封装载板2不会发生翘曲现象之外，且仅需运用一般性的封装设备即能完成薄型化电子封装件4的封装作业，而无需耗费巨资来修改或添购符合薄型化封装规范的封装设备。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (8)

1.一种半导体封装载板，其特征在于，包括：
线路结构，其包含：
多个线路层，各具有相对的第一电性面与第二电性面；
多个导电柱，各具有相对的第一端面与第二端面，并以其第二端面立设于该线路层的第一电性面上；
多个绝缘层，各具有相对的第一表面与第二表面，且用以包覆该线路层与该导电柱，以令其中一侧的导电柱的第一端面外露于该绝缘层的第一表面，且令另一侧的线路层的第二电性面外露于该绝缘层的第二表面；以及
支撑结构，其设于该线路结构的其中一侧的绝缘层的第一表面上，且该支撑结构形成有至少一穿孔以外露出该导电柱的第一端面，其中，该支撑结构为一感光型绝缘材，且该支撑结构为可移除抛弃式结构。
2.如权利要求1所述的半导体封装载板，其特征在于，该支撑结构为一感光型介电材或感光型干膜。
3.一种半导体封装载板的制法，其特征在于，包括：
提供一承载板；
于该承载板上形成线路层与导电柱，该线路层具有相对的第一电性面与第二电性面，且该导电柱具有相对的第一端面与第二端面，其中，该线路层以其第二电性面贴覆于该承载板上，该导电柱以其第二端面立设于该线路层的第一电性面上；
于该承载板上形成一具有相对的第一表面与第二表面的绝缘层，以令该绝缘层包覆该线路层与该导电柱，其中，该导电柱的第一端面外露出于该绝缘层的第一表面，该线路层的第二电性面外露出于该绝缘层的第二表面，使该绝缘层、该线路层及该导电柱形成为薄型化的线路结构；
形成支撑结构于该绝缘层的第一表面上，该支撑结构为一感光型绝缘材，且该支撑结构形成有至少一穿孔以露出该导电柱的第一端面，该支撑结构为可移除抛弃式结构；以及
移除该承载板，以露出该绝缘层的第二表面与该线路层的第二电性面，其中，该线路结构与该支撑结构形成为薄型化的封装载板。
4.如权利要求3所述的半导体封装载板的制法，其特征在于，该支撑结构的穿孔以微影方式形成。
5.如权利要求3所述的半导体封装载板的制法，其特征在于，该支撑结构为一感光型介电材或感光型干膜。
6.一种半导体封装制程，其特征在于，包括：
提供一如权利要求1至2中任一项所述的半导体封装载板；
将至少一电子元件结合至该绝缘层的第二表面上，以令该电子元件电性连接该线路层；
形成一封装层于该绝缘层的第二表面上，以令该封装层包覆该电子元件；以及
完全移除该支撑结构，以露出该绝缘层的第一表面与该导电柱的第一端面。
7.如权利要求6所述的半导体封装制程，其特征在于，移除该支撑结构的方法包括有化学方式、激光、等离子、喷砂或机械研磨。
8.如权利要求6所述的半导体封装制程，其特征在于，还包括于完全移除该支撑结构后，形成导电元件于该绝缘层的第一表面上，以令该导电元件电性连接该导电柱的第一端面。
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