TW202137446A - 半導體封裝載板及其製法與封裝製程 - Google Patents

半導體封裝載板及其製法與封裝製程 Download PDF

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TW202137446A
TW202137446A TW109109205A TW109109205A TW202137446A TW 202137446 A TW202137446 A TW 202137446A TW 109109205 A TW109109205 A TW 109109205A TW 109109205 A TW109109205 A TW 109109205A TW 202137446 A TW202137446 A TW 202137446A
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Taiwan
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insulating layer
layer
supporting structure
circuit
conductive pillar
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TW109109205A
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English (en)
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TWI762885B (zh
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周保宏
余俊賢
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恆勁科技股份有限公司
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Priority to TW109109205A priority Critical patent/TWI762885B/zh
Priority to US17/202,632 priority patent/US11508673B2/en
Priority to CN202110285458.6A priority patent/CN113496983A/zh
Publication of TW202137446A publication Critical patent/TW202137446A/zh
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Publication of TWI762885B publication Critical patent/TWI762885B/zh

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Abstract

一種半導體封裝載板係包括：絕緣層與嵌埋於該絕緣層中相互疊設之線路層與導電柱所形成之薄型化線路結構、以及形成於該絕緣層上之支撐結構，且該支撐結構設有外露出該導電柱之穿孔，以於後續進行封裝作業前，可先進行該封裝載板之電性檢測與篩選，以令後續封裝作業不會誤用到功能有瑕疵之封裝載板，故能避免耗損功能正常之電子元件。本發明復提供該半導體封裝載板之製法與利用該半導體封裝載板之封裝製程。

Description

半導體封裝載板及其製法與封裝製程
本發明係有關一種半導體封裝基板，尤指一種薄化產品之半導體封裝載板及其製法與封裝製程。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了提高多層電路板之佈線精密度，業界遂發展出一種增層技術(Build-up)，亦即在一核心板(Core board)之兩表面上分別以線路增層技術交互堆疊多層之介電層及線路層，並於該介電層中開設導電盲孔(Conductive via)以供上下層線路之間電性連接。
然而，由於該核心板之厚度約30至50微米(um)，致使封裝基板難以符合薄化需求，故為了滿足微型化(miniaturization)的需求，係發展出無核心層(coreless)之封裝技術。
第1A至1B圖係為習知半導體封裝件之製法之剖面示意圖，如第TW201913906號專利公開案。
如第1A圖所示，係提供一封裝基板1，其具有線路層11及 一支撐件12，該支撐件12係具有複數外露部分該線路層11之開口120，且該支撐件12係為絕緣板材、半導體板材或金屬板材。
於後續對該封裝基板1進行電性檢測時，係將一檢測探針經由該開口120電性連接該線路層11。
如第1B圖所示，待確認該封裝基板1之線路層11呈現正常狀態後，進行封裝製程，係設置至少一半導體晶片10於該封裝基板1上，並使該半導體晶片10電性連接該線路層11，且以一包覆層13包覆該半導體晶片10。於封裝製程後，可採用化學蝕刻方式移除支撐件12。
應可理解地，當檢測該封裝基板1之線路層11呈現不正常之狀態時，則報廢該不良之封裝基板1，而不會對該不良之封裝基板1進行封裝製程。
惟，習知半導體封裝件之製法中，該支撐件12係為絕緣板材、半導體板材或金屬板材，故其不易形成該開口120，且該開口120之對位誤差過大，致使於後續對該封裝基板1進行電性檢測時，該檢測探針容易插錯開口120而誤觸該線路層11，故於封裝作業前針對該封裝基板1進行電性檢測與篩選之作業容易發生錯誤，造成於封裝製程時(如第1B圖所示)，容易將功能正常之半導體晶片10接置於功能有瑕疵之封裝基板1上，導致必須將原本功能正常之半導體晶片10與功能有瑕疵之封裝基板1一併報廢，因而大幅增加該半導體封裝件1之整體製作成本。
另外，第TW I531038號專利亦配置有一具有開口之支撐載板，但其仍有開口之對位誤差過大之問題。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決 的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體封裝載板，係包括：線路結構，係包含：複數線路層，各係具有相對之第一電性面與第二電性面；複數導電柱，各係具有相對之第一端面與第二端面，並以其第二端面立設於該線路層之第一電性面上；複數絕緣層，各係具有相對之第一表面與第二表面，且係用以包覆該線路層與該導電柱，以令其中一側之導電柱之第一端面外露於該絕緣層之第一表面，且令另一側之線路層之第二電性面外露於該絕緣層之第二表面；以及支撐結構，係設於該線路結構之其中一側之絕緣層之第一表面上，且該支撐結構形成有至少一穿孔以外露出該導電柱之第一端面，其中，該支撐結構係為一感光型絕緣材。
本發明復提供一種半導體封裝載板之製法，係包括：提供一承載板；於該承載板上形成線路層與導電柱，該線路層係具有相對之第一電性面與第二電性面，且該導電柱係具有相對之第一端面與第二端面，其中，該線路層係以其第二電性面貼覆於該承載板上，該導電柱係以其第二端面立設於該線路層之第一電性面上；於該承載板上形成一具有相對之第一表面與第二表面之絕緣層，以令該絕緣層包覆該線路層與該導電柱，其中，該導電柱之第一端面係外露出於該絕緣層之第一表面，該線路層之第二電性面係外露出於該絕緣層之第二表面，使該絕緣層、該線路層及該導電柱形成為薄型化之線路結構；形成支撐結構於該絕緣層之第一表面上， 該支撐結構係為一感光型絕緣材，且該支撐結構形成有至少一穿孔以露出該導電柱之第一端面；以及移除該承載板，以露出該絕緣層之第二表面與該線路層之第二電性面，其中，該線路結構與該支撐結構形成為薄型化之封裝載板。
前述之製法中，該支撐結構之穿孔係以微影方式形成之。
前述之半導體封裝載板及其製法中，該支撐結構係為一感光型介電材。
前述之半導體封裝載板及其製法中，該支撐結構係為一由環氧樹脂基材所組成之絕緣材所形成者，且該支撐結構之穿孔係以雷射、或電漿、或噴砂形成之。
本發明另提供一種半導體封裝製程，係包括：提供一前述之半導體封裝載板；將至少一電子元件結合至該絕緣層之第二表面上，以令該電子元件電性連接該線路層；形成一封裝層於該絕緣層之第二表面上，以令該封裝層包覆該電子元件；以及完全移除該支撐結構，以露出該絕緣層之第一表面與該導電柱之第一端面。
前述之半導體封裝製程中，移除該支撐結構的方法係包括有化學方式、雷射、電漿、噴砂或機械研磨。
前述之半導體封裝製程中，復包括於完全移除該支撐結構後，形成導電元件於該絕緣層之第一表面上，以令該導電元件電性連接該導電柱之第一端面。
由上可知，本發明之半導體封裝載板及其製法與封裝製程，主要藉由以感光型絕緣材作為該支撐結構，以利於形成穿孔，且該穿孔之 對位極為精準而無對位誤差過大之問題，以於進行半導體封裝作業之前，可先針對該封裝載板進行電性檢測作業，以先篩選出功能正常之封裝載板，故相較於習知技術，本發明能避免於封裝作業時誤用到功能有瑕疵之封裝載板，故不會發生耗損功能正常之電子元件之問題，因而能降低該電子封裝件之整體製作成本，且提高後續生產效率。
再者，藉由該支撐結構之暫時性剛性支撐設計，促使能儘量的薄型化該線路結構，且藉由該線路結構與該支撐結構結合後之總厚度能滿足一般性封裝之規範要求，故除了於進行封裝製程前，該封裝載板不會發生翹曲現象之外，且僅需運用一般性的封裝設備即能完成薄型化電子封裝件的封裝作業，而無需耗費鉅資來修改或添購符合薄型化封裝規範之封裝設備。
1:封裝基板
10:半導體晶片
11:線路層
12:支撐件
120:開口
13:包覆層
2:半導體封裝載板
2a:支撐結構
2b:線路結構
20:承載板
200:板體
201:銅層
21:線路層
21a:第一電性面
21b:第二電性面
22:導電柱
22a:第一端面
22b:第二端面
23:絕緣層
23a,23a’,23a”:第一表面
23b:第二表面
260:穿孔
4:電子封裝件
40:電子元件
400:導電體
41:封裝層
42:導電元件
t:厚度
第1A至1B圖係為習知半導體封裝件之製法的剖視示意圖；
第2A至2F圖係為本發明之半導體封裝載板之製法的剖視示意圖；以及
第3A至3D圖係為第2F圖之後續封裝製程的剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之半導體封裝載板2之製法的剖面示意圖。
於本實施例中，該半導體封裝載板2係為無核心層(coreless)形式，其作為晶片尺寸覆晶封裝(flip-chip chip scale package，簡稱FCCSP)用之載板。
如第2A圖所示，提供一承載板20，且藉由圖案化製程形成一線路層21於該承載板20上，該線路層21具有相對之第一電性面21a與第二電性面21b，且該線路層21以其第二電性面21b貼覆在該承載板20上，再藉由圖案化製程，電鍍形成複數導電柱22於該線路層21上，該導電柱22係具有相對之第一端面22a與第二端面22b，且該導電柱22係以其第二端面22b立設於該線路層21之第一電性面21a上。
於本實施例中，該承載板20係為如絕緣板、陶瓷板、銅箔基板或玻璃板等基材，但無特別限制。具體地，本實施例係以銅箔基板作 說明，其板體200兩側表面具有銅層201。
如第2B圖所示，形成一絕緣層23於該承載板20上，使該絕緣層23包覆該線路層21與該複數導電柱22，其厚度t(如第2C圖所示)可小於或等於60微米(um)，如20至60微米不等。
於本實施例中，該絕緣層23係具有相對之第一表面23a’與第二表面23b，且該絕緣層23以其第二表面23b結合至該承載板20上。
再者，該絕緣層23係以鑄模方式、塗佈方式或壓合方式形成於該承載板20上，且形成該絕緣層23之材質係為介電材料，該介電材料可為環氧樹脂(Epoxy)，抑或者為鑄模化合物(Molding Compound)或底層塗料(Primer)，如環氧模壓樹脂(Epoxy Molding Compound，簡稱EMC)，其中，該環氧模壓樹脂係含有充填物(filler)，且該充填物含量為70至90wt%。
如第2C圖所示，移除該絕緣層23之第一表面23a’之部分材質，使該絕緣層23之第一表面23a”與該導電柱22之第一端面22a二者齊平(即共平面)，且該導電柱22之第一端面22a外露於該絕緣層23之第一表面23a”。
再者，於另一實施例中，可選擇性地移除該導電柱22之第一端面22a之部分材料(如蝕刻或其它等減成製法)，以令該導電柱22之第一端面22a能凹入且低於該絕緣層23之第一表面23a”。
如第2D圖所示，亦可於該絕緣層23之第一表面23a”上再增設至少一線路層21、至少一導電柱22及至少一絕緣層23，以令該些線路層21(如圖所示為三層)、導電柱22(如圖所示為三層)及絕緣層23 (如圖所示為三層)作為薄型化之線路結構2b。應可理解地，薄型化之該線路結構2b可視實際需求由單層之線路層21、導電柱22及絕緣層23所構成，或由複數層之線路層21、導電柱22及絕緣層23所構成。
於本實施例中，最外側之絕緣層23之第一表面23a與最外側之導電柱22之第一端面22a二者齊平(即共平面)，且最外側之導電柱22之第一端面22a外露於最外側之絕緣層23之第一表面23a。應可理解地，該導電柱22之第一端面22a亦可設為內凹或凸出該絕緣層23之第一表面23a，亦即該導電柱22之第一端面22a可視實際需求設為齊平、或內凹、或凸出於該絕緣層23之第一表面23a。
再者，可選擇性地形成一表面處理層(圖未示)於最外側之導電柱22之第一端面22a上，且令該表面處理層之表面可內凹、或齊平、或突出於最外側之絕緣層23之第一表面23a。例如，形成該表面處理層之材質可為銅面保護劑、有機保焊劑(Organic Solderability Preservative，簡稱OSP)、電鍍鎳鈀金、化學鎳鈀金(ENEPIG)、電鍍鎳金(Ni/Au)、鍍錫、鍍銀或上述組合等之其中一者。
如第2E圖所示，形成一絕緣材之支撐結構2a於該線路結構2b之第一表面23a上。
於本實施例中，該支撐結構2a係可由感光型絕緣材、或環氧樹酯基材，如雙馬來醯亞胺三嗪(Bismaleimide Triazine，簡稱BT)、FR-4、FR-5等絕緣材(其中以感光型絕緣材為最佳之選擇)，經由例如以鑄模方式、塗佈方式或壓合方式形成於該絕緣層23之第一表面23a上。
再者，該支撐結構2a上相對於該導電柱22之部位形成有至 少一穿孔260，以外露出最外側之導電柱22之第一端面22a(或其上之表面處理層)。於本實施例中，該穿孔260可藉由曝光顯影、或雷射、或電漿、或噴砂等方式形成之。
如第2F圖所示，移除全部該承載板20，以令該絕緣層23之第二表面23b完全露出，並且使該線路層21之第二電性面21b外露於該絕緣層23之第二表面23b。
於本實施例中，係以蝕刻方式(或以其他減成製法)移除該承載板20及該金屬層201，故會略蝕刻到該線路層21之第二電性面21b之局部區域，使該線路層21之第二電性面21b凹入及低於該絕緣層23之第二表面23a。
再者，亦可選擇性地再執行整平製程，以令該絕緣層23之第二表面23b與該線路層21之第二電性面21b二者之表面齊平。
又，於另一實施例中，亦可選擇性地再執行圖案化電鍍製程，以於該線路層21之第二電性面21b上形成導電凸塊(圖中未示出)，而有利後續晶片封裝製程之進行。
據此，即可以獲取一總厚度大於或等於100微米之半導體封裝載板2(即具有穿孔260之支撐結構2a與薄型化之線路結構2b二者之結合體)，以符合封裝廠現有一般性之半導體封裝設備的規格需求(因為當該半導體封裝載板2之厚度太薄時，則需要再耗費鉅資來修改或添購符合薄型化封裝規範之半導體封裝設備)。
再者，於進行該半導體封裝載板2之電性檢測時，係將測試設備之其中一部分接點端子(圖略)插入該些穿孔260中以接觸其中一側 之導電柱22之第一端面22a(或其上之表面處理層)，以及將該測試設備之另一部分接點端子(圖略)接觸另外一側之線路層21之第二電性面21b上，而得以檢測出該線路層21與導電柱22之電性狀態，並進而能預先淘汰掉功能有瑕疵之半導體封裝載板2。
因此，本發明之製法係以感光型絕緣材作為該支撐結構2a，以利於形成穿孔260，且該穿孔260之對位極為精準而無對位誤差過大之問題，不僅能提供薄型化線路結構2b之暫時支撐剛性，且可藉由該穿孔260外露出該導電柱22，因而得以針對該薄型化半導體封裝載板2預先進行電性檢測與篩選，以避免後續之半導體封裝製程誤用該功能有瑕疵之半導體封裝載板2而導致功能正常之電子元件無端損耗且徒增生產成本之問題，故本發明可完全革除習知相關產品無法進行電性檢測篩選等之缺失，且又能令具有薄型化線路結構2b之薄型化半導體封裝載板2完全符合封裝廠現有封裝設備之規格要求，因而能避免封裝廠需要再耗費鉅資來修改或添購符合薄型化封裝規範之封裝設備。
於後續封裝製程中，以半導體封裝載板2為例，進行如第3A至3D圖所示之後續封裝製程。
如第3A圖所示，將至少一電子元件40設於業經電性檢測與篩選過之功能正常之半導體封裝載板2之該絕緣層23之第二表面23b上。
於本實施例中，該電子元件40係為主動元件、被動元件或其二者組合，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該電子元件40係為半導體晶片，其藉由複數包 含如銅凸塊、焊錫凸塊等之導電體400以覆晶方式電性連接於該半導體封裝載板2之線路層21。或者，該電子元件40亦可藉由複數如銲線之導電體(圖略)以打線方式電性連接於該線路層21；亦或，該電子元件40可直接接觸該線路層21。然而，有關該電子元件40電性連接該線路層21之方式不限於上述。
如第3B圖所示，形成一封裝層41於該絕緣層之第二表面23b上，以令該封裝層41包覆該電子元件40，故可藉由該封裝層41提供之包覆與支撐剛性，使該封裝成品不會發生變形損壞等問題。
於本實施例中，該封裝層41可為壓合製程用之薄膜、模壓製程用之封裝膠體或印刷製程用之膠材等以包覆該電子元件40與該複數導電體400，且形成該封裝層41之材質係為聚醯亞胺(PI)、環氧樹脂(epoxy)或模封之封裝材。或者，該封裝層41可為底膠，其可形成於該半導體封裝載板2與該電子元件40之間以包覆該複數導電體400。應可理解地，有關該電子元件40之封裝方式並不限於上述。
如第3C圖所示，藉由化學方式、或雷射、或電漿、或噴砂、或機械研磨等完全移除該支撐結構2a，以外露出該絕緣層23之第一表面23a及該導電柱22之第一端面22a(或其上之表面處理層)。
據此，即可形成薄型化之電子封裝件4，其中，藉由薄型化之該線路結構2b與提供暫時支撐剛性之支撐結構2a二者結合之總厚度能符合封裝廠一般性的封裝設備規範，故可不必耗費鉅資來修改或添購符合薄型化封裝規範之封裝設備，即能順利完成薄型化電子封裝件4的封裝製程，並且再藉由該封裝層41所提供的包覆與支撐剛性，因而即使完全移除 該支撐結構2a，最終薄型化之該電子封裝件4依然能保有適當之剛性而不會發生變形與損壞等問題。
如第3D圖所示，可形成複數如焊球之導電元件42於該絕緣層23之第一表面23a上，使該導電元件42電性連接該導電柱22之第一端面22a(或其上之表面處理層)，以便能進一步與電路板(PCB)進行結合。
因此，本發明之製法中，主要藉由以感光型絕緣材作為該支撐結構2a，以利於形成穿孔260，且該穿孔260之對位極為精準而無對位誤差過大之問題，以於進行電子元件40之封裝作業前，先藉由該穿孔260進行薄型化之該半導體封裝載板2之電性檢測與篩選，以預先淘汰掉功能有瑕疵之該半導體封裝載板2，故能避免將功能正常之電子元件40接置於功能有瑕疵之半導體封裝載板2上，因而不會發生讓功能正常之電子元件40無端地耗損等問題，以有效降低該薄型化電子封裝件4之整體製作成本。
再者，藉由該支撐結構2a加強該半導體封裝載板2之整體結構剛性，以於進行封裝製程前，該薄型化之線路結構2b不會發生翹曲變形現象，且藉由該支撐結構2a與薄型化線路結構2b二者結合後之總厚度能滿足封裝廠一般性封裝設備之規範要求，致使本發明之薄型化半導體封裝載板2能提供作為電子元件40之封裝載板，且僅需運用一般性封裝設備即能完成薄型化電子封裝件4之封裝製程，因而能節省高昂的薄型化封裝設備之修改或添購成本。
本發明之實施例可提供一種半導體封裝載板2(如第2F圖所示)係包括：一線路結構2b以及一支撐結構2a，且該線路結構2b係包 含有複數線路層21、複數導電柱22及複數絕緣層23。
所述之線路層21係具有相對之第一電性面21a與第二電性面21b。
所述之導電柱22係具有相對之第一端面22a與第二端面22b，並以其第二端面22b立設於該線路層21之第一電性面21a上。
所述之絕緣層23係包覆該線路層21與該導電柱22，且該絕緣層23具有相對之第一表面23a與第二表面23b，以令其中一側之導電柱22之第一端面22a外露於該絕緣層23之第一表面23a，且令另一側之線路層21之第二電性面21b外露於該絕緣層23之第二表面23b。
所述之支撐結構2a係設於該線路結構2b之其中一側之絕緣層23之第一表面23a上，且該支撐結構2a形成有至少一對應該導電柱22之穿孔260，以外露出該導電柱22之第一端面22a，其中，該支撐結構2a係為一感光型絕緣材。
於一實施例中，該支撐結構2a係為一感光型介電材。
於一實施例中，該支撐結構2a係為一環氧樹脂基材之絕緣材。
綜上所述，本發明之半導體封裝載板2及其製法中，主要藉由該感光型絕緣材支撐結構2a具有穿孔260之設計，以於進行半導體封裝作業前，能先進行該半導體封裝載板2之電性檢測，以預先淘汰掉功能有瑕疵之半導體封裝載板2避免於封裝作業時誤用到功能有瑕疵之半導體封裝載板2，故能避免無端耗損功能正常電子元件40之問題，因而能有效降低該薄型化電子封裝件4之整體製作成本，且能提高後續生產效率。
再者，藉由該支撐結構2a之暫時性剛性支撐設計，促使能儘量的薄型化該線路結構2b，且藉由該線路結構2b與該支撐結構2a結合後之總厚度能滿足一般性封裝設備之規範要求，故除了於進行封裝製程前，該薄型化之半導體封裝載板2不會發生翹曲現象之外，且僅需運用一般性的封裝設備即能完成薄型化電子封裝件4的封裝作業，而無需耗費鉅資來修改或添購符合薄型化封裝規範之封裝設備。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:半導體封裝載板
2a:支撐結構
2b:線路結構
21:線路層
21a:第一電性面
21b:第二電性面
22:導電柱
22a:第一端面
22b:第二端面
23:絕緣層
23a:第一表面
23b:第二表面
260:穿孔

Claims (10)

  1. 一種半導體封裝載板，係包括：
    線路結構，係包含：
    複數線路層，各係具有相對之第一電性面與第二電性面；
    複數導電柱，各係具有相對之第一端面與第二端面，並以其第二端面立設於該線路層之第一電性面上；
    複數絕緣層，各係具有相對之第一表面與第二表面，且係用以包覆該線路層與該導電柱，以令其中一側之導電柱之第一端面外露於該絕緣層之第一表面，且令另一側之線路層之第二電性面外露於該絕緣層之第二表面；以及
    支撐結構，係設於該線路結構之其中一側之絕緣層之第一表面上，且該支撐結構形成有至少一穿孔以外露出該導電柱之第一端面，其中，該支撐結構係為一感光型絕緣材。
  2. 如申請專利範圍第1項所述之半導體封裝載板，其中，該支撐結構係為一感光型介電材。
  3. 如申請專利範圍第1項所述之半導體封裝載板，其中，該支撐結構係為一由環氧樹脂基材所組成之絕緣材所形成者。
  4. 一種半導體封裝載板之製法，係包括：
    提供一承載板；
    於該承載板上形成線路層與導電柱，該線路層係具有相對之第一電性面與第二電性面，且該導電柱係具有相對之第一端面與第二端面，其中，該線路層係以其第二電性面貼覆於該承載板上，該導電柱係以其第二端面立設於該線路層之第一電性面上；
    於該承載板上形成一具有相對之第一表面與第二表面之絕緣層，以令該絕緣層包覆該線路層與該導電柱，其中，該導電柱之第一端面係外露出於該絕緣層之第一表面，該線路層之第二電性面係外露出於該絕緣層之第二表面，使該絕緣層、該線路層及該導電柱形成為薄型化之線路結構；
    形成支撐結構於該絕緣層之第一表面上，該支撐結構係為一感光型絕緣材，且該支撐結構形成有至少一穿孔以露出該導電柱之第一端面；以及
    移除該承載板，以露出該絕緣層之第二表面與該線路層之第二電性面，其中，該線路結構與該支撐結構形成為薄型化之封裝載板。
  5. 如申請專利範圍第4項所述之半導體封裝載板之製法，其中，該支撐結構之穿孔係以微影方式形成之。
  6. 如申請專利範圍第4項所述之半導體封裝載板之製法，其中，該支撐結構係為一感光型介電材。
  7. 如申請專利範圍第4項所述之半導體封裝載板之製法，其中，該支撐結構係為一由環氧樹脂基材所組成之絕緣材所形成者，且該支撐結構之穿孔係以雷射、或電漿、或噴砂形成之。
  8. 一種半導體封裝製程，係包括：
    提供一如申請專利範圍第1至3項之其中一者所述之半導體封裝載板；
    將至少一電子元件結合至該絕緣層之第二表面上，以令該電子元件電性連接該線路層；
    形成一封裝層於該絕緣層之第二表面上，以令該封裝層包覆該電子元件；以及
    完全移除該支撐結構，以露出該絕緣層之第一表面與該導電柱之第一端面。
  9. 如申請專利範圍第8項所述之半導體封裝製程，其中，移除該支撐結構的方法係包括有化學方式、雷射、電漿、噴砂或機械研磨。
  10. 如申請專利範圍第8項所述之半導體封裝製程，復包括於完全移除該支撐結構後，形成導電元件於該絕緣層之第一表面上，以令該導電元件電性連接該導電柱之第一端面。
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