WO2022012422A1 - 封装基板制作方法 - Google Patents

封装基板制作方法 Download PDF

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Publication number
WO2022012422A1
WO2022012422A1 PCT/CN2021/105394 CN2021105394W WO2022012422A1 WO 2022012422 A1 WO2022012422 A1 WO 2022012422A1 CN 2021105394 W CN2021105394 W CN 2021105394W WO 2022012422 A1 WO2022012422 A1 WO 2022012422A1
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WIPO (PCT)
Prior art keywords
layer
circuit layer
metal
cavity
manufacturing
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PCT/CN2021/105394
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English (en)
French (fr)
Inventor
陈先明
伯迈斯特法兰克
冯磊
赵玉君
黄本霞
易锦馨
冯进东
李源
姜丽娜
特纳爱德华
王闻师
Original Assignee
珠海越亚半导体股份有限公司
安世半导体
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Application filed by 珠海越亚半导体股份有限公司, 安世半导体 filed Critical 珠海越亚半导体股份有限公司
Priority to KR1020237005278A priority Critical patent/KR20230038559A/ko
Priority to DE112021003770.6T priority patent/DE112021003770T5/de
Priority to GB2300796.6A priority patent/GB2611941A/en
Priority to JP2023502730A priority patent/JP2023534256A/ja
Priority to US18/005,608 priority patent/US20230326765A1/en
Publication of WO2022012422A1 publication Critical patent/WO2022012422A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular, to a method for manufacturing a packaging substrate.
  • Chip packages can be divided into leaded packages and leadless packages according to the type of pins. Compared with leaded packages, leadless packaged semiconductor devices have the advantages of low lead inductance, good thermal conductivity, and thin package thickness, which can reduce the cost of the package. The footprint on the PCB (Printed Circuit Board).
  • PCB printed Circuit Board
  • Leadless packaged semiconductor devices are commonly packaged with QFN (square flat leadless device) based on Leadframe (lead frame) and LGA (Land Grid Array, grid array package) and BGA (Ball Array package) based on organic packaging substrate.
  • QFN square flat leadless device
  • LGA Land Grid Array, grid array package
  • BGA Ball Grid array package
  • Grid Array, ball grid array package for the former, after the QFN is mounted on the PCB, an automatic optical inspection system can be used to detect defects in its soldering condition; for the latter, due to the pin design of LGA and BGA, it is avoided.
  • the edge of the package body cannot be exposed, so there is a detection blind spot.
  • the present application aims to solve one of the technical problems in the related art at least to a certain extent. To this end, the present application proposes a method for fabricating a package substrate, and the following is an overview of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the claims.
  • the technical solution is as follows:
  • an embodiment of the present application provides a method for fabricating a package substrate, including the following steps:
  • a carrier board is provided, the pattern of the first circuit layer is made on the carrier board, and metal is deposited to form the first circuit layer;
  • a gold cavity pattern is made on the upper surface of the first circuit layer, metal is deposited and etched to form a metal cavity, and a dielectric layer is pressed and thinned on the surface of the metal cavity to expose the upper surface of the metal cavity;
  • a first solder resist layer and a second solder resist layer are respectively formed on the surfaces of the first circuit layer and the second circuit layer, and the first solder resist layer or the second solder resist layer is patterned and formed pad;
  • the cavity, the first circuit layer, the second circuit layer, the first solder resist layer and the second solder resist layer are cut.
  • the packaging substrate proposed in the present application can lead out the lead solder joints of electronic components to the side of the packaging substrate, which is convenient for optical
  • the application can complete the redistribution of multi-layer circuits on the packaging substrate, and is suitable for wire bonding and chip die packaging, as well as multi-chip and multi-device integrated packaging, which improves the Diversification and integration of functions of the substrate;
  • the packaging process of the packaging substrate proposed in the present application is simple and saves production costs.
  • the depositing metal includes sequentially depositing a metal seed layer and depositing a circuit layer.
  • the metal seed layer material includes metal titanium and metal copper.
  • the method further includes forming a protective layer, and the protective layer is provided on the circuit layer and the surface of the pad.
  • the protective layer material includes nickel-palladium-gold, nickel-gold, tin, silver, and organic solder protection film.
  • the method of depositing metal includes at least one of the following:
  • an embodiment of the present application provides another method for fabricating a package substrate, including the following steps:
  • a carrier board is provided, the pattern of the first circuit layer is made on the carrier board, and metal is deposited to form the first circuit layer;
  • a first solder resist layer and a second solder resist layer are correspondingly formed on the surface of the second circuit layer, and the first solder resist layer or the second solder resist layer is patterned to form a pad;
  • the method for manufacturing a package substrate according to the second aspect of the present application has at least the following beneficial effects:
  • the package substrate proposed in the present application can lead solder joints of electronic components to the side of the package substrate, which is convenient for optical
  • the application can complete the redistribution of multi-layer circuits on the packaging substrate, and is suitable for wire bonding and chip die packaging, as well as multi-chip and multi-device integrated packaging, which improves the Diversification and integration of functions of the substrate;
  • the packaging process of the packaging substrate proposed in the present application is simple and saves production costs.
  • the dielectric layer is drilled by means of laser drilling.
  • the material of the medium layer includes a prepreg, a film-type resin and a polyethylene resin.
  • the thickness of the dielectric layer (100) is between 180um and 250um.
  • FIG. 1 is a cross-sectional view of a package substrate provided by an embodiment of the present application
  • FIGS. 2 to 11 are cross-sectional views corresponding to steps of a method for manufacturing a package substrate provided by another embodiment of the present application;
  • 12 to 16 are cross-sectional views corresponding to steps of a method for fabricating a package substrate provided by another embodiment of the present application.
  • Dielectric layer 100 Dielectric layer 100 , first circuit layer 210 , second circuit layer 220 , first solder mask layer 310 , second solder mask layer 320 , pad 330 , metal cavity 230 , cavity 240 , protective layer 400 , seed layer 500 , photosensitive dry film 600 , carrier plate 700 .
  • the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including this number, above, below, within, etc. are understood as including this number. If it is described that the first and the second are only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance, or indicating the number of the indicated technical features or the order of the indicated technical features. relation.
  • an embodiment of the present application provides a packaging substrate, including a dielectric layer 100 ; a circuit layer, including a first circuit layer 210 and a second circuit layer 220 respectively disposed on the upper surface and the lower surface of the dielectric layer 100 .
  • the first circuit layer 210 extends horizontally from the upper surface of the dielectric layer 100 to both ends of the dielectric layer 100
  • the second circuit layer 220 extends from the lower surface of the dielectric layer 100 through the sidewall of the dielectric layer 100 to overlap with the first circuit layer 210 ,
  • a flanking structure is formed;
  • the solder mask layer, including the first solder mask layer 310 and the second solder mask layer 320, are respectively arranged on the surfaces of the first circuit layer 210 and the second circuit layer 220, and the first solder mask layer 310 or the second resistance layer
  • One of the solder layers 320 is provided with a pad 330, and the pad 330 is connected to the circuit layer.
  • the upper surface and the lower surface of the dielectric layer 100 are respectively covered with the first circuit layer 210 and the second circuit layer 220, and the surfaces of the first circuit layer 210 and the second circuit layer 220 are provided with a solder resist layer and Pad 330, wherein the pad 330 is communicated with the first circuit layer 210 for connecting with the pins of the electronic components mounted on the package substrate, and the first circuit layer 210 extends from the upper surface of the dielectric layer 100 to the horizontal layer of the dielectric At both ends of the layer 100, the second circuit layer 220 extends from the lower surface of the dielectric layer 100 through the sidewall of the dielectric layer 100 and overlaps with the first circuit layer 210 to form a flanking structure.
  • the first circuit layer 210 and the second circuit layer 220 connect the dielectric layer. 100 is wrapped inside, and the dielectric layer 100 and the flank structure form the chute cavity 240 structure.
  • semiconductor electronic components such as LGA or BGA whose pin position is not exposed on the side
  • the pins and pads 330 located on the lower surface of the device connection the pad 330 is connected to the first circuit layer 210, and the first circuit layer 210 is drawn out from the flanking structure, and then the electrical characteristics of the electronic components are drawn out to the flanking structures on both sides of the dielectric layer 100.
  • soldering material includes tin-lead solder, silver solder, copper solder and the like.
  • an embodiment of the present application provides a package substrate.
  • a first circuit layer 210 and a second circuit layer 220 respectively include a first end of the first circuit layer and a second end of the first circuit layer separated by an insulating material. terminal and the first terminal of the second circuit layer and the second terminal of the second circuit layer.
  • the first circuit layer 210 and the second circuit layer 220 respectively include two parts, the two parts of the first circuit layer 210 are respectively disposed on the lower surfaces of the two pads, and the two pads are respectively connected to the electronic element.
  • the positive and negative electrodes of the electronic components are drawn out to both sides of the substrate through the first end of the first circuit layer and the second end of the first circuit layer, and are connected with the first end of the second circuit layer and the second end of the first circuit layer.
  • the second end of the second circuit layer is connected to realize electrical distinction.
  • the first circuit layer or the second circuit layer can be composed of It consists of two parts, corresponding to the positive and negative electrodes of the same electronic component.
  • the first circuit layer or the second circuit layer can also have a non-disconnected structure.
  • a strip structure formed by a layer of metal is connected to the two and the pads.
  • the two pads respectively correspond to the positive electrode (negative electrode) of one electronic component and the negative electrode (positive electrode) of another electronic component, and perform electrical connection of multiple electronic components.
  • an embodiment of the present application provides a package substrate, further comprising a protective layer 400 , the protective layer 400 is disposed on the surface of the circuit layer and the pad 330 , in one embodiment, on the second circuit layer 220 and the solder
  • the surface of the disk 330 is covered with a protective layer 400.
  • an embodiment of the present application provides a packaging substrate, and the material of the protective layer 400 includes nickel-palladium-gold, nickel-gold, tin, silver, and organic solder protection film.
  • another embodiment of the present application further provides a method for fabricating a package substrate, the method including but not limited to the following steps:
  • Step S101 a carrier board 700 is provided, a pattern of the first circuit layer 210 is made on the carrier board 700 , metal is deposited to form the first circuit layer 210 , specifically, as shown in FIG.
  • the pattern of the first circuit layer 210 is formed by exposure and development, and then the first circuit layer 210 is formed by electroplating.
  • the two sides of the carrier board 700 include detachable double-layer copper clad laminates.
  • the first circuit layer 210 can be formed on both sides of the circuit board as much as possible. In an embodiment of the present application, preferably, a single side is used as an example to describe the manufacturing steps.
  • Step S102 a cavity 240 pattern is formed on the upper surface of the first circuit layer 210 , metal is deposited and etched to form a metal cavity 230 , the dielectric layer 100 is laminated on the surface of the metal cavity 230 and thinned to expose the upper surface of the metal cavity 230 Specifically, as shown in FIG.
  • a layer of photosensitive dry film 600 is continuously adhered on the photosensitive dry film 600, the cavity 240 is patterned by exposure and development, and the protective layer 400 is formed by electroplating or electroless plating,
  • the metal cavity 230 is formed by electroplating again, and the first photosensitive dry film 600 and the second photosensitive dry film 600 are removed with a film stripping solution, and the upper surface and sidewalls of the metal cavity 230 are exposed.
  • the dielectric layers are stacked and laminated. 100 , as shown in FIG.
  • the dielectric material is thinned and planarized by the grinding plate process until the upper surface of the strip-shaped metal cavity 230 is exposed, so that the upper surface of the metal cavity 230 and the upper surface of the dielectric layer 100 are on the same plane, and the bearing The board 700 is separated from the dielectric layer 100 so that the first circuit layer 210 and the lower surface of the dielectric layer 100 are on the same surface.
  • the material of the protective layer 400 is a chemically inactive metal, such as nickel, titanium, etc.
  • the material of the dielectric layer 100 includes a prepreg (PP), a thin film resin (ABF) or an epoxy resin (PID), a prepreg and
  • the thin film resin can be thinned by plasma etching, grinding plate polishing or laser drilling, and the epoxy resin can be thinned by exposure and development.
  • the lamination thickness is between 180-250um.
  • the prepreg is a sheet material made of treated glass fiber cloth impregnated with resin glue, and then heat-treated (pre-baking) to make the resin enter the semi-curing stage. It will soften under heat and pressure, and will react and solidify after cooling.
  • Step S103 remove the carrier plate 700, etch away the metal cavity 230 to expose the cavity 240, deposit metal on the surface and sidewalls of the cavity 240 and the surface of the dielectric layer 100 and perform patterning and etching to form the second circuit layer 220, Specifically, as shown in FIG. 6 , a photosensitive dry film 600 is pasted on the lower surface of the dielectric layer 100 including the first metal layer, and the photosensitive dry film 600 is cured by a photolithography process. The photosensitive dry film 600 is exposed to the whole plate for the purpose of The first circuit layer 210 is protected, and the metal cavity 230 is removed by etching with a metal etchant to form a cavity 240 .
  • the sidewall of the cavity 240 is vertical, the bottom size is the same as the top size, the cavity 240 is composed of the bottom nickel metal protective layer 400 and the sidewall organic resin medium layer 100, as shown in FIG. 7, the nickel metal protection is removed by using a nickel etching solution Layer 400, the upper surface of the first circuit layer 210 is exposed, and then the photosensitive dry film 600 is removed with the stripping solution to expose the lower surface of the first circuit layer 210.
  • the seed layer 500 is formed on the upper surface by sputtering or chemical electroplating.
  • the seed layer 500 includes metals such as titanium and copper, but is not limited to the above-mentioned metals.
  • Expose protect the first circuit layer 210, and then deposit a metal copper layer on the upper surface of the seed layer 500 by whole plate electroplating.
  • a photosensitive dry film 600 is adhered to the upper surface of the metal copper layer, and photolithography is used to form a specific Using the etching process to etch the metal copper layer and the seed layer 500, the second circuit layer 220 is formed, and the photosensitive dry film 600 on the upper and lower surfaces is removed with a film stripping solution.
  • the method of depositing metal includes physical sputtering and electroless plating.
  • electroless plating is used to deposit the metal layer.
  • Step S104 respectively forming a first solder resist layer 310 and a second solder resist layer 320 on the surfaces of the first circuit layer 210 and the second circuit layer 220 , and patterning the first solder resist layer 310 or the second solder resist layer 320 Pads 330 are formed. Specifically, as shown in FIG.
  • a first solder resist layer 310 and a second solder resist layer 320 are respectively applied on the surfaces of the first circuit layer 210 and the second circuit layer 220 and the first solder resist layer 310
  • a pad 330 is formed at a specific position for connection with the first circuit layer 210, and further metal surface treatment is performed on the surface of the pad 330 and the surface of the second circuit layer 220 to form a protective layer 400, and the surface treatment includes depositing nickel-palladium-gold, nickel-gold , tin, silver and other chemically stable metals, including the use of organic solder mask for surface coverage.
  • Step S105 cutting the cavity 240 , the first circuit layer 210 , the second circuit layer 220 , the first solder resist layer 310 and the second solder resist layer 320 , specifically, as shown in FIG. 11 , the mounting of electronic components is performed , install the pins of the electronic components at the position of the pad 330 and use plastic sealing material for plastic packaging, and cut the position of the cavity 240 to form a packaging unit, and point the pins of the electronic components to the first circuit layer 210 and the first circuit layer 210 and the first circuit layer 210. Two ends of the circuit layer 220 are cut.
  • another embodiment of the present application further provides another method for fabricating a package substrate, the method including but not limited to the following steps:
  • step S201 a carrier board 700 is provided, a pattern of the first circuit layer 210 is made on the carrier board 700 , metal is deposited to form the first circuit layer 210 , specifically, as shown in FIG. 2 , a photosensitive dry film is applied on the carrier board 700 600 , forming a pattern of the first circuit layer 210 by exposure and developing, and then forming the first circuit layer 210 by electroplating.
  • Step S202 laminating the dielectric layer 100 on the upper surface of the first circuit layer 210 , drilling the dielectric layer 100 to form the cavity 240 , specifically, as shown in FIG. 12 , stacking and laminating the dielectric layer 100 and the dielectric layer 100 Adjust according to design needs.
  • the thickness of the dielectric layer 100 is between 180-250um
  • the material of the dielectric layer 100 includes thermosetting organic resins such as prepreg or film resin or thermoplastic organic resins such as polyethylene.
  • the medium layer 100 is made of a prepreg, which is a treated glass fiber cloth, impregnated with resin glue, and then heat-treated (pre-baking) to make the resin enter the semi-curing stage.
  • the thin sheet material is called a prepreg, which softens under heating and pressure, and reacts and solidifies after cooling.
  • a cavity 240 is formed on the dielectric layer 100 by means of laser drilling, and the bottom of the cavity 240 is flush with the upper surface of the first circuit layer 210. It should be noted that the size of the bottom opening of the cavity 240 is smaller than the size of the top opening to form a trapezoidal cavity 240 structure, which can also realize the extraction of the pins of the electronic components.
  • Step S203 remove the carrier board 700, deposit metal on the surface and sidewalls of the cavity 240 and the surface of the dielectric layer 100, and perform pattern fabrication and etching to form the second circuit layer 220.
  • the carrier board is 700 is removed, so that the lower surface of the first circuit layer 210 and the lower surface of the dielectric layer 100 are on the same plane, and a seed layer 500 is formed in the cavity 240 and the upper surface of the dielectric layer 100 by sputtering or electroless plating, and the seed layer 500 A metal layer is electroplated on the entire upper surface, and the deposition thickness can be set according to the actual design.
  • the deposition thickness is between 15-30um, as shown in FIG.
  • the surface and the lower surface of the dielectric layer 100 are adhered to the photosensitive dry film 600 at the same time, and the photosensitive dry film 600 on the upper surface is patterned, the excess metal layer and the seed layer 500 are removed by etching, the second circuit layer 220 is formed, and the film is removed to remove the upper surface. and the photosensitive dry film 600 on the lower surface.
  • Step S204 respectively forming a first solder resist layer 310 and a second solder resist layer 320 on the surfaces of the first circuit layer 210 and the second circuit layer 220 , and performing the process on the first solder resist layer 310 or the second solder resist layer 320 .
  • Pads 330 are formed by pattern fabrication. Specifically, as shown in FIG. 15 , a solder resist layer is applied on the upper and lower surfaces of the substrate, and specific pads 330 are formed by a photolithography process. The protective layer 400 is applied on the surface of 330 .
  • Step S205 cutting the cavity 240 , the first circuit layer 210 , the second circuit layer 220 , the first solder resist layer 310 and the second solder resist layer 320 , specifically, as shown in FIG. 16 , the mounting of electronic components is performed , install the pins of the electronic components at the position of the pad 330 and use plastic sealing material for plastic packaging, and cut the position of the cavity 240 to form a packaging unit, and point the pins of the electronic components to the first circuit layer 210 and the first circuit layer 210 and the first circuit layer 210. Both ends of the two circuit layers 220 .

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Abstract

本申请公开了一种封装基板制作方法，该方法包括步骤：提供承载板，在承载板上制作第一线路层；在第一线路层上表面制作金空腔图案，沉积并刻蚀金属形成金属腔体，在金属腔体表面压合介质层并减薄，露出金属腔体上表面；去除承载板，刻蚀掉金属腔体露出空腔，在空腔表面和侧壁以及介质层表面沉积金属并进行图案制作和刻蚀，形成第二线路层；分别在第一线路层和第二线路层表面对应形成第一阻焊层和第二阻焊层并对第一阻焊层或第二阻焊层进行图案制作形成焊盘；切割空腔、第一线路层、第二线路层、第一阻焊层和第二阻焊层。本申请的封装基板制作方法可以将封装器件的焊接测试点连接至基板侧边，通过基板侧边进行电子元器件与PCB的焊接检测。

Description

封装基板制作方法 技术领域
本申请涉及半导体封装技术领域，尤其涉及一种封装基板制作方法。
技术背景
随着微电子技术的不断发展，电子工业日趋复杂化和小型化，尤其是在移动电话和携带型电脑等移动设备中，集成了越来越多的半导体器件。作为电子设备核心的芯片也越来越复杂，需要越来越多的输入输出触点，以支持更多的功能需求。
芯片封装体根据引脚的类型可分成有引脚封装和无引脚封装，相对于有引脚封装，无引脚封装半导体器件具有引线电感低、热传导良好以及封装厚度轻薄的优点，可以降低在PCB(印刷电路板)上的占用面积。
无引线封装半导体器件常见有以Leadframe(引线框架)为基底完成封装的QFN(方形扁平无引线器件)以及以有机封装基板为基底完成的LGA(Land Grid Array，栅格阵列封装)和BGA(Ball Grid Array，球栅阵列封装)，对于前者，在将QFN安装在PCB上后可使用自动光学检查系统对其焊接状况进行缺陷检测；而对于后者，因LGA和BGA的管脚设计避开了封装体边缘无法露出，从而存在检测盲区。
申请内容
本申请旨在至少在一定程度上解决相关技术中的技术问题之一。为此，本申请提出一种封装基板制作方法，以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。所述技术方案如下：
第一方面，本申请实施例提供一种封装基板制作方法，包括以下步骤：
提供承载板，在承载板上制作第一线路层的图案，沉积金属，形成第一线路层；
在第一线路层上表面制作金空腔图案，沉积并刻蚀金属形成金属腔体，在所述金属腔体表面压合介质层并减薄，露出所述金属腔体上表面；
去除所述承载板，刻蚀掉所述金属腔体露出空腔，在所述空腔表面和侧壁以及介质层表面沉积金属并进行图案制作和刻蚀，形成第二线路层；
分别在所述第一线路层和所述第二线路层表面对应形成第一阻焊层和第二阻焊层并对所述第一阻焊层或所述第二阻焊层进行图案制作形成焊盘；
切割所述空腔、所述第一线路层、所述第二线路层、所述第一阻焊层和所述第二阻焊层。
根据本申请第一方面实施例的封装基板制作方法，至少具有以下有益效果：第一方面，本申请提出的封装基板可以把电子元器件的引脚焊点引出到封装基板的侧边，方便光学检测，直接判断焊接状 况；第二方面，本申请可在封装基板上完成多层线路的再分布，适用于引线键合和芯片的管芯封装，以及多芯片和多器件的集成封装，提高了基板功能的多元化和集成化；第三方面，本申请提出的封装基板封装流程简单，节省生产成本。
可选地，在本申请的一个实施例中，所述沉积金属包括依次沉积金属种子层和沉积线路层。
可选地，在本申请的一个实施例中，所述金属种子层材料包括金属钛和金属铜。
可选地，在本申请的一个实施例中，还包括形成保护层，所述保护层设置在所述线路层和所述焊盘表面。
可选地，在本申请的一个实施例中，所述保护层材料包括镍钯金、镍金、锡、银、有机保焊膜。
可选地，在本申请的一个实施例中，沉积金属的方式包括以下至少之一：
通过物理溅射进行金属沉积；
通过化学电镀进行金属沉积。
第二方面，本申请实施例提供了另外一种封装基板制作方法，包括以下步骤：
提供承载板，在承载板上制作第一线路层的图案，沉积金属，形成第一线路层；
在所述第一线路层上表面层压介质层，对所述介质层进行钻孔，形成空腔；
去除所述承载板，在所述空腔表面和侧壁以及介质层表面沉积金属并进行图案制作和刻蚀，形成第二线路层和第三线路层；分别在所述第一线路层和所述第二线路层表面对应形成第一阻焊层和第二阻焊层并对所述第一阻焊层或所述第二阻焊层进行图案制作形成焊盘；切割所述空腔、所述第一线路层、所述第二线路层、所述第一阻焊层和所述第二阻焊层。
根据本申请第二方面实施例的封装基板制作方法，至少具有以下有益效果：第一方面，本申请提出的封装基板可以把电子元器件的引脚焊点引出到封装基板的侧边，方便光学检测，直接判断焊接状况；第二方面，本申请可在封装基板上完成多层线路的再分布，适用于引线键合和芯片的管芯封装，以及多芯片和多器件的集成封装，提高了基板功能的多元化和集成化；第三方面，本申请提出的封装基板封装流程简单，节省生产成本。
可选地，在本申请的一个实施例中，采用激光钻孔的方式对所述介质层进行钻孔。
可选地，在本申请的一个实施例中，所述介质层材料包括半固化片、薄膜型树脂和聚乙烯树脂。
可选地，在本申请的一个实施例中，所述介质层(100)厚度在180um到250um之间。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1是本申请一个实施例提供的封装基板的截面图；
图2至图11是本申请另一个实施例提供的封装基板制作方法步骤对应的截面图；
图12至图16是本申请另一个实施例提供的封装基板制作方法步骤对应的截面图。
介质层100、第一线路层210、第二线路层220、第一阻焊层310、第二阻焊层320、焊盘330、金属腔体230、空腔240、保护层400、种子层500、感光干膜600、承载板700。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。
本部分将详细描述本申请的具体实施例，本申请之较佳实施例在附图中示出，附图的作用在于用图形补充说明书文字部分的描述，使人能够直观地、形象地理解本申请的每个技术特征和整体技术方案，但其不能理解为对本申请保护范围的限制。
在申请的描述中，若干的含义是一个或者多个，多个的含义是两个及两个以上，大于、小于、超过等理解为不包括本数，以上、以下、以内等理解为包括本数。如果有描述到第一、第二只是用于区分技术特征为目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量或者隐含指明所指示的技术特征的先后关系。
参照图1，本申请的一个实施例提供的一种封装基板，包括介质层100；线路层，包括分别设置在介质层100的上表面和下表面的第一线路层210和第二线路层220，其中第一线路层210从介质层100上表面水平层延伸出介质层100两端，第二线路层220从介质层100下表面开始延伸经过介质层100侧壁与第一线路层210重合，形成侧翼结构；阻焊层，包括第一阻焊层310和第二阻焊层320，分别设置在第一线路层210和第二线路层220表面，在第一阻焊层310或者第二阻焊层320其中之一设置有焊盘330，焊盘330与线路层连接。
在一实施例中，介质层100的上表面和下表面分别覆盖有第一线路层210和第二线路层220，并且在第一线路层210和第二线路层220表面设置有阻焊层和焊盘330，其中焊盘330与第一线路层210连通，用于与安装在封装基板上的电子元器件的引脚进行连接，第一线路层210从介质层100上表面水平层延伸出介质层100两端，第二线路层220从介质层100下表面开始延伸经过介质层100侧壁与第一线路层210重合，形成侧翼结构，第一线路层210和第二线路层220将介质层100包裹在内部，介质层100与侧翼结构构成滑槽空腔240结构，当安装LGA或者BGA等引脚位置非侧边露出的半导体电子元器件时，位于器件下表面的引脚与焊盘330连接，焊盘330与第一线路层210连接，第一线路层210又由侧翼结构引出，进而将电子元器件的电气特性引出至介质层100两侧边的侧翼结构上， 在进行PCB焊接时，只需将空腔240结构中的第二线路层220表面浸润焊接材料即可，焊接材料包括锡铅焊料、银焊料、铜焊料等。
参照图1，本申请的一个实施例提供了一种封装基板，第一线路层210和第二线路层220分别包括由绝缘材料隔开的第一线路层第一端和第一线路层第二端以及第二线路层第一端和第二线路层第二端。
在一实施例中，第一线路层210和第二线路层220分别包括两部分，第一线路层210的两部分分别对应设置在两个焊盘的下表面，两个焊盘分别连接电子元器件的正极和负极引脚上，通过第一线路层第一端和第一线路层第二端将电子元器件的正极和负极引出至基板的两侧边，与第二线路层第一端和第二线路层第二端进行连接，实现电性区别，需要说明的是，当基板上存在多个焊盘及及对应连接多个电子元器件时，第一线路层或者第二线路层可以由两部分组成，对应连接同一个电子元器件的正负极，第一线路层或者第二线路层也可以非断开结构，由一层金属形成的条状结构，与两个以及焊盘连接，两个焊盘分别对应一个电子元器件的正极(负极)和另外一个电子元器件的负极(正极)，进行多个电子元件的电气连接。
参照图1，本申请的一个实施例提供了一种封装基板，还包括保护层400，保护层400设置在线路层和焊盘330表面，在一实施例中，在第二线路层220和焊盘330的表面覆盖有一层保护层400，通过覆盖保护层400可以防止裸露在外的第二线路层220或者焊盘330氧化，增强基板的可靠性。
参照图1，本申请的一个实施例提供了一种封装基板，保护层400材料包括镍钯金、镍金、锡、银、有机保焊膜。
基于上述封装基板，提出本申请的封装基板制作方法的各个实施例。
参照图2至图11，本申请的另一个实施例还提供了一种封装基板制作方法，该方法包括但不限于以下步骤：
步骤S101，提供承载板700，在承载板700上制作第一线路层210的图案，沉积金属，形成第一线路层210，具体地，如图2所示，在承载板700上表面施加感光干膜600，通过曝光显影的方式形成第一线路层210图案，然后通过电镀的方式形成第一线路层210，需要说明的是，承载板700两面包含可拆卸的双层覆铜板，在承载板700的两面尽可以形成第一线路层210，在本申请的一个实施例中，优选的，以单面为例来描述制作步骤。
步骤S102，在第一线路层210上表面制作空腔240图案，沉积并刻蚀金属形成金属腔体230，在金属腔体230表面压合介质层100并减薄，露出金属腔体230上表面，具体地，如图3所示，在感光干膜600上继续粘附一层感光干膜600，通过曝光显影的方式进行空腔240图案制作，通过电镀或者化学镀的方式形成保护层400，再电镀形成金属腔体230，利用退膜药水去除第一感光干膜600和第二感光干膜600，暴露金属腔体230上表面和侧壁，如图4所示，堆叠和层压介质层100，如图5所示，通过磨板工艺减薄和平坦化电介质材料，直至露出条形金属腔体230上表面，使金属腔体230 上表面与介质层100上表面处于同一平面，将承载板700与介质层100分离，使第一线路层210与介质层100下表面处于同一表面。
需要说明的是，保护层400材料为化学特性不活泼的金属，例如镍、钛等，介质层100材料包括包括半固化片(PP)、薄膜型树脂(ABF)或者环氧树脂(PID)，半固化片和薄膜型树脂可以通过等离子刻蚀、磨板抛光或者激光钻孔等方式进行减薄，环氧树脂可通过曝光显影等方式进行减薄处理，在本申请的一个实施例中，优选的，使用半固化片作为介质层100，层压厚度在180‐250um之间，半固化片是经过处理的玻纤布浸渍上树脂胶液，再经热处理(预烘)使树脂进入半固化阶段而制成的薄片材料，其在加热加压下会软化，冷却后会反应固化。
步骤S103，去除承载板700，刻蚀掉金属腔体230露出空腔240，在空腔240表面和侧壁以及介质层100表面沉积金属并进行图案制作和刻蚀，形成第二线路层220，具体地，如图6所示，在包含有第一金属层的介质层100下表面贴覆感光干膜600，通过光刻工艺固化感光干膜600，感光干膜600采用整板曝光目的是为了保护第一线路层210，利用金属蚀刻液蚀刻除金属腔体230，形成空腔240。空腔240的侧壁垂直，底部尺寸和顶部尺寸一致，空腔240由底层镍金属保护层400和侧壁有机树脂介质层100组成，如图7所示，使用镍蚀刻药液去除镍金属保护层400，露出第一线路层210上表，再用退膜药水去除感光干膜600，露出第一线路层210下表面，如图8所示，在第一线路层210上表面和介质层100上表面通过溅射或者化学电镀的方式形成种子层500，种子层500包括钛、铜等金属，但不限于上述金属，在线第一线路层210下表面一侧粘附感光干膜600，整版曝光，保护第一线路层210，再通过整板电镀在种子层500上表面沉淀金属铜层，如图9所示，在金属铜层上表面一侧粘附感光干膜600，光刻形成特定的图案，使用蚀刻工艺蚀刻金属铜层和种子层500，形成第二线路层220，使用退膜药水退除上下表面的感光干膜600。
需要说明的是，沉积金属的方式包括物理溅射和化学电镀，优选的，本申请的一个实施例采用化学电镀进行金属层沉积。
步骤S104，分别在第一线路层210和第二线路层220表面对应形成第一阻焊层310和第二阻焊层320并对第一阻焊层310或第二阻焊层320进行图案制作形成焊盘330，具体地，如图10所示，在第一线路层210和第二线路层220表面分别施加第一阻焊层310和第二阻焊层320并对第一阻焊层310特定位置形成焊盘330用于与第一线路层210连接，进一步对焊盘330表面和第二线路层220表面进行金属表面处理，形成保护层400，表面处理的包括沉积镍钯金、镍金、锡、银等化学稳定的金属，还包括使用有机保焊膜进行表面覆盖。
步骤S105，切割空腔240、第一线路层210、第二线路层220、第一阻焊层310和第二阻焊层320，具体地，如图11所示，进行电子元器件的贴装，将电子元器件的引脚安装在焊盘330位置处并使用塑封材料进行塑封，并对空腔240位置进行切割形成封装单元，将电子元器件的引脚指出至第一线路层210和第二线路层220的切割两端。
参照图2、图12至图16，本申请的另一个实施例还提供了另外一种封装基板制作方法，该方法包括但不限于以下步骤：
步骤S201，提供承载板700，在承载板700上制作第一线路层210的图案，沉积金属，形成第一线路层210，具体地，如图2所示，在承载板700上施加感光干膜600，通过曝光显影的方式形成第一线路层210图案，然后通过电镀的方式形成第一线路层210。
步骤S202，在第一线路层210上表面层压介质层100，对介质层100进行钻孔，形成空腔240，具体地，如图12所示，堆叠和层压介质层100，介质层100根据设计需要进行调整，优选的，在本申请的一个实施例中，介质层100厚度在180‐250um之间，介质层100材料包括半固化片或薄膜型树脂等热固性有机树脂或者聚乙烯等热塑性有机树脂，优选的，在本申请的一个实施例中，介质层100采用半固化片，半固化片是经过处理的玻纤布，浸渍上树脂胶液，再经热处理(预烘)使树脂进入半固化阶段而制成的薄片材料称为半固化片，其在加热加压下会软化，冷却后会反应固化，对介质层100通过激光钻孔的方式形成空腔240，空腔240底部与第一线路层210上表面齐平，需要说明的是，空腔240的底部开口尺寸小于顶部开口尺寸形成梯形空腔240结构，同样可以实现电子元器件引脚的引出。
步骤S203，去除承载板700，在空腔240表面和侧壁以及介质层100表面沉积金属并进行图案制作和刻蚀，形成第二线路层220，具体地，如图13所示，将承载板700移除，使第一线路层210下表面和介质层100下表面处于同一平面，通过溅射或者化学镀的方式在空腔240内和介质层100上表面形成种子层500，在种子层500上表面整板电镀沉积金属层，沉积厚度可根据实际设计进行设定，在本申请的一个实施例中，优选的，沉积厚度在15‐30um之间，如图14所示，在金属层上表面和介质层100下表面同时粘附感光干膜600，并对上表面感光干膜600进行图案制作，蚀刻去除多余的金属层和种子层500，形成第二线路层220，退膜去除上表面和下表面的感光干膜600。
步骤S204，分别在第一线路层210和第二线路层220表面对应形成第一阻焊层310和第二阻焊层320并对第一阻焊层310或所述第二阻焊层320进行图案制作形成焊盘330，具体地，如图15所示，在基板上下表面施加阻焊层，通过光刻工艺形成特定焊盘330，通过表面处理工艺，在第二线路层220表面和焊盘330表面施加保护层400。
步骤S205，切割空腔240、第一线路层210、第二线路层220、第一阻焊层310和第二阻焊层320，具体地，如图16所示，进行电子元器件的贴装，将电子元器件的引脚安装在焊盘330位置处并使用塑封材料进行塑封，并对空腔240位置进行切割形成封装单元，将电子元器件的引脚指出至第一线路层210和第二线路层220两端。
以上是对本申请的较佳实施进行了具体说明，但本申请并不局限于上述实施方式，熟悉本领域的技术人员在不违背本申请精神的前提下还可作出种种的等同变形或替换，这些等同的变形或替换均包含在本申请权利要求所限定的范围内。

Claims (10)

  1. 一种封装基板制作方法，其特征在于，包括以下步骤：
    提供承载板(700)，在所述承载板(700)上制作第一线路层(210)的图案，沉积金属，形成第一线路层(210)；
    在第一线路层(210)上表面制作空腔(240)图案，沉积并刻蚀金属形成金属腔体(230)，在所述金属腔体(230)表面压合介质层(100)并减薄，露出所述金属腔体(230)上表面；
    去除所述承载板(700)，刻蚀掉所述金属腔体(230)露出空腔(240)，在所述空腔(240)表面和侧壁以及介质层(100)表面沉积金属并进行图案制作和刻蚀，形成第二线路层(220)；
    分别在所述第一线路层(210)和所述第二线路层(220)表面对应形成第一阻焊层(310)和第二阻焊层(320)并对所述第一阻焊层(310)或所述第二阻焊层(320)进行图案制作形成焊盘(330)；
    切割所述空腔(240)、所述第一线路层(210)、所述第二线路层(220)、所述第一阻焊层(310)和所述第二阻焊层(320)。
  2. 根据权利要求1所述的封装基板制作方法，其特征在于，所述沉积金属包括依次沉积金属种子层(500)和沉积线路层。
  3. 根据权利要求2所述的封装基板制作方法，其特征在于，所述金属种子层(500)材料包括金属钛和金属铜。
  4. 根据权利要求1所述的封装基板制作方法，其特征在于，还包括分别设置在所述线路层和所述焊盘(330)表面的保护层(400)。
  5. 根据权利要求4所述的封装基板制作方法，所述保护层(400)材料包括镍钯金、镍金、锡、银、有机保焊膜。
  6. 根据权利要求1所述的封装基板制作方法，其特征在于，沉积金属的方式包括以下至少之一：
    通过物理溅射进行金属沉积；
    通过化学电镀进行金属沉积。
  7. 一种封装基板制作方法，其特征在于，包括以下步骤：
    提供承载板(700)，在所述承载板(700)上制作第一线路层(210)的图案，沉积金属，形成第一线路层(210)；
    在所述第一线路层(210)上表面层压介质层(100)，对所述介质层(100)进行钻孔，形成空腔(240)；
    去除所述承载板(700)，在所述空腔(240)表面和侧壁以及介质层(100)表面沉积金属并进行图案制作和刻蚀，形成第二线路层(220)；
    分别在所述第一线路层(210)和所述第二线路层(220)表面对应形成第一阻焊层(310)和第二阻焊层(320)并对所述第一阻焊层(310)或所述第二阻焊层(320)进行图案制作形成焊盘(330)；
    切割所述空腔(240)、所述第一线路层(210)、所述第二线路层(220)、所述第一阻焊层(310)和所述第二阻焊层(320)。
  8. 根据权利要求7所述的封装基板制作方法，其特征在于，采用激光钻孔的方式对所述介质层(100)进行钻孔。
  9. 根据权利要求7所述的封装基板制作方法，其特征在于，所述介质层(100)材料包括半固化片、薄膜型树脂和聚乙烯树脂。
  10. 根据权利要求9所述的封装基板制作方法，其特征在于，所述介质层(100)厚度在180um到250um之间。
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