JP3877717B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP3877717B2 JP3877717B2 JP2003339123A JP2003339123A JP3877717B2 JP 3877717 B2 JP3877717 B2 JP 3877717B2 JP 2003339123 A JP2003339123 A JP 2003339123A JP 2003339123 A JP2003339123 A JP 2003339123A JP 3877717 B2 JP3877717 B2 JP 3877717B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- wiring
- pad electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/09—Treatments involving charged particles
- H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/906—Cleaning of wafer as interim step
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
(i)コアレスで実装できるため、トランジスタ、IC、LSIの小型・薄型化を実現できる。
(ii)トランジスタからシステムLSI、さらにチップタイプのコンデンサや抵抗を回路形成し、パッケージングすることができるため、高度なSIP(System in Package)を実現できる。
(iii)現有の半導体チップを組合せできるため、システムLSIを短期間に開発できる。
(iv)単層ISB構造とした場合、半導体ベアチップが直下の銅材に直接マウントされており、良好な放熱性を得ることができる。
(v)回路配線が銅材でありコア材がないため、低誘電率の回路配線となり、高速データ転送や高周波回路で優れた特性を発揮する。
(vi)電極がパッケージの内部に埋め込まれる構造のため、電極材料のパーティクルコンタミの発生を抑制できる。
(vii)パッケージサイズはフリーであり、1個あたりの廃材を64ピンのSQFPパッケージと比較すると、約1/10の量となるため、環境負荷を低減できる。
(viii)部品を載せるプリント回路基板から、機能の入った回路基板へと、新しい概念のシステム構成を実現できる。
(ix)ISBのパターン設計は、プリント回路基板のパターン設計と同じように容易であり、セットメーカーのエンジニアが自ら設計できる。
バイアス: 無印加
プラズマガス: アルゴン10〜20sccm、酸素0〜10sccm
Claims (5)
- 配線および層間絶縁膜からなる配線構造体と、
前記配線構造体の少なくとも一部を覆う被覆絶縁膜と、
前記配線構造体の表面または前記被覆絶縁膜の表面に設けられ、前記配線に接続するパッド電極と、
前記被覆絶縁膜の上に形成された半導体チップと、
前記パッド電極および前記半導体チップを電気的に接続する導電部材と、
を備え、
前記配線構造体の前記半導体チップが形成された面と反対の面に導電性膜が形成され、
前記パッド電極は、電極膜およびその表面に形成された導電性保護膜とを含み、前記導電部材の一端が前記導電性保護膜に接して形成されており、
前記被覆絶縁膜の表面がプラズマ処理面であって、前記導電性保護膜の表面が耐プラズマ性材料からなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記被覆絶縁膜は凹部を有し、前記パッド電極は前記凹部の内部に設けられ、前記凹部の内壁と前記パッド電極の側面との間に空隙部が設けられたことを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記被覆絶縁膜の表面に、微小突起群が形成されていることを特徴とする半導体装置。 - 請求項1乃至3のいずれかに記載の半導体装置において、
前記導電性保護膜は、前記電極膜上に形成された密着膜と、該密着膜上に形成され前記導線性保護膜の最表面を構成する被覆膜とを含むことを特徴とする半導体装置。 - 基材上に導電性膜、配線および層間絶縁膜からなる配線構造体を形成する工程と、
前記配線構造体の少なくとも一部を覆う被覆絶縁膜を形成する工程と、
前記配線構造体の表面または前記被覆絶縁膜の表面に、前記配線に接続し、電極膜およびその表面に形成された導電性保護膜を含むパッド電極を形成する工程と、
前記被覆絶縁膜の表面および前記パッド電極の表面が露出した状態でプラズマ処理を行う工程と、
前記被覆絶縁膜および前記パッド電極を含む面を封止樹脂で封止する工程と、
前記基材を剥離して前記導電性膜を露出させる工程と、
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003339123A JP3877717B2 (ja) | 2003-09-30 | 2003-09-30 | 半導体装置およびその製造方法 |
TW093128410A TWI248140B (en) | 2003-09-30 | 2004-09-20 | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
KR1020040077129A KR100644311B1 (ko) | 2003-09-30 | 2004-09-24 | 반도체 칩을 적층한 반도체 장치 및 그 제조 방법 |
US10/951,541 US7405484B2 (en) | 2003-09-30 | 2004-09-28 | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
CN2008101455117A CN101393871B (zh) | 2003-09-30 | 2004-09-30 | 层积半导体芯片的半导体装置制造方法 |
CNB2004100833596A CN100421249C (zh) | 2003-09-30 | 2004-09-30 | 层积半导体芯片的半导体装置及其制造方法 |
US12/143,603 US7939373B2 (en) | 2003-09-30 | 2008-06-20 | Manufacturing method for semiconductor device containing stacked semiconductor chips |
US13/095,657 US20110263121A1 (en) | 2003-09-30 | 2011-04-27 | Manufacturing method for semiconductor device containing stacked semiconductor chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003339123A JP3877717B2 (ja) | 2003-09-30 | 2003-09-30 | 半導体装置およびその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006173798A Division JP4413206B2 (ja) | 2006-06-23 | 2006-06-23 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005109067A JP2005109067A (ja) | 2005-04-21 |
JP3877717B2 true JP3877717B2 (ja) | 2007-02-07 |
Family
ID=34373339
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003339123A Expired - Fee Related JP3877717B2 (ja) | 2003-09-30 | 2003-09-30 | 半導体装置およびその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (3) | US7405484B2 (ja) |
JP (1) | JP3877717B2 (ja) |
KR (1) | KR100644311B1 (ja) |
CN (2) | CN101393871B (ja) |
TW (1) | TWI248140B (ja) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
SG142140A1 (en) | 2003-06-27 | 2008-05-28 | Semiconductor Energy Lab | Display device and method of manufacturing thereof |
TWI358776B (en) * | 2003-11-08 | 2012-02-21 | Chippac Inc | Flip chip interconnection pad layout |
US8853001B2 (en) * | 2003-11-08 | 2014-10-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
US8026128B2 (en) | 2004-11-10 | 2011-09-27 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
US20070105277A1 (en) | 2004-11-10 | 2007-05-10 | Stats Chippac Ltd. | Solder joint flip chip interconnection |
US8350384B2 (en) | 2009-11-24 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US8216930B2 (en) | 2006-12-14 | 2012-07-10 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
JP4928945B2 (ja) | 2003-11-10 | 2012-05-09 | スタッツ・チップパック・インコーポレイテッド | バンプ−オン−リードフリップチップ相互接続 |
USRE44500E1 (en) | 2003-11-10 | 2013-09-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
US7659633B2 (en) | 2004-11-10 | 2010-02-09 | Stats Chippac, Ltd. | Solder joint flip chip interconnection having relief structure |
USRE47600E1 (en) | 2003-11-10 | 2019-09-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming electrical interconnect with stress relief void |
US8574959B2 (en) | 2003-11-10 | 2013-11-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming bump-on-lead interconnection |
US9029196B2 (en) | 2003-11-10 | 2015-05-12 | Stats Chippac, Ltd. | Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask |
TWI262041B (en) * | 2003-11-14 | 2006-09-11 | Hitachi Chemical Co Ltd | Formation method of metal layer on resin layer, printed wiring board, and production method thereof |
KR20070107154A (ko) | 2005-03-25 | 2007-11-06 | 스태츠 칩팩, 엘티디. | 기판상에 좁은 상호접속 사이트를 갖는 플립 칩 상호접속체 |
US8841779B2 (en) | 2005-03-25 | 2014-09-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate |
US9258904B2 (en) * | 2005-05-16 | 2016-02-09 | Stats Chippac, Ltd. | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings |
US20060255473A1 (en) | 2005-05-16 | 2006-11-16 | Stats Chippac Ltd. | Flip chip interconnect solder mask |
JP2007067147A (ja) * | 2005-08-31 | 2007-03-15 | Shinko Electric Ind Co Ltd | プリント配線基板およびその製造方法 |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
CN1997271B (zh) * | 2006-01-06 | 2010-07-21 | 聚鼎科技股份有限公司 | 散热装置和其制作方法 |
CN101079460B (zh) * | 2006-05-23 | 2010-05-12 | 台达电子工业股份有限公司 | 发光装置 |
CN101079461B (zh) * | 2006-05-23 | 2010-05-12 | 台达电子工业股份有限公司 | 发光装置 |
US7902660B1 (en) * | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US8349721B2 (en) * | 2008-03-19 | 2013-01-08 | Stats Chippac, Ltd. | Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding |
US7759137B2 (en) * | 2008-03-25 | 2010-07-20 | Stats Chippac, Ltd. | Flip chip interconnection structure with bump on partial pad and method thereof |
US9345148B2 (en) | 2008-03-25 | 2016-05-17 | Stats Chippac, Ltd. | Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad |
JP4876272B2 (ja) * | 2008-04-02 | 2012-02-15 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 印刷回路基板及びその製造方法 |
US7897502B2 (en) * | 2008-09-10 | 2011-03-01 | Stats Chippac, Ltd. | Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers |
US7786839B2 (en) * | 2008-12-28 | 2010-08-31 | Pratt & Whitney Rocketdyne, Inc. | Passive electrical components with inorganic dielectric coating layer |
US8659172B2 (en) * | 2008-12-31 | 2014-02-25 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material with solder mask patch |
US8198186B2 (en) * | 2008-12-31 | 2012-06-12 | Stats Chippac, Ltd. | Semiconductor device and method of confining conductive bump material during reflow with solder mask patch |
US20100237500A1 (en) * | 2009-03-20 | 2010-09-23 | Stats Chippac, Ltd. | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site |
US8039384B2 (en) | 2010-03-09 | 2011-10-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces |
US8409978B2 (en) | 2010-06-24 | 2013-04-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe |
US8492197B2 (en) | 2010-08-17 | 2013-07-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate |
US8435834B2 (en) | 2010-09-13 | 2013-05-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP |
US8127979B1 (en) * | 2010-09-25 | 2012-03-06 | Intel Corporation | Electrolytic depositon and via filling in coreless substrate processing |
US8693203B2 (en) | 2011-01-14 | 2014-04-08 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices |
US8472207B2 (en) | 2011-01-14 | 2013-06-25 | Harris Corporation | Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods |
JP2012156309A (ja) * | 2011-01-26 | 2012-08-16 | Nitto Denko Corp | 配線回路基板およびその製造方法ならびに燃料電池 |
JP6046406B2 (ja) * | 2011-07-26 | 2016-12-14 | ローム アンド ハース エレクトロニック マテリアルズ エルエルシーRohm and Haas Electronic Materials LLC | 高温耐性銀コート基体 |
KR101175909B1 (ko) * | 2011-07-27 | 2012-08-22 | 삼성전기주식회사 | 인쇄회로기판의 표면처리 방법 및 인쇄회로기판 |
US20130033671A1 (en) * | 2011-08-04 | 2013-02-07 | Endicott Interconnect Technologies, Inc. | Liquid crystal polymer (lcp) surface layer adhesion enhancement |
CN104112732A (zh) * | 2013-08-19 | 2014-10-22 | 广东美的集团芜湖制冷设备有限公司 | 集成电路模块及其制造方法 |
JP2015076576A (ja) * | 2013-10-11 | 2015-04-20 | パナソニックIpマネジメント株式会社 | 電気装置、電気装置の製造方法 |
JP2022071925A (ja) * | 2020-10-29 | 2022-05-17 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3918149A (en) * | 1974-06-28 | 1975-11-11 | Intel Corp | Al/Si metallization process |
US4908094A (en) * | 1986-04-14 | 1990-03-13 | International Business Machines Corporation | Method for laminating organic materials via surface modification |
US4894115A (en) * | 1989-02-14 | 1990-01-16 | General Electric Company | Laser beam scanning method for forming via holes in polymer materials |
JP3457348B2 (ja) * | 1993-01-15 | 2003-10-14 | 株式会社東芝 | 半導体装置の製造方法 |
US5485038A (en) * | 1993-07-15 | 1996-01-16 | Hughes Aircraft Company | Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers |
JP2698827B2 (ja) * | 1993-11-05 | 1998-01-19 | カシオ計算機株式会社 | バンプ電極を備えた半導体装置の製造方法 |
KR970000214B1 (ko) | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | 반도체 장치 및 그 제조방법 |
JP3444053B2 (ja) * | 1995-10-13 | 2003-09-08 | ソニー株式会社 | 薄膜半導体装置 |
JP2843315B1 (ja) * | 1997-07-11 | 1999-01-06 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
US5910341A (en) * | 1996-10-31 | 1999-06-08 | International Business Machines Corporation | Method of controlling the spread of an adhesive on a circuitized organic substrate |
JP2000039451A (ja) | 1998-07-22 | 2000-02-08 | Hoya Corp | バーンインボード用多層配線基板及びその製造方法 |
US6225661B1 (en) * | 1998-09-02 | 2001-05-01 | Advanced Micro Devices, Inc. | MOS transistor with stepped gate insulator |
JP2000216297A (ja) | 1999-01-21 | 2000-08-04 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6593658B2 (en) * | 1999-09-09 | 2003-07-15 | Siliconware Precision Industries, Co., Ltd. | Chip package capable of reducing moisture penetration |
US6406991B2 (en) * | 1999-12-27 | 2002-06-18 | Hoya Corporation | Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board |
TW515012B (en) * | 2000-09-08 | 2002-12-21 | Matsushita Electric Ind Co Ltd | Plasma-processing apparatus, plasma-processing method, and chip mounted method |
JP2002085803A (ja) | 2000-09-20 | 2002-03-26 | Kato Seisakusho:Kk | ゲーム機 |
JP2002270640A (ja) * | 2001-03-08 | 2002-09-20 | Hitachi Ltd | 半導体パッケージ及びその製造方法 |
JP3560563B2 (ja) * | 2001-05-08 | 2004-09-02 | シャープ株式会社 | 半導体装置及びその製造方法 |
JP2003007921A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US6869831B2 (en) * | 2001-09-14 | 2005-03-22 | Texas Instruments Incorporated | Adhesion by plasma conditioning of semiconductor chip surfaces |
US6921860B2 (en) * | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
US6853060B1 (en) * | 2003-04-22 | 2005-02-08 | Amkor Technology, Inc. | Semiconductor package using a printed circuit board and a method of manufacturing the same |
-
2003
- 2003-09-30 JP JP2003339123A patent/JP3877717B2/ja not_active Expired - Fee Related
-
2004
- 2004-09-20 TW TW093128410A patent/TWI248140B/zh not_active IP Right Cessation
- 2004-09-24 KR KR1020040077129A patent/KR100644311B1/ko not_active IP Right Cessation
- 2004-09-28 US US10/951,541 patent/US7405484B2/en not_active Expired - Fee Related
- 2004-09-30 CN CN2008101455117A patent/CN101393871B/zh not_active Expired - Fee Related
- 2004-09-30 CN CNB2004100833596A patent/CN100421249C/zh not_active Expired - Fee Related
-
2008
- 2008-06-20 US US12/143,603 patent/US7939373B2/en not_active Expired - Fee Related
-
2011
- 2011-04-27 US US13/095,657 patent/US20110263121A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US7405484B2 (en) | 2008-07-29 |
US20050067686A1 (en) | 2005-03-31 |
US20110263121A1 (en) | 2011-10-27 |
CN100421249C (zh) | 2008-09-24 |
TW200522228A (en) | 2005-07-01 |
JP2005109067A (ja) | 2005-04-21 |
CN1604320A (zh) | 2005-04-06 |
US7939373B2 (en) | 2011-05-10 |
CN101393871A (zh) | 2009-03-25 |
TWI248140B (en) | 2006-01-21 |
CN101393871B (zh) | 2011-07-13 |
US20080311737A1 (en) | 2008-12-18 |
KR100644311B1 (ko) | 2006-11-23 |
KR20050031963A (ko) | 2005-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3877717B2 (ja) | 半導体装置およびその製造方法 | |
TWI293796B (ja) | ||
JP4020874B2 (ja) | 半導体装置およびその製造方法 | |
US6784530B2 (en) | Circuit component built-in module with embedded semiconductor chip and method of manufacturing | |
JP3842548B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
US8183469B2 (en) | Wiring board and method of manufacturing the same | |
US20060012028A1 (en) | Device mounting board | |
JP2005322858A (ja) | 半導体装置の製造方法 | |
WO2022012422A1 (zh) | 封装基板制作方法 | |
US20090149034A1 (en) | Semiconductor module and method of manufacturing the same | |
US20060193108A1 (en) | Circuit device and manufacturing method thereof | |
JP2005268453A (ja) | 回路装置およびその製造方法 | |
JP4413206B2 (ja) | 半導体装置およびその製造方法 | |
JP2005109068A (ja) | 半導体装置およびその製造方法 | |
KR100592866B1 (ko) | 반도체 모듈 및 그 제조 방법 | |
JP4605176B2 (ja) | 半導体搭載基板及び半導体パッケージの製造方法並びに半導体パッケージ | |
JP4663172B2 (ja) | 半導体装置の製造方法 | |
JP2936540B2 (ja) | 回路基板及びその製造方法とこれを用いた半導体パッケージの製造方法 | |
JP4103482B2 (ja) | 半導体搭載基板とそれを用いた半導体パッケージ並びにそれらの製造方法 | |
JP4605177B2 (ja) | 半導体搭載基板 | |
JP2006245070A (ja) | 回路装置 | |
JP2006310890A (ja) | 半導体モジュールおよびその製造方法 | |
US20060284288A1 (en) | Wafer and single chip having circuit rearranged structure and method for fabricating the same | |
TWI307143B (en) | Method for manufacturing package substrate and for its chip package structure | |
JP2005286146A (ja) | 半導体装置および半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060417 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060425 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060626 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060718 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060822 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20060927 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20061017 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20061031 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101110 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101110 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111110 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111110 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121110 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121110 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131110 Year of fee payment: 7 |
|
LAPS | Cancellation because of no payment of annual fees |