JP5851211B2 - 半導体パッケージ、半導体パッケージの製造方法及び半導体装置 - Google Patents
半導体パッケージ、半導体パッケージの製造方法及び半導体装置 Download PDFInfo
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- JP5851211B2 JP5851211B2 JP2011247666A JP2011247666A JP5851211B2 JP 5851211 B2 JP5851211 B2 JP 5851211B2 JP 2011247666 A JP2011247666 A JP 2011247666A JP 2011247666 A JP2011247666 A JP 2011247666A JP 5851211 B2 JP5851211 B2 JP 5851211B2
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- insulating layer
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- interlayer insulating
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Description
このような半導体パッケージの一例としては、半導体チップの能動面(回路形成面)及び側面が絶縁層により覆われており、その絶縁層上に、半導体チップと電気的に接続された配線構造が積層されてなる構造が提案されている(例えば、特許文献1参照)。
例えば支持基板を準備し、その支持基板上に、半導体チップの能動面と反対側の面が支持基板の表面に接するように半導体チップを搭載する。続いて、搭載した半導体チップを絶縁層により封止し、絶縁層上に配線層と層間絶縁層とを積層して配線構造を形成する。そして、支持基板を除去することによって、半導体パッケージを製造する。
、前記半導体チップの搭載面とは反対側の最外層の前記層間絶縁層を厚さ方向に貫通する溝部と、前記溝部に充填されるとともに、前記最外層の層間絶縁層の上面に形成された埋込樹脂層と、を有し、前記埋込樹脂層は、前記最外層の層間絶縁層の上面に形成された最外層の配線層を被覆するとともに、前記最外層の配線層の一部を外部接続用パッドとして露出させる開口部を有し、前記埋込樹脂層は、前記層間絶縁層の熱膨張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有する。
(半導体パッケージの構造)
図1(a)に示すように、半導体パッケージ1は、半導体チップ2を有している。この半導体チップ2としては、例えばCPU(Central Processing Unit)チップやGPU(Graphics Processing Unit)チップなどのロジックチップを用いることができる。また、半導体チップ2としては、例えばDRAM(Dynamic Random Access Memory)チップ、SRAM(Static Random Access Memory)チップやフラッシュメモリチップなどのメモリチップを用いることができる。
半導体パッケージ1において、第1配線層10は、最外層(図1では最下層)に形成されている。この第1配線層10は、第1導電層10Aと第2導電層10Bとを有している。第1導電層10Aとしては、例えば金(Au)膜、ニッケル(Ni)膜を、Au膜が半導体パッケージ1の外部に露出するように、この順番で順次積層した導電層を用いることができる。また、第2導電層10Bとしては、例えばCu層等を含む導電層を用いることができる。なお、上記Au膜の厚さは例えば0.1〜1μm程度とすることができ、上記Ni膜の厚さは例えば1〜10μm程度とすることができる。また、第2導電層10B(Cu層)の厚さは例えば10〜40μm程度とすることができる。
次に、半導体装置3の構造を図2に従って説明する。なお、図2において、半導体パッケージ1は図1(a)とは上下を反転して描かれている。
半導体パッケージ4は、配線基板60と、その配線基板60にフリップチップ実装された第1の半導体チップ71と、第1の半導体チップ71の上に接着された第2の半導体チップ72とを有している。また、半導体パッケージ4は、第1の半導体チップ71と配線基板60との隙間を充填するように設けられたアンダーフィル樹脂73と、第1の半導体チップ71及び第2の半導体チップ72等を封止する封止樹脂74とを有している。なお、第1の半導体チップ71の平面形状は、第2の半導体チップ72の平面形状よりも大きく形成されている。
これに対し、本実施形態の半導体パッケージ1では、最外層の層間絶縁層である第4絶縁層41及びその第4絶縁層41の下層に形成された第3絶縁層31に、その第4絶縁層41を厚さ方向に貫通する溝部41Xを形成するようにした。これにより、第3絶縁層31及び第4絶縁層41が溝部41Xによって複数の領域に分断される。このため、溝部41Xが形成されずに第3絶縁層31及び第4絶縁層41が広い領域にわたって一体的に形成された場合と比較して、第3絶縁層31及び第4絶縁層41が収縮することによって生じる応力を緩和することができる。この結果、半導体パッケージ1に生じる反りを低減することができる。
次に、上記半導体パッケージ1の製造方法を説明する。
まず、半導体パッケージ1を製造するためには、図3(a)に示すように、支持基板80を用意する。この支持基板80としては、例えば金属板や金属箔を用いることができ、本実施形態では、例えば銅箔を用いる。この支持基板80の厚さは、例えば35〜200μm程度である。
(半導体装置の製造方法)
次に、図7(a)に示すように、半導体パッケージ4を用意する。ここでは、図示を省略して詳細な説明を割愛するが、半導体パッケージ4は例えば以下のような方法で製造される。すなわち、チップ用パッド62、ボンディング用パッド63及び外部接続端子64を有する配線基板60を形成し、その配線基板60の上面に形成されたチップ用パッド62に第1の半導体チップ71のバンプ71Aをフリップチップ接合する。続いて、配線基板60と第1の半導体チップ71との間にアンダーフィル樹脂73を形成した後、第1の半導体チップ71の上に第2の半導体チップ72を接着剤により接着する。次いで、第2の半導体チップ72の上面に形成された電極パッド(図示略)と配線基板60の上面に形成されたボンディング用パッド63との間をボンディングワイヤ75によりワイヤボンディング接続した後、第1及び第2の半導体チップ71,72及びボンディングワイヤ75等を封止樹脂74で樹脂封止する。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(8)溝部41Xの断面形状を略楔状に形成するようにした。これにより、第4絶縁層41及び第3絶縁層31を複数の領域に確実に分断することができる。このため、第3絶縁層31及び第4絶縁層41が収縮することによって生じる応力を効果的に緩和することができ、半導体パッケージ1に生じる反りを低減することができる。
なお、上記実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・図8に示されるように、上記実施形態における埋込樹脂層51を省略するようにしてもよい。このような構造であっても、上記実施形態の(1)、(3)〜(8)と同様の効果を奏することができる。
例えば上記実施形態では、第3絶縁層31及び第4絶縁層41の2層分の層間絶縁層に溝部41Xを形成するようにしたが、図10(a)に示されるように、3層以上の層間絶縁層に溝部41Xを形成するようにしてもよい。図10(a)に示した変形例では、溝部41Xは、第4絶縁層41の面41Aから第4絶縁層41及び第3絶縁層31を厚さ方向に貫通して、第2絶縁層21の厚さ方向の中途位置まで形成されている。このように溝部41Xが深く形成されると、その溝部41Xによって分断される層間絶縁層の数が増加するため、効果的に反りを抑制することができる。
・上記実施形態における半導体パッケージ4の配線基板60に実装される半導体チップの数や、その半導体チップの実装の形態(例えばフリップチップ実装、ワイヤボンディングによる実装、又はこれらの組み合わせ)などは様々に変形・変更することが可能である。
次に、実施例及び比較例を挙げて上記実施形態及びその変形例をさらに具体的に説明する。
実施例1の半導体パッケージは、図1(a)に示した半導体パッケージ1である。シミュレーション条件としては、半導体パッケージ1の平面形状を12mm×12mmの正方形状とし、半導体チップ2の平面形状を9mm×9mmの正方形状とし、半導体チップ2の厚さを100μmとした。また、半導体パッケージ1全体の厚さを550μmとした。具体的には、第2〜第5配線層20,30,40,50の厚さをそれぞれ15μmとし、第1絶縁層11の厚さを180μm、第2及び第3絶縁層21,31の厚さを30μm、第4絶縁層41の厚さを100μm、埋込樹脂層51の厚さを50μmとした。なお、溝部41XはCO2レーザによるレーザ加工により形成し、その溝部41Xの深さを120μmとした。
実施例2の半導体パッケージは、図8に示した半導体パッケージ1Aであり、実施例1の半導体パッケージから埋込樹脂層51を除去した構造を有している。シミュレーション条件としては、上記半導体パッケージ1Aを厚さ200μmの支持基板80に固定した状態で反りを測定する点のみが上記実施例1と異なる。
比較例1の半導体パッケージは、図13に示される半導体パッケージ5である。この半導体パッケージ5は、溝部41X(図1(a)参照)が形成されていない点を除き、実施例1の半導体パッケージ1と同一の構造を有する。なお、シミュレーション条件については、実施例1と同一の条件である。
比較例2の半導体パッケージは、図14に示される半導体パッケージ6である。この半導体パッケージ6は、溝部41X(図8参照)が形成されていない点を除き、実施例2の半導体パッケージ1Aと同一の構造を有する。なお、シミュレーション条件については、実施例2と同一の条件である。
各例の半導体パッケージを190℃の環境下に置いて応力を解放後、温度を25℃に下げたときの反りを測定した。反りは、各半導体パッケージの半導体チップ2の搭載されたチップ搭載面11Aとは反対側の面の高さを対角線に沿って順次測定し、最も高い点と最も低い点との高さの差を測定した。なお、チップ搭載面11Aとは反対側の面が凸状に沿った場合の反り量をプラスとし、チップ搭載面とは反対側の面が凹状に沿った場合の反り量をマイナスとして、図15にシミュレーション結果を示した。
図15に示すように、実施例1と比較例1、及び、実施例2と比較例2をそれぞれ比較すると、溝部41Xを設けることにより(実施例1,2)、溝部41Xを設けない場合(比較例1,2)に比べ、半導体パッケージの反り量を大幅に低減できることが確認された。すなわち、溝部41Xの形成によって、高い反り改善効果が得られることが確認された。
2 半導体チップ
4 半導体パッケージ(他の半導体パッケージ又は第2半導体パッケージ)
10 第1配線層
10P 接続パッド(パッド)
11 第1絶縁層
20,30,40,50 配線層
21 第2絶縁層(層間絶縁層)
31 第3絶縁層(層間絶縁層)
41 第4絶縁層(最外層の層間絶縁層)
41X 溝部
51 埋込樹脂層
80 支持基板
Claims (11)
- 半導体チップと、
前記半導体チップを覆うように形成された第1絶縁層と、
前記第1絶縁層上に積層され、前記半導体チップと電気的に接続された配線層と該配線層上に積層される層間絶縁層とが交互に積層されてなる配線構造と、を有し、
前記半導体チップの搭載面とは反対側の最外層の前記層間絶縁層を厚さ方向に貫通する溝部と、
前記溝部に充填されるとともに、前記最外層の層間絶縁層の上面に形成された埋込樹脂層と、を有し、
前記埋込樹脂層は、前記最外層の層間絶縁層の上面に形成された最外層の配線層を被覆するとともに、前記最外層の配線層の一部を外部接続用パッドとして露出させる開口部を有し、
前記埋込樹脂層は、前記層間絶縁層の熱膨張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有することを特徴とする半導体パッケージ。 - 半導体チップと、
前記半導体チップを覆うように形成された第1絶縁層と、
前記第1絶縁層上に積層され、前記半導体チップと電気的に接続された配線層と該配線層上に積層される層間絶縁層とが交互に積層されてなる配線構造と、を有し、
前記半導体チップの搭載面とは反対側の最外層の前記層間絶縁層には、該最外層の層間絶縁層を厚さ方向に貫通する溝部が形成され、
前記溝部は、前記最外層の層間絶縁層の下層に形成された層間絶縁層の厚さ方向の中途位置まで形成され、
前記最外層の層間絶縁層は、補強材入りの樹脂材からなり、他の前記層間絶縁層の熱膨
張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有する絶縁層であることを特徴とする半導体パッケージ。 - 前記溝部は、前記最外層の層間絶縁層の下層に形成された層間絶縁層を厚さ方向に貫通するように形成されていることを特徴とする請求項1に記載の半導体パッケージ。
- 前記最外層の層間絶縁層は、補強材入りの樹脂材からなり、他の前記層間絶縁層の熱膨
張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有する絶縁層であることを特徴とする請求項1又は3に記載の半導体パッケージ。 - 前記溝部は、前記半導体チップと対向する領域よりも外側の領域に形成されていることを特徴とする請求項1〜4のいずれか1つに記載の半導体パッケージ。
- 前記溝部は、断面視して楔状に形成されていることを特徴とする請求項1〜5のいずれか1つに記載の半導体パッケージ。
- 前記半導体チップと同一平面上に、他の半導体パッケージと接続されるパッドが形成されていることを特徴とする請求項1〜6のいずれか1つに記載の半導体パッケージ。
- 支持基板上に半導体チップを固定する工程と、
前記半導体チップが固定された前記支持基板上に、前記半導体チップを覆うように第1絶縁層を形成する工程と、
前記第1絶縁層上に、前記半導体チップと電気的に接続するように配線層と該配線層上に積層される層間絶縁層とを交互に積層する工程と、
前記層間絶縁層のうち最後に積層した最外層の層間絶縁層に、該最外層の層間絶縁層を厚さ方向に貫通する溝部を形成する工程と、
前記溝部を形成した後に、前記最外層の層間絶縁層の上面に、前記溝部を充填するように、且つ前記最外層の層間絶縁層の上面に形成された最外層の配線層を被覆するように埋込樹脂層を形成する工程と、
前記埋込樹脂層に、前記最外層の配線層の一部を外部接続用パッドとして露出させる開口部を形成する工程と、
前記支持基板を除去する工程と、
を有し、
前記埋込樹脂層は、前記層間絶縁層の熱膨張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有することを特徴とする半導体パッケージの製造方法。 - 支持基板上に半導体チップを固定する工程と、
前記半導体チップが固定された前記支持基板上に、前記半導体チップを覆うように第1絶縁層を形成する工程と、
前記第1絶縁層上に、前記半導体チップと電気的に接続するように配線層と該配線層上に積層される層間絶縁層とを交互に積層する工程と、
前記層間絶縁層のうち最後に積層した最外層の層間絶縁層に、該最外層の層間絶縁層を厚さ方向に貫通する溝部を形成する工程と、
前記支持基板を除去する工程と、
を有し、
前記溝部を形成する工程では、前記最外層の層間絶縁層の下層に形成された層間絶縁層の厚さ方向の中途位置まで前記溝部を形成し、
前記最外層の層間絶縁層は、補強材入りの樹脂材からなり、他の前記層間絶縁層の熱膨
張係数よりも前記半導体チップの熱膨張係数に近い熱膨張係数を有する絶縁層であることを特徴とする半導体パッケージの製造方法。 - 前記支持基板上に前記半導体チップを固定する工程の前に、前記支持基板上に他の半導体パッケージと接続されるパッドを形成する工程を有することを特徴とする請求項8又は9に記載の半導体パッケージの製造方法。
- 請求項1〜7のいずれか1つに記載の半導体パッケージと、
前記半導体パッケージ上に積層される他の半導体パッケージと、
を有することを特徴とする半導体装置。
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