JP6584939B2 - 配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 - Google Patents
配線基板、半導体パッケージ、半導体装置、配線基板の製造方法及び半導体パッケージの製造方法 Download PDFInfo
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- JP6584939B2 JP6584939B2 JP2015241424A JP2015241424A JP6584939B2 JP 6584939 B2 JP6584939 B2 JP 6584939B2 JP 2015241424 A JP2015241424 A JP 2015241424A JP 2015241424 A JP2015241424 A JP 2015241424A JP 6584939 B2 JP6584939 B2 JP 6584939B2
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- 239000004065 semiconductor Substances 0.000 title claims description 198
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000011347 resin Substances 0.000 claims description 172
- 229920005989 resin Polymers 0.000 claims description 172
- 238000007789 sealing Methods 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 50
- 229920001187 thermosetting polymer Polymers 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000005498 polishing Methods 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 676
- 229910052751 metal Inorganic materials 0.000 description 62
- 239000002184 metal Substances 0.000 description 62
- 229910000679 solder Inorganic materials 0.000 description 51
- 239000000463 material Substances 0.000 description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 36
- 239000010949 copper Substances 0.000 description 28
- 238000005530 etching Methods 0.000 description 26
- 238000007747 plating Methods 0.000 description 21
- 239000011889 copper foil Substances 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 17
- 239000002335 surface treatment layer Substances 0.000 description 17
- 238000012986 modification Methods 0.000 description 15
- 230000004048 modification Effects 0.000 description 15
- 239000010936 titanium Substances 0.000 description 15
- 230000003746 surface roughness Effects 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 239000000243 solution Substances 0.000 description 10
- 239000007864 aqueous solution Substances 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 9
- 238000009713 electroplating Methods 0.000 description 8
- 239000007788 liquid Substances 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 7
- 229910000881 Cu alloy Inorganic materials 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 238000007772 electroless plating Methods 0.000 description 6
- 239000000945 filler Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000000654 additive Substances 0.000 description 4
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 3
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000004745 nonwoven fabric Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000012779 reinforcing material Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000002759 woven fabric Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 2
- 239000004760 aramid Substances 0.000 description 2
- 229920003235 aromatic polyamide Polymers 0.000 description 2
- -1 azole compound Chemical class 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- KAESVJOAVNADME-UHFFFAOYSA-N 1H-pyrrole Natural products C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- VUCAVCCCXQVHAN-UHFFFAOYSA-L azane dichlorocopper Chemical compound N.Cl[Cu]Cl VUCAVCCCXQVHAN-UHFFFAOYSA-L 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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Description
以下、図1〜図14に従って第1実施形態について説明する。
図1に示した半導体パッケージ10は、例えば、パッケージオンパッケージ(POP)構造の半導体装置における下側の半導体パッケージである。この半導体パッケージ10は、配線基板20と、配線基板20に実装された半導体チップ50と、半導体チップ50の一部を被覆する封止樹脂60と、封止樹脂60及び配線基板20の一部の絶縁層を貫通する貫通孔60Xとを有している。
まず、配線構造21の構造について説明する。
配線構造23は、配線構造21の最上層に形成された絶縁層30の上面30Aに積層された配線構造である。配線構造23は、配線構造21よりも配線密度の高い配線層が形成された高密度配線層である。
ここで、絶縁層41,43の材料としては、例えば、フェノール系樹脂やポリイミド系樹脂等の感光性樹脂を主成分とする絶縁性樹脂を用いることができる。これら絶縁層41,43は、例えば、シリカやアルミナ等のフィラーを含有していてもよい。また、配線層40,42,44の材料としては、例えば、銅や銅合金を用いることができる。
配線層42は、絶縁層41の上面に形成されている。配線層42は、配線層40と電気的に接続されている。この配線層42は、貫通孔41X内に充填されたビア配線と、絶縁層41の上面に形成された配線パターンとを有している。
次いで、図5(d)に示す工程では、シード層107上に、所定の箇所に開口パターン108Xを有するレジスト層108を形成する。開口パターン108Xは、配線層40(図1参照)の形成領域に対応する部分のシード層107を露出するように形成される。このため、開口パターン108Xの一部は、配線層33の上面33Aの一部と平面視で重なるように形成される。レジスト層108の材料としては、例えば、次工程のめっき処理に対して耐めっき性がある材料を用いることができる。レジスト層108の材料としては、例えば、レジスト層103(図3(b)参照)と同様の材料を用いることができる。また、レジスト層108は、レジスト層103と同様の方法により形成することができる。本工程において、シード層107の上面が平滑面になっているため、そのシード層107上に形成されるレジスト層108にパターニング欠陥が生じることを抑制できる。すなわち、レジスト層108に開口パターン108Xを高精度に形成することができる。
次いで、金属層109をエッチングマスクとして、不要なシード層107をエッチングにより除去する。例えば、シード層107がTi層/Cu層からなる場合には、まず、硫酸過水系のエッチング液を用いたウェットエッチングによりCu層を除去する。その後、例えば、CF4等のエッチングガスを用いたドライエッチングや、KOH系のエッチング液を用いたウェットエッチングにより、Ti層を除去する。本工程により、図6(b)に示すように、ビア配線31の上端面31Aと配線層33の上面33Aの一部とに接触されたシード層107と、そのシード層107上に形成された金属層109とからなる配線層40が絶縁層30の上面30Aに形成される。このように、配線層40は、セミアディティブ法によって形成される。また、配線層40とビア配線31と配線層33とは別工程で形成されるため、配線層40とビア配線31と配線層33とは一体的に形成されていない。なお、これ以降の図6(c)〜図9(c)では、シード層107と金属層109の図示を省略し、配線層40として図示する。
図7(b)に示す工程では、まず、回路形成面に形成された接続端子51と、その接続端子51の下面に形成された接合部材52とを有する半導体チップ50を準備する。続いて、接続端子P2上に、半導体チップ50の接続端子51をフリップチップ接合する。例えば、接合部材52がはんだ層である場合には、接続端子P2と接続端子51とを位置合わせした後に、リフロー処理を行って接合部材52(はんだ層)を溶融させ、接続端子51を接続端子P2に電気的に接続する。
次に、図9(b)に示す工程では、配線層32の下面の一部を露出させるための開口部22Xを有するソルダレジスト層22を、絶縁層30の下面に積層する。このソルダレジスト層22は、例えば、感光性のソルダレジストフィルムをラミネートし、又は液状のソルダレジストを塗布し、当該レジストを所要の形状にパターニングすることにより形成することができる。これにより、ソルダレジスト層22の開口部22Xから配線層32の下面の一部が外部接続用パッドP1として露出される。なお、必要に応じて、外部接続用パッドP1上に表面処理層を形成するようにしてもよい。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(1)熱硬化性樹脂を主成分とする絶縁性樹脂からなる絶縁層30の上面30Aに凹部30Yを形成し、その凹部30YにPOP用の接続パッドとなる配線層33(パッド34)を形成した。このため、配線層33を有する半導体パッケージ10に別の半導体パッケージを接合する際に配線層33にかかる荷重を、機械的強度の高い熱硬化性樹脂からなる絶縁層30で受けることができる。これにより、配線層33に外力が加わった際に絶縁層30にクラック等の樹脂破壊が発生することを好適に抑制することができる。
あるいは、図14(a)及び図14(b)に示すように、配線層40(回路パターン440B)の下面を、配線層33の回路パターン36の上面の一部と接するように形成することもできる。例えば図14(a)に示すように、回路パターン36を横断するように回路パターン40Bを形成し、その横断する部分で回路パターン40Bの下面と回路パターン36の上面とを接続してもよい。なお、この場合には、図2に示したパッド35を省略することもできる。
以下、図15〜図18に従って第2実施形態を説明する。先の図1〜図14に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
半導体装置11は、半導体パッケージ10Aと、その半導体パッケージ10Aに接合された半導体パッケージ70と、半導体パッケージ10A,70間に形成された封止樹脂95と、外部接続端子96とを有している。
半導体パッケージ10Aと半導体パッケージ70との間の空間には、封止樹脂95が充填されている。この封止樹脂95によって、半導体パッケージ70が半導体パッケージ10Aに対して固定されるとともに、配線基板20に実装された半導体チップ50が封止される。すなわち、封止樹脂95は、半導体パッケージ10Aと半導体パッケージ70とを接着する接着剤として機能するとともに、半導体チップ50を保護する保護層として機能する。さらに、封止樹脂95を設けたことにより、半導体装置11全体の機械的強度を高めることができる。
次に、図18に従って、半導体装置11の製造方法について説明する。
その後、半導体パッケージ10Aの外部接続用パッドP1上に外部接続端子96(図16参照)を形成する。以上の製造工程により、図16に示した半導体装置11を製造することができる。
(7)感光性樹脂を主成分とする絶縁層41よりも機械特性の高い封止樹脂60の上面に接続パッドP3を形成し、別の半導体パッケージ70を接続パッドP3と貫通電極61を介してPOP用の配線層33(パッド34)に電気的に接続するようにした。このため、半導体パッケージ10Aの接続パッドP3に別の半導体パッケージ70を接合する際にPOP用の配線層33(パッド34)にかかる荷重を、絶縁層30だけでなく、機械的強度の高い封止樹脂60でも受けることができる。これにより、配線層33(パッド34)にかかる荷重を封止樹脂60にも分散することができ、配線層33(パッド34)に外力が加わった際に絶縁層30にクラック等の樹脂破壊が発生することを更に抑制することができる。
なお、上記実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・図10〜図14に示した変形例の半導体パッケージ10に、貫通孔60X内に充填された貫通電極61と、封止樹脂60の上面に形成された配線層62とを設けるようにしてもよい。
これに限らず、例えば図19に示すように、貫通孔60Xの内面(貫通孔60Xの内側面及び貫通孔60Xの底部に露出する配線層33の上面33A)に沿って形成された貫通電極63を介して、接続パッドP3と配線層33とを電気的に接続するようにしてもよい。このとき、図中右側に示すように、貫通孔60Xの内側面に形成された部分よりも、貫通孔60Xの底部に形成された部分が厚くなるように貫通電極63を形成してもよい。なお、この場合の接続パッドP3(配線層62)は、封止樹脂60の上面に、例えば平面視略環状(リング状)に形成される。
・上記各実施形態では、半導体チップ50の裏面を露出するように封止樹脂60を形成した。これに限らず、半導体チップ50の裏面を被覆するように封止樹脂60を形成してもよい。
・上記第2実施形態では、半導体パッケージ10Aと半導体パッケージ70とを接続する接続端子としてはんだボール90を用いるようにした。これに限らず、例えば、柱状の接続端子である金属ポストや、スプリング性を有した接続端子(スプリング接続端子)等を、半導体パッケージ10と半導体パッケージ70とを接続する接続端子として用いるようにしてもよい。
・上記各実施形態の半導体パッケージ10,10Aの製造方法において、貫通孔60Xは、封止樹脂60を形成した後であればいつ形成してもよい。例えば、半導体チップ50及び封止樹脂60を上面側から薄化した直後に、その薄化後の封止樹脂60と絶縁層43,41とを厚さ方向に貫通する貫通孔60Xを形成するようにしてもよい。
11 半導体装置
20 配線基板
21 配線構造
22 ソルダレジスト層(最外絶縁層)
23 配線構造
30 絶縁層
30X 貫通孔
30Y 凹部
31 ビア配線
32 配線層
33 配線層
40 配線層
41 絶縁層
42 配線層
43 絶縁層(最上層の絶縁層)
44 配線層(最上層の配線層)
50 半導体チップ
60 封止樹脂
60X 貫通孔
61 貫通電極
62 配線層
70 半導体パッケージ
90 はんだボール(接続端子)
P2 接続端子(パッド)
P3 接続パッド
Claims (12)
- 熱硬化性樹脂を主成分とする絶縁性樹脂からなる第1絶縁層と、
前記第1絶縁層の上面に形成された凹部と、
前記第1絶縁層から露出された上面を有し、前記凹部に形成された第1配線層と、
前記第1絶縁層を厚さ方向に貫通し、前記第1絶縁層から露出された上端面を有するビア配線と、
前記ビア配線の上端面及び前記第1配線層の上面に接するように、前記第1絶縁層の上面に形成された第2配線層と、
感光性樹脂を主成分とする絶縁性樹脂からなり、前記第2配線層の少なくとも一部を被覆するとともに、前記第1絶縁層の上面に形成された第2絶縁層と、
前記ビア配線の下端面に接するように、前記第1絶縁層の下面に形成された第3配線層と、
感光性樹脂を主成分とする絶縁性樹脂からなり、前記第3配線層の少なくとも一部を被覆するように前記第1絶縁層の下面に形成された最外絶縁層と、
前記第2配線層と、前記第2絶縁層と、前記第2絶縁層の上面に形成された第4配線層と、感光性樹脂を主成分とする絶縁性樹脂からなり、前記第4配線層の少なくとも一部を被覆するとともに、前記第2絶縁層の上面に形成された第3絶縁層とを有する配線構造と、を有し、
前記配線構造の最上層の配線層は、電子部品と接続されるパッドとして機能することを特徴とする配線基板。 - 前記第1絶縁層の上面と前記第1配線層の上面と前記ビア配線の上端面とが研磨面であり、
前記第1配線層と前記第2配線層の接続部は、前記第1配線層の上面と前記第2配線層の上面及び側面とによって形成される段差を有し、
前記第2絶縁層は、前記段差を被覆するように形成されていることを特徴とする請求項1に記載の配線基板。 - 熱硬化性樹脂を主成分とする絶縁性樹脂からなる第1絶縁層と、
前記第1絶縁層の上面に形成された凹部と、
前記第1絶縁層から露出された上面を有し、前記凹部に形成された第1配線層と、
前記第1絶縁層を厚さ方向に貫通し、前記第1絶縁層から露出された上端面を有するビア配線と、
前記第1絶縁層の上面に形成された配線構造と、
前記配線構造の最上層の配線層に接続された電子部品と、
前記電子部品を封止する封止樹脂と、を有し、
前記配線構造は、
前記ビア配線の上端面及び前記第1配線層の上面に接するように、前記第1絶縁層の上面に形成された第2配線層と、
感光性樹脂を主成分とする絶縁性樹脂からなり、前記第2配線層の少なくとも一部を被覆するとともに、前記第1絶縁層の上面に形成された第2絶縁層と、を有することを特徴とする半導体パッケージ。 - 前記封止樹脂と前記配線構造を厚さ方向に貫通して、前記第1配線層の上面の少なくとも一部を露出する貫通孔を有することを特徴とする請求項3に記載の半導体パッケージ。
- 前記貫通孔内に形成され、前記第1配線層に接続された貫通電極と、
前記封止樹脂の上面に形成され、前記貫通電極を介して前記第1配線層と接続された接続パッドと、をさらに有することを特徴とする請求項4に記載の半導体パッケージ。 - 前記電子部品は、前記最上層の配線層にフリップチップ実装された半導体チップであり、
前記封止樹脂は、前記半導体チップの回路形成面及び側面を被覆し、前記半導体チップの回路形成面とは反対側の裏面を露出し、
前記封止樹脂の上面と前記半導体チップの裏面は面一であることを特徴とする請求項3〜5のいずれか一項に記載の半導体パッケージ。 - 前記ビア配線の下端面に接するように、前記第1絶縁層の下面に形成された第3配線層と、
感光性樹脂を主成分とする絶縁性樹脂からなり、前記第3配線層の少なくとも一部を被覆するように前記第1絶縁層の下面に形成された最外絶縁層と、をさらに有し、
前記第1絶縁層の熱膨張係数と前記封止樹脂の熱膨張係数と前記最外絶縁層の熱膨張係数とが等しいことを特徴とする請求項3〜6のいずれか一項に記載の半導体パッケージ。 - 請求項3〜7のいずれか一項に記載の半導体パッケージと、
前記半導体パッケージの上に接続端子を介して搭載された他の半導体パッケージと、
を有することを特徴とする半導体装置。 - 熱硬化性樹脂を主成分とする絶縁性樹脂からなる第1絶縁層と、前記第1絶縁層の上面に形成された凹部と、前記第1絶縁層から露出された上面を有し、前記凹部に形成された第1配線層とを有する構造体を支持基板上に形成する工程と、
前記第1絶縁層を厚さ方向に貫通する貫通孔を形成する工程と、
前記貫通孔を充填するとともに、前記第1絶縁層の上面及び前記第1配線層の上面を被覆する導電層を形成する工程と、
前記第1絶縁層の上面を被覆する前記導電層と前記第1絶縁層の上面の一部と前記第1配線層の上面の一部とを研磨することにより、前記第1絶縁層の上面に露出する上端面を有するビア配線を前記貫通孔内に形成する工程と、
前記第1絶縁層の上面に、前記ビア配線の上端面及び前記第1配線層の上面と接する第2配線層を形成する工程と、
前記第1絶縁層の上面に、前記第2配線層の少なくとも一部を被覆するように、感光性樹脂を主成分とする絶縁性樹脂からなる第2絶縁層を形成する工程と、を有することを特徴とする配線基板の製造方法。 - 熱硬化性樹脂を主成分とする絶縁性樹脂からなる第1絶縁層と、前記第1絶縁層の上面に形成された凹部と、前記第1絶縁層から露出された上面を有し、前記凹部に形成された第1配線層とを有する構造体を支持基板上に形成する工程と、
前記第1絶縁層を厚さ方向に貫通する貫通孔を形成する工程と、
前記貫通孔を充填するとともに、前記第1絶縁層の上面及び前記第1配線層の上面を被覆する導電層を形成する工程と、
前記第1絶縁層の上面を被覆する前記導電層と前記第1絶縁層の上面の一部と前記第1配線層の上面の一部とを研磨することにより、前記第1絶縁層の上面に露出する上端面を有するビア配線を前記貫通孔内に形成する工程と、
前記第1絶縁層の上面に、配線構造を形成する工程と、
前記配線構造の最上層の配線層に電子部品を接続する工程と、
前記配線構造の最上層の絶縁層の上面に、前記電子部品を封止する封止樹脂を形成する工程と、を含み、
前記配線構造を形成する工程は、
前記第1絶縁層の上面に、前記ビア配線の上端面及び前記第1配線層の上面と接する第2配線層を形成する工程と、
前記第1絶縁層の上面に、前記第2配線層の少なくとも一部を被覆するように、感光性樹脂を主成分とする絶縁性樹脂からなる第2絶縁層を形成する工程と、を有することを特徴とする半導体パッケージの製造方法。 - 前記封止樹脂及び前記電子部品を上面側から薄化する工程と、
前記封止樹脂と前記配線構造の絶縁層とを厚さ方向に貫通し、前記第1配線層の上面の一部を露出する貫通孔を形成する工程と、をさらに含むことを特徴とする請求項10に記載の半導体パッケージの製造方法。 - 前記支持基板を除去する工程と、
前記第1絶縁層の下面に、前記ビア配線の下端面と接する第3配線層を形成する工程と、
前記第1絶縁層の下面に、感光性樹脂を主成分とする絶縁性樹脂からなり、前記第3配線層の少なくとも一部を被覆する最外絶縁層を形成する工程と、をさらに含むことを特徴とする請求項10又は11に記載の半導体パッケージの製造方法。
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US11715680B2 (en) | 2020-12-17 | 2023-08-01 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
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