JP6626687B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents
配線基板、半導体装置及び配線基板の製造方法 Download PDFInfo
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- JP6626687B2 JP6626687B2 JP2015211723A JP2015211723A JP6626687B2 JP 6626687 B2 JP6626687 B2 JP 6626687B2 JP 2015211723 A JP2015211723 A JP 2015211723A JP 2015211723 A JP2015211723 A JP 2015211723A JP 6626687 B2 JP6626687 B2 JP 6626687B2
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Description
以下、図1〜図8に従って第1実施形態を説明する。
図2に示すように、半導体装置10は、配線基板20と、その配線基板20にフリップチップ実装された1つ又は複数(ここでは、1つ)の半導体素子60と、アンダーフィル材65と、封止樹脂66と、外部接続端子70とを有している。
以上説明したように、配線基板20では、1層の絶縁層40が、配線パターン30の4つの側面と下面と上面との6面に接触されている。すなわち、絶縁層40は、配線パターン30を取り囲むように形成されている。そして、絶縁層40、特に配線パターン30の上面と接触する被覆部41により、配線パターン30が係止されている。換言すると、各配線パターン30は、絶縁層40内に食い込んで形成され、上面の外縁部が絶縁層40の被覆部41に係止されている。このため、配線パターン30が絶縁層40から剥離することが好適に抑制される。
図5(a)に示すように、支持体80の下面にキャリア付金属箔81が貼着された支持基板を準備する。支持体80は、例えば、ガラス、アラミド、LCP(Liquid Crystal Polymer)繊維の織布や不織布などの補強材に、エポキシ樹脂やポリイミド樹脂等の熱硬化性樹脂を含浸させたプリプレグである。キャリア付金属箔81は、支持体80の下面に貼着されたキャリア層82と、キャリア層82の下面に剥離層(図示略)を介して積層された極薄の金属箔83とを有している。キャリア層82は、金属箔83の取り扱いを容易にするための支持材として設けられている。キャリア層82は、例えば、厚さが15〜70μm程度の銅板である。金属箔83は、例えば、厚さが0.5〜5μm程度の銅箔である。
次に、半導体装置10の製造方法について説明する。
まず、図8(d)に示す工程では、柱状の接続端子61を有する半導体素子60を用意する。接続端子61は、公知の製造方法により製造することが可能であるため、図示を省略して詳細な説明を割愛するが、例えば以下のような方法で製造される。
続いて、配線基板20の絶縁層40上に、半導体素子60を封止する封止樹脂66(図2参照)を形成する。例えば、封止樹脂66の材料として熱硬化性を有したモールド樹脂を用いる場合には、アンダーフィル材65を形成した構造体を金型内に収容し、その金型内に圧力(例えば、5〜10MPa)を印加し、流動化したモールド樹脂を導入する。その後、モールド樹脂を180℃程度の温度で加熱して硬化させることで、封止樹脂66を形成する。なお、モールド樹脂を充填する方法としては、例えば、トランスファーモールド法、コンプレッションモールド法やインジェクションモールド法などの方法を用いることができる。
以上説明した本実施形態によれば、以下の効果を奏することができる。
(1)配線パターン30の下面及び側面を被覆する絶縁層40に、配線パターン30の上面の外縁部全周を連続して被覆する被覆部41を設けた。これにより、絶縁層40が配線パターン30の4つの側面と下面と上面との6面に接触され、その絶縁層40によって配線パターン30が係止される。このため、配線パターン30が絶縁層40から剥離することを好適に抑制することができる。
以下、図9〜図12に従って第3実施形態を説明する。この実施形態の半導体装置10Aは、配線基板20Aの配線パターン30の構成が上記第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図8に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
以下、図13に従って第3実施形態について説明する。この実施形態では、配線基板20の製造方法が第1実施形態と異なっている。以下、第1実施形態との相違点を中心に説明する。先の図1〜図12に示した部材と同一の部材にはそれぞれ同一の符号を付して示し、それら各要素についての詳細な説明は省略する。
次に、図13(b)に示す工程では、図13(a)に示した構造体の下面側に露出している金属層のうちCu層、ここでは配線パターン30及び金属箔83に対して選択的に粗化処理を施す。この粗化処理により、各配線パターン30の下面及び側面に微細な凹凸が形成され、それら各配線パターン30の下面全面及び側面全面が粗化面30Rに形成される。さらに、凹部84Xに露出された各配線パターン30の上面にも微細な凹凸が形成され、それら各配線パターン30の上面の一部も粗化面30Rに形成される。また、粗化処理により、凹部84Xの底部に露出する金属箔83の下面83Aに微細な凹凸が形成され、その金属箔83の下面83Aが粗化面83Rに形成される。例えば、粗化前の(または、金属膜84に被覆された)配線パターン30及び金属箔83の表面の粗度が表面粗さRa値で1〜300nm程度であるのに対し、粗化処理により配線パターン30及び金属箔83の表面の粗度を表面粗さRa値で100〜700nm程度とすることができる。換言すると、本工程では、外部に露出された配線パターン30及び金属箔83の表面の粗度が、表面粗さRa値で100〜150nm程度となるように粗化が行われる。ここで、表面粗さRa値とは、表面粗さを表わす数値の一種であり、算術平均粗さと呼ばれるものであって、具体的には測定領域内で変化する高さの絶対値を平均ラインである表面から測定して算術平均したものである。
以上説明した実施形態によれば、第1実施形態の(1)〜(5)の効果に加えて以下の効果を奏することができる。
なお、上記各実施形態は、これを適宜変更した以下の態様にて実施することもできる。
・図14に示す製造工程により配線基板20を形成するようにしてもよい。なお、図14(a)は、先の図13(b)に示した工程の代わりに実施される。
以上説明した製造方法により製造された配線基板20では、絶縁層40の上面40Aと突出部42の側面とを粗化面40Rとしたため、絶縁層40とアンダーフィル材65との密着性をより向上させることができる。
・上記各実施形態におけるアンダーフィル材65を省略してもよい。この場合には、例えば、封止樹脂66によって、配線基板20,20A,20Bと半導体素子60との隙間を封止するようにしてもよい。
・上記各実施形態では、支持基板の片側(一方の面)に配線パターン30及び絶縁層40を積層し、最後に支持基板を除去してコアレスの配線基板20を製造するようにした。これに限らず、例えば、支持基板の両側(一方の面及び他方の面)に金属膜84を形成し、それら両側の金属膜84上に配線パターン30及び絶縁層40を積層し、最後に支持基板及び金属膜84を除去して複数のコアレスの配線基板20を製造するようにしてもよい。
・上記各実施形態では、絶縁層40から露出する配線パターン30の上面の一部に表面処理層52を形成するようにした。これに限らず、例えば、絶縁層40から露出する配線パターン30(接続パッド31、パッド32及び回路パターン33)の上面全面を被覆するように表面処理層52に形成するようにしてもよい。
・上記各実施形態における表面処理層52を省略してもよい。
・上記各実施形態における配線基板20,20A,20Bにおける配線パターンの取り回しなどは様々に変形・変更することが可能である。
20,20A,20B 配線基板
30 配線パターン
30R 粗化面
31 接続パッド
32 パッド
33 回路パターン
40 絶縁層
40A 上面
40R 粗化面
41 被覆部
51 表面処理層
52 表面処理層
60 半導体素子
80 支持体(支持基板)
81 キャリア付金属箔(支持基板)
82 キャリア層
83 金属箔
84 金属膜
84X 凹部
Claims (9)
- 電子部品が実装される実装領域内に形成されたパッドと、前記パッドから平面方向に延出された回路パターンとを有する配線パターンと、
前記配線パターンの上面の外縁部全周を連続して被覆する被覆部を有し、前記配線パターンの下面及び側面を被覆するとともに、前記配線パターンの上面の一部を露出する絶縁層と、
前記被覆部の側面と、前記絶縁層から露出する前記配線パターンの上面とからなる凹部と、を有し、
前記絶縁層の上面は、前記配線パターンの上面よりも上方に形成されており、
前記被覆部の側面は、凸型R形状に形成されており、
前記凹部は、底部の開口径が最も狭く形成されるとともに、前記底部から上方に向かうに連れて開口径が大きくなるように形成されており、
前記絶縁層の上面は、前記被覆部の側面よりも表面粗度の大きい粗化面であることを特徴とする配線基板。 - 前記配線パターンの上面は、前記外縁部以外の部分が前記絶縁層から露出していることを特徴とする請求項1に記載の配線基板。
- 前記絶縁層と接する前記配線パターンの表面全面は、前記絶縁層から露出された前記配線パターンの上面よりも表面粗度の大きい粗化面であることを特徴とする請求項1又は2に記載の配線基板。
- 前記配線パターンは、前記回路パターンを介して前記パッドと接続された接続パッドを有し、
前記絶縁層は、前記接続パッドの下面の一部を露出する貫通孔を有することを特徴とする請求項1〜3のいずれか一項に記載の配線基板。 - 前記貫通孔に露出された前記接続パッドの下面に形成された表面処理層と、
前記絶縁層から露出された前記パッドの上面に形成された表面処理層と、
を有することを特徴とする請求項4に記載の配線基板。 - 請求項1〜5のいずれか一項に記載の配線基板と、
前記パッドと電気的に接続され、前記配線基板に実装された半導体素子と、を有することを特徴とする半導体装置。 - 支持基板を準備する工程と、
前記支持基板の下面に金属膜を形成する工程と、
前記金属膜の下面に配線パターンを形成する工程と、
前記配線パターンをマスクにして、前記金属膜を前記配線パターン及び前記支持基板に対して選択的に除去し、前記配線パターンの上面の外縁部を露出する凹部を前記金属膜に形成する工程と、
前記配線パターンの下面全面及び側面全面を被覆するとともに、前記凹部を充填する絶縁層を形成する工程と、
前記支持基板を除去する工程と、
前記金属膜を除去する工程と、を有し、
前記絶縁層には、前記配線パターンの上面の外縁部全周を連続して被覆する被覆部が形成されることを特徴とする配線基板の製造方法。 - 前記凹部を形成する工程の後であって、前記絶縁層を形成する工程の前に、前記配線パターンと前記凹部に露出する前記支持基板とに対して選択的に粗化処理を施す工程を有することを特徴とする請求項7に記載の配線基板の製造方法。
- 前記凹部を形成する工程では、等方性エッチングにより、前記金属膜を除去して前記凹部を形成することを特徴とする請求項7又は8に記載の配線基板の製造方法。
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