CN112071821B - 半导体封装基板及其制法与电子封装件 - Google Patents

半导体封装基板及其制法与电子封装件 Download PDF

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CN112071821B
CN112071821B CN202010449653.3A CN202010449653A CN112071821B CN 112071821 B CN112071821 B CN 112071821B CN 202010449653 A CN202010449653 A CN 202010449653A CN 112071821 B CN112071821 B CN 112071821B
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周保宏
余俊贤
许诗滨
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Phoenix Pioneer Technology Co Ltd
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Abstract

一种半导体封装基板及其制法与电子封装件，该制法包括于线路结构上形成具有第一开孔与第二开孔的金属片，使该线路结构的第一焊垫外露于该第一开孔，该线路结构的第二焊垫外露于该第二开孔，且于该金属片上及该第二开孔中的孔壁上形成绝缘层，借由接地用的第一导电元件设于该第一开孔中时能接触该金属片与该第一焊垫，以令在信号传递中所产生的热能可利用该金属片及该第一导电元件进行散逸。

Description

半导体封装基板及其制法与电子封装件
技术领域
本发明有关一种封装基材，特别涉及一种具散热功能的承载基板及电子封装件。
背景技术
随着产业应用的发展，近年来逐渐朝着如人工智能(AI)芯片、高阶芯片或堆叠芯片等大尺寸芯片的封装规格的趋势进行研发，如3D或2.5D IC工艺，以应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品，如人工智能(AI)芯片、GPU等。
因此，业界遂改用大尺寸板面的覆晶封装基板，如40*40、70*70或其它更厚且大的结构板型，以承载如人工智能(AI)芯片、高阶芯片或堆叠芯片等大尺寸芯片。
如图1A所示，现有电子封装件1包括：一封装基板1a、以及一结合于该封装基板1a上的半导体芯片19。具体地，该封装基板1a包括一核心层10、设于该核心层10上的线路增层部11、及设于该线路增层部11上的防焊层12，且令该防焊层12外露出该线路增层部11最外侧的线路层，从而供作为接点(即I/O)11a,11b，以于上侧借由焊锡凸块13a接置该半导体芯片19，并于下侧(如图1B所示的植球侧或BGA)借由焊锡球13b接置电路板(图未示)。
现有核心层10的制作中，采用玻纤配合环氧树酯所组成的基材，如BT(Bismaleimide Triazine)、FR4或FR5等，再其上进行导通孔工艺，如机械钻孔、激光钻孔或双锥状盲孔等成孔步骤，再于孔中电镀形成导电部100。此外，线路增层部11的增层方法亦使用ABF种类的材料作为介电层，且该防焊层12的材质选择使用绿漆或油墨等材料。
现有封装基板1a的信号传递路径由上至下按序为焊锡凸块13a、接点11a、线路增层部11、导电部100、线路增层部11、接点11b与焊锡球13b(反向亦同)，而在信号传递中会产生热能，且产生的热能只能利用该封装基板1a的金属材(如该线路增层部11的铜材线路表面)设计及介电材料进行散逸。
然而，现有封装基板1a的散热速度极慢，因而造成热能积累于该封装基板1a中，导致整个电子封装件1容易发烫，进而影响该电子封装件1的整体效能(如降低传输速度、运算速度等)与使用寿命，故该封装基板1a难以符合散热需求。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种半导体封装基板及其制法与电子封装件，以利于热能的散逸。
本发明的半导体封装基板，包括：线路结构，其包含至少一介电层及结合于该介电层的线路层，且该线路结构具有相对的置晶侧与植球侧，其中，该植球侧的线路层具有第一焊垫与第二焊垫；金属片，其借由一结合材结合于该线路结构的植球侧上，且该金属片具有第一开孔与第二开孔，其中，该第一开孔外露出该第一焊垫，该第二开孔外露出该第二焊垫；以及绝缘层，其设于该金属片上及该第二开孔中的孔壁上，且该绝缘层未形成于该第一开孔中的孔壁上。
本发明亦提供一种半导体封装基板的制法，包括：提供一包含至少一介电层及结合于该介电层的线路层的线路结构，且该线路结构具有相对的置晶侧与植球侧，其中，该植球侧的线路层上形成有第一焊垫与第二焊垫；借由结合材将一金属片结合于该线路结构的植球侧上，且形成第一开孔与第二开孔于该金属片上，以令该第一焊垫外露于该第一开孔，且该第二焊垫外露于该第二开孔；形成绝缘层于该线路结构的植球侧及该金属片上；以及移除该第一开孔、第二开孔中及该第一焊垫、第二焊垫上的该绝缘层，以令该第一焊垫外露于该第一开孔，且该第二焊垫外露于该第二开孔，其中，该第二开孔的孔壁上保留有该绝缘层。
所述的制法中，还包括于该线路结构的置晶侧上形成多个导电凸块，以结合至少一电子元件。
所述的半导体封装基板及其制法中，还包括形成第一导电元件于该第一开孔中的第一焊垫上，以令该第一导电元件接触该金属片。
所述的半导体封装基板中，还包括形成第二导电元件于该第二开孔中的第二焊垫上，以令该第二导电元件接触该绝缘层而未接触该金属片。
本发明更提供一种电子封装件，包括：所述的半导体封装基板；以及电子元件，其设于该线路结构的置晶侧上。
所述的电子封装件中，还包括封装层，其设于该半导体封装基板上，以将该电子元件结合至该半导体封装基板上。
所述的电子封装件中，该电子元件以多个导电凸块设于该线路结构的置晶侧上。
由上可知，本发明的半导体封装基板及其制法与电子封装件，主要借由该金属片的第一开孔中未形成该绝缘层，使接地用的第一导电元件能接触该金属片，以令在信号传递中所产生的热能除了利用该半导体封装基板的金属材及介电材料进行散逸外，更能利用该金属片及第一导电元件进行散逸，故相较于现有技术，本发明能避免热能积累于该半导体封装基板中的情况，以避免整个电子封装件过热发烫的问题，因而该半导体封装基板符合散热需求，使其能确保该电子封装件的整体效能与使用寿命。
附图说明
图1A为现有电子封装件的剖视示意图。
图1B为图1A的仰视图。
图2A至图2E为本发明的电子封装件的制法的剖视示意图。
图2D’为图2D的仰视图。
符号说明
1 电子封装件
1a 封装基板
10,20 核心层
100,200 导电部
11 线路增层部
11a,11b 接点
12 防焊层
13a 焊锡凸块
13b 焊锡球
19 半导体芯片
2 半导体封装基板
2a 线路结构
20a 置晶侧
20b 植球侧
21 增层部
210 介电层
211 线路层
212 第一焊垫
212’ 焊垫
213 第二焊垫
22 防焊层
220 开孔
23 金属片
230 第一开孔
231 第二开孔
24 结合材
25 绝缘层
26a 第一导电元件
26b 第二导电元件
27 导电凸块
4 电子封装件
40 电子元件
41 封装层。
具体实施方式
以下借由特定的具体实施例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所公开的内容轻易地了解本发明的其他优点及技术效果。
须知，本说明书说明书附图所示出的结构、比例、大小等，均仅用以配合说明书所公开的内容，以供熟悉此技艺的人士的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的技术效果及所能实现的目之下，均应仍落在本发明所公开的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当视为本发明可实施的范围。
图2A至图2E为本发明的电子封装件4及半导体封装基板2的制法的剖视示意图。
如图2A所示，提供一线路结构2a，该线路结构2a具有相对的置晶侧20a与植球侧20b，两侧均可用于置放电子元件(如半导体芯片、无源元件等)，且将置放半导体芯片的外接侧称为置晶侧20a。
于本实施例中，该线路结构2a具有一核心层20，其内形成有多个导电部200。例如，形成该核心层20的材质采用含玻纤及有机树脂的基材，如BT(Bismaleimide Triazine)、FR4或FR5等，亦或采用高刚性无玻纤但含有填充材(filler)(如SiO2)的有机基材，再于其上进行导通孔工艺，如机械钻孔或激光钻孔等成孔步骤，并于孔中形成该导电部200。或者，于另一实施例中，形成该核心层20的材质为有机绝缘材，该有机绝缘材可为ABF(AjinomotoBuild-up Film)、有玻纤或无玻纤的预浸材(Prepreg)、铸模化合物(Molding Compound)，如环氧模压树脂(Epoxy Molding Compound，简称EMC)形成的核心基材，优选者，采用高刚性及低热膨胀系数(CTE)的EMC，此时该导电部200可由单一导电柱体或由多个相互接触堆叠的导电柱体所组成。
此外，该线路结构2a还包括设于该核心层20上的增层部21，其具有至少一介电层210及多个结合该介电层210的线路层211，该线路结构2a的置晶侧20a的最外层的线路层211具有多个焊垫212’，且该线路结构2a的植球侧20b的最外层的线路层211具有多个第一焊垫212(如接地接点)及第二焊垫213(如信号接点)，并于该线路结构2a的置晶侧20a上的增层部21上可形成一防焊层22。例如，该介电层210可为液状环氧树脂、膜状ABF、预浸材、模压树脂(EMC)或感光型树脂形成，且形成该防焊层22的材质可为石墨烯、油墨、绿漆、ABF或非感光型介电材(如EMC)或其它适当材质，并无特别限制。应可理解地，有关该线路层211的布设层数可依需求设计。
又，于该线路结构2a的植球侧20b上借由结合材24结合一金属片23。例如，该金属片23为钢板、镍合金(alloy 42)片体等，且该结合材24为粘着胶材。
另外，于其它实施例中，该核心层20可改为硅基材，以令该增层部21设于该硅基材上，使该线路结构2a成为硅中介板(silicon interposer)形式。或者，于其它实施例中，该线路结构2a可为无核心层(coreless)形式。
如图2B所示，于该金属片23上形成多个第一开孔230与多个第二开孔231，并使所述多个第一开孔230与第二开孔231延伸穿过该结合材24，以令部分线路层(如所述多个第一焊垫212)外露于所述多个第一开孔230，且令该第二焊垫213外露于所述多个第二开孔231。
于本实施例中，该金属片23为钢板、镍合金(alloy 42)片体等，且该结合材24为粘着胶材。
如图2C所示，形成一绝缘层25于该第一焊垫212、该第二焊垫213、该金属片23上与该多个第一开孔230及第二开孔231内。
于本实施例中，形成该绝缘层25的材质可为如石墨烯的高导热率的防焊材或如油墨、绿漆、ABF或非感光型介电材(如EMC)等一般防焊材，并无特别限制。
如图2D及图2D’所示，移除该绝缘层25的部分材质(例如，该第一开孔230中与该第一焊垫212上的全部绝缘层25、该第二开孔231中与第二焊垫213上的部分绝缘层25)，以保留该金属片23上及所述多个第二开孔231孔壁上的绝缘层25，使所述多个第一焊垫212外露于所述多个第一开孔230，且所述多个第二焊垫213外露于所述多个第二开孔231。
于本实施例中，该绝缘层25披覆于该第二开孔231中的孔壁上，而未披覆于该第一开孔230中的孔壁上，使该第一开孔230中没有该绝缘层25。
此外，也可形成多个开孔220于该防焊层22上，以令所述多个焊垫212’外露于所述多个开孔220。
因此，本发明的半导体封装基板2于该植球侧20b上增设金属片23，使该半导体封装基板2的散热效能增加，以减缓该半导体封装基板2的温度升高的速度。
如图2E所示，该第一开孔230中的第一焊垫212上结合第一导电元件26a，使该第一导电元件26a接触该金属片23与该第一焊垫212，且该第二开孔231中的第二焊垫213上结合第二导电元件26b，使该第二导电元件26b接触该绝缘层25与该第二焊垫213而不会接触该金属片23。
于本实施例中，该第一与第二导电元件26a,26b包含焊锡材料，如焊锡球。
此外，可于该线路结构2a的置晶侧20a的外露焊垫212’上设置至少一电子元件40，并形成封装层41于该线路结构2a的置晶侧20a上以固定结合该电子元件40，以形成电子封装件4。
所述的电子元件40为主动元件、无源元件或其二者组合，其中，该主动元件例如为半导体芯片，且该无源元件例如为电阻、电容及电感。例如，该电子元件40为半导体芯片，其借由多个含焊锡的导电凸块27以覆晶方式电性连接所述多个焊垫212’。或者，该电子元件40也可借由多个焊线(图略)以打线方式电性连接所述多个焊垫212’。然而，有关该电子元件电性连接该承载基板2的方式不限于上述，且该电子元件也可嵌埋于该增层部21中。
所述的封装层41可为底胶，其形成于该线路结构2a的置晶侧20a与该电子元件40之间以包覆所述多个导电凸块27。或者，该封装层可为压合工艺用的薄膜、模压工艺用的封装胶体或印刷工艺用的胶材等以包覆该电子元件40与所述多个导电凸块27，且形成该封装层41的材质为聚酰亚胺(PI)、环氧树脂(epoxy)或模封的封装材。应可理解地，有关该电子元件40的封装方式并不限于上述。
因此，本发明的电子封装件4及其半导体封装基板2主要借由该金属片23的第一开孔230中未形成该绝缘层25，使接地用的第一导电元件26a能接触该金属片23，因而能加速该半导体封装基板2的热能散逸。具体地，本发明的电子封装件4的信号传递路径由上至下按序为该电子元件40、导电凸块27、焊垫212’、增层部21的线路层211、导电部200、增层部21的线路层211、第二焊垫213与第二导电元件26b(反向亦同)，而在信号传递中所产生的热能除了利用该承载基板2的金属材(如增层部21的线路层211的铜材表面)及该介电层210进行散逸外，更利用该金属片23及第一导电元件26a进行散逸。
此外，本发明的承载基板2的绝缘层25若采用高导热材(如石墨烯)作为防焊层，可更增快该绝缘层25的导热速率，使该绝缘层25不仅具有防焊功能，且可加速该半导体封装基板2的热能散逸效果，使该电子封装件4的整体效能与使用寿命更稳定。
综上所述，本发明的半导体封装基板2及借此封装完成的电子封装件4，借由该金属片23及该第一开孔230内部的结构特征，使接地用的第一导电元件26a能接触该金属片23，以令在信号传递中所产生的热能可利用该金属片23及第一导电元件26a进行散逸，因而能加速该承载基板2的热能散逸，故相较于现有技术，本发明能有效增进该半导体封装基板2的散热效益，以避免整个电子封装件4发烫的问题发生。因此，该半导体封装基板2可满足电子封装件4的散热需求，进而能有效确保该电子封装件4的整体效能(如降低传输速度、运算速度等)与使用寿命。
上述实施例仅用以例示性说明本发明的原理及其技术效果，而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的构思及范围下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种半导体封装基板，其特征在于，包括：
线路结构，其包含至少一介电层及结合于该介电层的线路层，且该线路结构具有相对的置晶侧与植球侧，其中，该植球侧的线路层具有第一焊垫与第二焊垫；
金属片，其借由一结合材结合于该线路结构的植球侧上，且该金属片具有第一开孔与第二开孔，其中，该第一开孔外露出该第一焊垫，该第二开孔外露出该第二焊垫；以及
绝缘层，其设于该金属片上及该第二开孔的孔壁上，且该绝缘层未形成于该第一开孔的孔壁上以外露出该金属片，而该第二开孔的孔壁上具有该绝缘层以包覆住该金属片。
2.根据权利要求1所述的半导体封装基板，其特征在于，该第一开孔中的第一焊垫上结合有第一导电元件，以令该第一导电元件接触该金属片。
3.根据权利要求1所述的半导体封装基板，其特征在于，该第二开孔中的第二焊垫上结合有第二导电元件，以令该第二导电元件接触该绝缘层而未接触该金属片。
4.一种电子封装件，其特征在于，包括：
根据权利要求1至3中任一所述的半导体封装基板；以及
电子元件，其设于该线路结构的置晶侧上。
5.根据权利要求4所述的电子封装件，其特征在于，该电子封装件还包括封装层，其设于该半导体封装基板上，以将该电子元件结合至该半导体封装基板上。
6.根据权利要求4所述的电子封装件，其特征在于，该电子元件以多个导电凸块设于该线路结构的置晶侧上。
7.一种半导体封装基板的制法，其特征在于，包括：
提供一包含至少一介电层及设于该介电层上的线路层的线路结构，且该线路结构具有相对的置晶侧与植球侧，其中，该植球侧的线路层上形成有第一焊垫与第二焊垫；
借由结合材将一金属片结合于该线路结构的植球侧上，且形成第一开孔与第二开孔于该金属片上，以令该第一焊垫外露于该第一开孔，且该第二焊垫外露于该第二开孔；
形成绝缘层于该线路结构的植球侧及该金属片上；以及
移除该第一开孔、第二开孔中及该第一焊垫、第二焊垫上的该绝缘层，以令该第一焊垫外露于该第一开孔，且该第二焊垫外露于该第二开孔，其中，该第一开孔的孔壁上未保留有该绝缘层以外露出该金属片，而该第二开孔的孔壁上保留有该绝缘层以包覆住该金属片。
8.根据权利要求7所述的半导体封装基板的制法，其特征在于，该制法还包括形成第一导电元件于该第一开孔中的第一焊垫上，以令该第一导电元件接触该金属片。
9.根据权利要求7所述的半导体封装基板的制法，其特征在于，该制法还包括形成第二导电元件于该第二开孔中的第二焊垫上，以令该第二导电元件接触该绝缘层而未接触该金属片。
10.根据权利要求7所述的半导体封装基板的制法，其特征在于，该制法还包括于该线路结构的置晶侧上形成多个导电凸块，以结合至少一电子元件。
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