US11450597B2 - Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same - Google Patents

Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same Download PDF

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US11450597B2
US11450597B2 US16/897,372 US202016897372A US11450597B2 US 11450597 B2 US11450597 B2 US 11450597B2 US 202016897372 A US202016897372 A US 202016897372A US 11450597 B2 US11450597 B2 US 11450597B2
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solder pads
metal sheet
holes
circuit structure
package substrate
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US20200388564A1 (en
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Pao-Hung CHOU
Chun-Hsien YU
Shih-Ping Hsu
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Definitions

  • the present disclosure relates to package substrates, and, more particularly, to a carrier substrate that can dissipate heat and an electronic package having the carrier substrate.
  • fabricators use a large-sized flip-chip package substrate, such as one with board size of 40*40, 70*70, or more, to carry the AI chips, advanced chips or stacked chips, which have a large size.
  • an electronic package 1 comprises a package substrate 1 a and a semiconductor chip 19 bonded onto the package substrate 1 a .
  • the package substrate 1 a includes a core layer 10 , a circuit built-up layer 11 formed on the core layer 10 , and a solder resist layer 12 formed on the circuit built-up layer 11 .
  • the solder resist layer 12 is exposed from an outermost one of circuit layers of the circuit built-up layer 11 and is used as contacts (i.e., I/O) 11 a and 11 b , for the semiconductor chip 19 to be mounted on an upper side thereof via solder bumps 13 a and a circuit board (not shown) to be mounted on a lower side thereof (e.g., the ball planting side or BGA shown in FIG. 1B ) via solder balls 13 b.
  • a substrate composed of glass fiber and epoxy resin is used, such as bismaleimide triazine (BT), FR4, FR5 etc.
  • a via formation process such as mechanically drilling, laser drilling or dual-cone-shaped-via processes, is performed on the substrate, and an electroplating process is performed on the vias to form conductive portions 100 .
  • the circuit built-up layer 11 is formed by using ABF as a dielectric layer.
  • the solder resist layer 12 is made of solder resist or solder ink.
  • the signals of the package substrate 1 a are transmitted from the solder bumps 13 a , through the contacts 11 a , the circuit built-up layer 11 , the conductive portions 100 , the circuit built-up layer 11 and the contacts 11 b to the solder balls 13 b (or in a reverse order).
  • a metal material e.g., a copper circuit surface of the circuit built-up layer 11
  • a dielectric material of the package substrate 1 a e.g., a copper circuit surface of the circuit built-up layer 11
  • the heat dissipating efficiency of the package substrate 1 a is poor, and the heat will accumulate in the package substrate 1 a , which heats up the whole electronic package 1 and affects the overall performance (e.g., reducing the transmission speed and calculation speed) and lifespan of the electronic package 1 .
  • the package substrate 1 a does not meet the heat dissipating requirement.
  • the present disclosure provides a semiconductor package substrate, comprising: a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, the circuit structure comprising: at least one dielectric layer; and a circuit layer formed on the dielectric layer, wherein the circuit layer on the ball planting side includes a plurality of first solder pads and a plurality of second solder pads; a metal sheet having a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; a bonding material bonding the metal sheet onto the ball planting side of the circuit structure; and an insulation layer formed on the metal sheet and a hole wall of each of the second holes, and being free from being formed on a hole wall of each of the first holes.
  • the present disclosure further provides a method for fabricating a semiconductor package substrate, comprising: providing a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, wherein the circuit structure comprises: at least one dielectric layer; a circuit layer formed on the dielectric layer; and a plurality of first solder pads and a plurality of second solder pads disposed on the circuit layer on the ball planting side; bonding a metal sheet onto the ball planting side of the circuit structure via a bonding material; forming on the metal sheet a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; forming an insulation layer on the ball planting side of the circuit structure and the metal sheet; and removing a portion of the insulation layer on the first solder pads in the first holes and the second solder pads in the second holes, with the first and second solder pads exposed from the first and second holes, respectively, and the insulation layer remained on a hole wall of each of the second holes.
  • a plurality of conductive bumps are disposed on the chip mounting side of the circuit structure and bonded to at least one electronic component.
  • a plurality of first conductive elements are disposed on the first solder pads in the first holes and are in contact with the metal sheet.
  • a plurality of second conductive elements are disposed on the second solder pads in the second holes and are in contact with the insulation layer and in no contact with the metal sheet.
  • the present disclosure further provides an electronic package, comprising: the above-described semiconductor package substrate; and at least an electronic component disposed on the chip mounting side of the circuit structure.
  • an encapsulation layer is formed on the semiconductor package substrate and bonds the electronic component to the semiconductor package substrate.
  • the electronic component is disposed via a plurality of conductive bumps on the chip mounting side of the circuit structure.
  • the insulation layer is not formed in the first hole of the metal sheet, and the first conductive element that is used to be grounded can be in contact with the metal sheet. Therefore, the heat generated during a signal transmission process can be dissipated not only by the metal material and dielectric material of the semiconductor package substrate, but also by the metal sheet and the first conductive element.
  • the present disclosure prevents the heat from being accumulated in the semiconductor package substrate, so as to avoid overheating the entire electronic package. Therefore, the semiconductor package substrate meets the heat dissipating requirement, which ensures the overall performance and lifespan of the electronic package.
  • FIG. 1A is a cross-sectional view of an electronic package according to the prior art.
  • FIG. 1B is a bottom view of FIG. 1A .
  • FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package according to the present disclosure.
  • FIG. 2D ′ is a bottom view of FIG. 2D .
  • FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package 4 and a semiconductor package substrate 2 according to the present disclosure.
  • a circuit structure 2 a is provided.
  • the circuit structure 2 a has a chip mounting side 20 a and a ball planting side 20 b opposing the chip mounting side 20 a , on both of which an electronic component (e.g., a semiconductor chip, a passive element etc.) can be disposed.
  • the chip mounting side 20 a is an externally mounting side where a semiconductor chip is mounted.
  • the circuit structure 2 a comprises a core layer 20 and a plurality of conductive portions 200 formed therein.
  • the core layer 20 is made of a substrate composed of glass fiber and organic resin, such as bismaleimide triazine (BT), FR4, FR5 etc., or is made of a highly rigid organic substrate having a filler (e.g., SiO 2 ) and without glass fiber.
  • a via formation process such as mechanically drilling, laser drilling etc., is then performed on the substrate, and the conductive portions 200 are formed in the via.
  • the core layer 20 is a core substrate formed by an organic insulation material, such as an ajinomoto build-up film (ABF), a prepreg with or without glass fiber, or a molding compound, such as epoxy molding compound (EMC).
  • an organic insulation material such as an ajinomoto build-up film (ABF)
  • a prepreg with or without glass fiber or a molding compound, such as epoxy molding compound (EMC).
  • EMC epoxy molding compound
  • a highly rigid EMC of a low coefficient of thermal expansion (CTE) is used to form the core substrate.
  • the conductive portions 200 are composed of a single conductive pillar or a plurality of conductive pillars stacked on one another.
  • the circuit structure 2 a further comprises a built-up portion 21 disposed on the core layer 20 and having at least one dielectric layer 210 and a plurality of circuit layers 211 bonded to the dielectric layer 210 .
  • a plurality of solder pads 212 ′ are disposed on the outmost one of the circuit layers 211 of the chip mounting side 20 a of the circuit structure 2 a .
  • a plurality of first solder pads 212 e.g., grounded contacts
  • second solder pads 213 e.g., signal contacts
  • a solder resist layer 22 is formed on the built-up portion 21 on the chip mounting side 20 a of the circuit structure 2 a .
  • the dielectric layer 210 is made of a liquid epoxy resin, an ABF film, prepreg, EMC or photosensitive resin.
  • the solder resist layer 22 is made of graphene, solder ink, solder resist, ABF, a non-photosensitive dielectric material (e.g., EMC), or other suitable materials.
  • a number of the circuit layers 211 can be designed on demands.
  • a metal sheet 23 is bonded onto the ball planting side 20 b of the circuit structure 2 a via a bonding material 24 .
  • the metal sheet 23 is a steel board, a nickel alloy (an alloy 42) sheet, etc.
  • the bonding material 24 is an adhesive material.
  • the core layer 20 is replaced by a silicon substrate, and the built-up portion 21 is disposed on the silicon substrate, allowing the circuit structure 2 a to become a silicon interposer.
  • the circuit structure 2 a is a coreless layer.
  • a plurality of first holes 230 and a plurality of second holes 231 are formed on the metal sheet 23 and extended through the bonding material 24 , with a portion of the circuit layer (e.g., the first solder pads 212 ) exposed from the first holes 230 and the second solder pads 213 exposed from the second holes 231 .
  • the circuit layer e.g., the first solder pads 212
  • the metal sheet 23 is a steel board, a nickel alloy (an alloy 42) sheet, etc.
  • the bonding material 24 is an adhesive material.
  • an insulation layer 25 is formed on the first solder pads 212 , the second solder pads 213 , the metal sheet 23 and in the plurality of first holes 230 and second holes 231 .
  • the insulation layer 25 is made of a solder resist material having a high heat dissipating rate, such as graphene, or a general solder resist material, such as solder ink, solder mask, ABF or a non-photosensitive dielectric material (e.g., EMC).
  • a solder resist material having a high heat dissipating rate such as graphene
  • a general solder resist material such as solder ink, solder mask, ABF or a non-photosensitive dielectric material (e.g., EMC).
  • a portion of the insulation layer 25 (e.g., the entire insulation layer 25 in the first holes 230 and on the first solder pads 212 , and a portion of the insulation layer 25 in the second holes 231 and on the second solder pads 213 ) is removed, with the insulation layer 25 on the metal sheet 23 and hole walls of the second holes 231 remained, the first solder pads 212 being exposed from the first holes 230 , and the second solder pads 213 being exposed from the second holes 231 .
  • the insulation layer 25 covers the hole walls of the second holes 231 and does not cover the hole walls of the first holes 230 , and the insulation layer 25 is not formed in the first holes 230 .
  • a plurality of holes 220 are formed on the solder resist layer 22 , and the solder pads 212 ′ are exposed from the holes 220 .
  • the metal sheet 23 is disposed on the ball planting side 20 b , and the semiconductor package substrate 2 has the heat dissipating performance improved and temperature rising speed decreased.
  • a first conductive element 26 a is bonded onto the first solder pads 212 in the first holes 230 , and is in contact with the metal sheet 23 and the first solder pads 212 ; and a second conductive element 26 b is bonded onto the second solder pads 213 in the second holes 231 , and is in contact with the insulation layer 25 and the second solder pads 213 and in no contact with the metal sheet 23 .
  • first and second conductive elements 26 a and 26 b comprise a solder material, such as solder balls.
  • At least one electronic component 40 is disposed on the exposed solder pads 212 ′ on the chip mounting side 20 a of the circuit structure 2 a , and an encapsulation layer 41 is formed on the chip mounting side 20 a of the circuit structure 2 a and is bonded and secured to the electronic component 40 , to form an electronic package 4 .
  • the electronic component 40 is an active element, such as a semiconductor chip, a passive element, such as a resistor, a capacitor and an inductor, or a combination thereof.
  • the electronic component 40 is a semiconductor chip electrically connected to the solder pads 212 ′ in a flip-chip manner via a plurality of solder-containing conductive bumps 27 .
  • the electronic component 40 is electrically connected to the solder pads 212 ′ in a wire bonding manner via a plurality of solder wires (not shown).
  • the electronic component can also be electrically connected to the semiconductor package substrate 2 in other manners.
  • the electronic component is embedded in the built-up portion 21 .
  • the encapsulation layer 41 is an underfill, and is formed between the chip mounting side 20 a of the circuit structure 2 a and the electronic component 40 to encapsulate the conductive bumps 27 .
  • the encapsulation layer is a thin film used in a compressing process, an encapsulant used in a molding process, or a glue material used in a printing process, and encapsulates the electronic component 40 and the conductive bumps 27 .
  • the encapsulating layer 41 is made of polyimide (PI), epoxy resin, or a molding compound. It should be understood that the electronic component 40 can be packaged in other manners.
  • the insulation layer 25 is not formed in the first holes 230 of the metal sheet 23 , and the first conductive element 26 a that is used to be grounded can be in contact with the metal sheet 23 , thereby increasing the heat dissipating speed of the semiconductor package substrate 2 .
  • the electronic package 4 transmits signals from the electronic component 40 , through the conductive bumps 27 , the solder pads 212 ′, the circuit layers 211 of the built-up portion 21 , the conductive portions 200 , the circuit layers 211 of the built-up portion 21 and the second solder pads 213 to the second conductive element 26 b (or in a reverse order).
  • the heat generated during a signal transmission process can be dissipated not only by the metal material (e.g., the copper surface of the circuit layers 211 of the built-up portion 21 ) and the dielectric layer 210 of the semiconductor package substrate 2 , but also by the metal sheet 23 and the first conductive element 26 a.
  • the metal material e.g., the copper surface of the circuit layers 211 of the built-up portion 21
  • the dielectric layer 210 of the semiconductor package substrate 2 but also by the metal sheet 23 and the first conductive element 26 a.
  • the insulation layer 25 of the semiconductor package substrate 2 uses a high thermal conductive material (e.g., graphene) as the solder resist layer, and has the thermal conductivity further increased. Therefore, the insulation layer 25 not only has the solder resist function, but can also improve the heat dissipating performance of the semiconductor package substrate 2 and stabilize the overall performance and lifespan of the electronic package 4 .
  • a high thermal conductive material e.g., graphene
  • the first conductive element 26 a that is used to be grounded can be in contact with the metal sheet 23 via the structural features inside the metal sheet 23 and the first holes 230 , to allow the heat generated during the signal transmission process to be dissipated by the metal sheet 23 and the first conductive element 26 a , and thereby improving the heat dissipating performance of the semiconductor package substrate 2 .
  • the semiconductor package substrate 2 according to the present disclosure has great heat dissipating performance, and can prevent the entire electronic package 4 from heating up. Therefore, the semiconductor package substrate 2 according to the present disclosure can meet the heat dissipating requirement of the electronic package 4 , and ensure the overall performance (e.g., the transmission speed or calculation speed) and lifespan of the electronic package 4 .

Abstract

A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Taiwanese Application Serial No. 108119907, filed on Jun. 10, 2019. The entirety of the application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND 1. Technical Field
The present disclosure relates to package substrates, and, more particularly, to a carrier substrate that can dissipate heat and an electronic package having the carrier substrate.
2. Description of the Prior Art
In recent years, more and more large size chips, such as artificial intelligence (AI) chips, advanced chips, or stacked chips have come to the market. Accordingly, sophisticated fabrication processes, such as 3D or 2.5D IC fabrication process, are developed and applied to advanced products, such as AI chips, GPU, etc., which require high density circuits/high transmission speed/high number of stacked layer/large size.
Accordingly, fabricators use a large-sized flip-chip package substrate, such as one with board size of 40*40, 70*70, or more, to carry the AI chips, advanced chips or stacked chips, which have a large size.
As shown in FIG. 1A, an electronic package 1 according to the prior art comprises a package substrate 1 a and a semiconductor chip 19 bonded onto the package substrate 1 a. The package substrate 1 a includes a core layer 10, a circuit built-up layer 11 formed on the core layer 10, and a solder resist layer 12 formed on the circuit built-up layer 11. The solder resist layer 12 is exposed from an outermost one of circuit layers of the circuit built-up layer 11 and is used as contacts (i.e., I/O) 11 a and 11 b, for the semiconductor chip 19 to be mounted on an upper side thereof via solder bumps 13 a and a circuit board (not shown) to be mounted on a lower side thereof (e.g., the ball planting side or BGA shown in FIG. 1B) via solder balls 13 b.
In the fabrication of the core layer 10, a substrate composed of glass fiber and epoxy resin is used, such as bismaleimide triazine (BT), FR4, FR5 etc., a via formation process, such as mechanically drilling, laser drilling or dual-cone-shaped-via processes, is performed on the substrate, and an electroplating process is performed on the vias to form conductive portions 100. The circuit built-up layer 11 is formed by using ABF as a dielectric layer. The solder resist layer 12 is made of solder resist or solder ink.
The signals of the package substrate 1 a are transmitted from the solder bumps 13 a, through the contacts 11 a, the circuit built-up layer 11, the conductive portions 100, the circuit built-up layer 11 and the contacts 11 b to the solder balls 13 b (or in a reverse order). When the signals are transmitted, heat is generated and is dissipated by a metal material (e.g., a copper circuit surface of the circuit built-up layer 11) and a dielectric material of the package substrate 1 a.
However, the heat dissipating efficiency of the package substrate 1 a is poor, and the heat will accumulate in the package substrate 1 a, which heats up the whole electronic package 1 and affects the overall performance (e.g., reducing the transmission speed and calculation speed) and lifespan of the electronic package 1. The package substrate 1 a does not meet the heat dissipating requirement.
Therefore, how to solve the problems of the prior art is becoming an urgent issue in the art.
SUMMARY
In view of the drawbacks of the prior art, the present disclosure provides a semiconductor package substrate, comprising: a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, the circuit structure comprising: at least one dielectric layer; and a circuit layer formed on the dielectric layer, wherein the circuit layer on the ball planting side includes a plurality of first solder pads and a plurality of second solder pads; a metal sheet having a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; a bonding material bonding the metal sheet onto the ball planting side of the circuit structure; and an insulation layer formed on the metal sheet and a hole wall of each of the second holes, and being free from being formed on a hole wall of each of the first holes.
The present disclosure further provides a method for fabricating a semiconductor package substrate, comprising: providing a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, wherein the circuit structure comprises: at least one dielectric layer; a circuit layer formed on the dielectric layer; and a plurality of first solder pads and a plurality of second solder pads disposed on the circuit layer on the ball planting side; bonding a metal sheet onto the ball planting side of the circuit structure via a bonding material; forming on the metal sheet a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom; forming an insulation layer on the ball planting side of the circuit structure and the metal sheet; and removing a portion of the insulation layer on the first solder pads in the first holes and the second solder pads in the second holes, with the first and second solder pads exposed from the first and second holes, respectively, and the insulation layer remained on a hole wall of each of the second holes.
In an embodiment, a plurality of conductive bumps are disposed on the chip mounting side of the circuit structure and bonded to at least one electronic component.
In an embodiment, a plurality of first conductive elements are disposed on the first solder pads in the first holes and are in contact with the metal sheet.
In an embodiment, a plurality of second conductive elements are disposed on the second solder pads in the second holes and are in contact with the insulation layer and in no contact with the metal sheet.
The present disclosure further provides an electronic package, comprising: the above-described semiconductor package substrate; and at least an electronic component disposed on the chip mounting side of the circuit structure.
In an embodiment, an encapsulation layer is formed on the semiconductor package substrate and bonds the electronic component to the semiconductor package substrate.
In an embodiment, the electronic component is disposed via a plurality of conductive bumps on the chip mounting side of the circuit structure.
It is known from the above that in the semiconductor package substrate, the method for fabricating the same, and the electronic package having the same according to the present disclosure, the insulation layer is not formed in the first hole of the metal sheet, and the first conductive element that is used to be grounded can be in contact with the metal sheet. Therefore, the heat generated during a signal transmission process can be dissipated not only by the metal material and dielectric material of the semiconductor package substrate, but also by the metal sheet and the first conductive element. Compared with the prior art, the present disclosure prevents the heat from being accumulated in the semiconductor package substrate, so as to avoid overheating the entire electronic package. Therefore, the semiconductor package substrate meets the heat dissipating requirement, which ensures the overall performance and lifespan of the electronic package.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a cross-sectional view of an electronic package according to the prior art.
FIG. 1B is a bottom view of FIG. 1A.
FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package according to the present disclosure.
FIG. 2D′ is a bottom view of FIG. 2D.
 DETAILED DESCRIPTION
The following illustrative embodiments are provided to illustrate the present disclosure, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification.
It should be appreciated that the structures, proportions, size and the like of the figures in the present disclosure are intended to be used in conjunction with the disclosure of the specification. They are not intended to limit the invention and therefore do not represent any substantial technical meanings. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present disclosure. As used herein, the terms “over,” “first,” “second,” “a” and the like, are used to distinguish one element from another, and are not intended to limit the scope of the present disclosure. Changes or adjustments are considered to be within the scope of the present disclosure, without departing from the scope of the present disclosure.
FIGS. 2A to 2E are cross-sectional views illustrating a method for fabricating an electronic package 4 and a semiconductor package substrate 2 according to the present disclosure.
As shown in FIG. 2A, a circuit structure 2 a is provided. The circuit structure 2 a has a chip mounting side 20 a and a ball planting side 20 b opposing the chip mounting side 20 a, on both of which an electronic component (e.g., a semiconductor chip, a passive element etc.) can be disposed. The chip mounting side 20 a is an externally mounting side where a semiconductor chip is mounted.
In an embodiment, the circuit structure 2 a comprises a core layer 20 and a plurality of conductive portions 200 formed therein. In an embodiment, the core layer 20 is made of a substrate composed of glass fiber and organic resin, such as bismaleimide triazine (BT), FR4, FR5 etc., or is made of a highly rigid organic substrate having a filler (e.g., SiO2) and without glass fiber. A via formation process, such as mechanically drilling, laser drilling etc., is then performed on the substrate, and the conductive portions 200 are formed in the via. In another embodiment, the core layer 20 is a core substrate formed by an organic insulation material, such as an ajinomoto build-up film (ABF), a prepreg with or without glass fiber, or a molding compound, such as epoxy molding compound (EMC). In yet another embodiment, a highly rigid EMC of a low coefficient of thermal expansion (CTE) is used to form the core substrate. In still another embodiment, the conductive portions 200 are composed of a single conductive pillar or a plurality of conductive pillars stacked on one another.
The circuit structure 2 a further comprises a built-up portion 21 disposed on the core layer 20 and having at least one dielectric layer 210 and a plurality of circuit layers 211 bonded to the dielectric layer 210. A plurality of solder pads 212′ are disposed on the outmost one of the circuit layers 211 of the chip mounting side 20 a of the circuit structure 2 a. A plurality of first solder pads 212 (e.g., grounded contacts) and second solder pads 213 (e.g., signal contacts) are disposed on the outermost one of the circuit layers 211 of the ball planting side 20 b of the circuit structure 2 a. A solder resist layer 22 is formed on the built-up portion 21 on the chip mounting side 20 a of the circuit structure 2 a. In an embodiment, the dielectric layer 210 is made of a liquid epoxy resin, an ABF film, prepreg, EMC or photosensitive resin. In another embodiment, the solder resist layer 22 is made of graphene, solder ink, solder resist, ABF, a non-photosensitive dielectric material (e.g., EMC), or other suitable materials. A number of the circuit layers 211 can be designed on demands.
A metal sheet 23 is bonded onto the ball planting side 20 b of the circuit structure 2 a via a bonding material 24. In an embodiment, the metal sheet 23 is a steel board, a nickel alloy (an alloy 42) sheet, etc. In another embodiment, the bonding material 24 is an adhesive material.
In another embodiment, the core layer 20 is replaced by a silicon substrate, and the built-up portion 21 is disposed on the silicon substrate, allowing the circuit structure 2 a to become a silicon interposer. In yet another embodiment, the circuit structure 2 a is a coreless layer.
As shown in FIG. 2B, a plurality of first holes 230 and a plurality of second holes 231 are formed on the metal sheet 23 and extended through the bonding material 24, with a portion of the circuit layer (e.g., the first solder pads 212) exposed from the first holes 230 and the second solder pads 213 exposed from the second holes 231.
In an embodiment, the metal sheet 23 is a steel board, a nickel alloy (an alloy 42) sheet, etc. In another embodiment, the bonding material 24 is an adhesive material.
As shown in FIG. 2C, an insulation layer 25 is formed on the first solder pads 212, the second solder pads 213, the metal sheet 23 and in the plurality of first holes 230 and second holes 231.
In an embodiment, the insulation layer 25 is made of a solder resist material having a high heat dissipating rate, such as graphene, or a general solder resist material, such as solder ink, solder mask, ABF or a non-photosensitive dielectric material (e.g., EMC).
As shown in FIGS. 2D and 2D′, a portion of the insulation layer 25 (e.g., the entire insulation layer 25 in the first holes 230 and on the first solder pads 212, and a portion of the insulation layer 25 in the second holes 231 and on the second solder pads 213) is removed, with the insulation layer 25 on the metal sheet 23 and hole walls of the second holes 231 remained, the first solder pads 212 being exposed from the first holes 230, and the second solder pads 213 being exposed from the second holes 231.
In an embodiment, the insulation layer 25 covers the hole walls of the second holes 231 and does not cover the hole walls of the first holes 230, and the insulation layer 25 is not formed in the first holes 230.
In an embodiment, a plurality of holes 220 are formed on the solder resist layer 22, and the solder pads 212′ are exposed from the holes 220.
In the semiconductor package substrate 2 according to the present disclosure, the metal sheet 23 is disposed on the ball planting side 20 b, and the semiconductor package substrate 2 has the heat dissipating performance improved and temperature rising speed decreased.
As shown in FIG. 2E, a first conductive element 26 a is bonded onto the first solder pads 212 in the first holes 230, and is in contact with the metal sheet 23 and the first solder pads 212; and a second conductive element 26 b is bonded onto the second solder pads 213 in the second holes 231, and is in contact with the insulation layer 25 and the second solder pads 213 and in no contact with the metal sheet 23.
In an embodiment, the first and second conductive elements 26 a and 26 b comprise a solder material, such as solder balls.
At least one electronic component 40 is disposed on the exposed solder pads 212′ on the chip mounting side 20 a of the circuit structure 2 a, and an encapsulation layer 41 is formed on the chip mounting side 20 a of the circuit structure 2 a and is bonded and secured to the electronic component 40, to form an electronic package 4.
In an embodiment, the electronic component 40 is an active element, such as a semiconductor chip, a passive element, such as a resistor, a capacitor and an inductor, or a combination thereof. In another embodiment, the electronic component 40 is a semiconductor chip electrically connected to the solder pads 212′ in a flip-chip manner via a plurality of solder-containing conductive bumps 27. In yet another embodiment, the electronic component 40 is electrically connected to the solder pads 212′ in a wire bonding manner via a plurality of solder wires (not shown). The electronic component can also be electrically connected to the semiconductor package substrate 2 in other manners. In still another embodiment, the electronic component is embedded in the built-up portion 21.
In an embodiment, the encapsulation layer 41 is an underfill, and is formed between the chip mounting side 20 a of the circuit structure 2 a and the electronic component 40 to encapsulate the conductive bumps 27. In another embodiment, the encapsulation layer is a thin film used in a compressing process, an encapsulant used in a molding process, or a glue material used in a printing process, and encapsulates the electronic component 40 and the conductive bumps 27. In yet another embodiment, the encapsulating layer 41 is made of polyimide (PI), epoxy resin, or a molding compound. It should be understood that the electronic component 40 can be packaged in other manners.
In the semiconductor package substrate 2 and the electronic package 4 having the semiconductor package substrate 2 according to the present disclosure, the insulation layer 25 is not formed in the first holes 230 of the metal sheet 23, and the first conductive element 26 a that is used to be grounded can be in contact with the metal sheet 23, thereby increasing the heat dissipating speed of the semiconductor package substrate 2. In an embodiment, the electronic package 4 transmits signals from the electronic component 40, through the conductive bumps 27, the solder pads 212′, the circuit layers 211 of the built-up portion 21, the conductive portions 200, the circuit layers 211 of the built-up portion 21 and the second solder pads 213 to the second conductive element 26 b (or in a reverse order). Therefore, the heat generated during a signal transmission process can be dissipated not only by the metal material (e.g., the copper surface of the circuit layers 211 of the built-up portion 21) and the dielectric layer 210 of the semiconductor package substrate 2, but also by the metal sheet 23 and the first conductive element 26 a.
In an embodiment, the insulation layer 25 of the semiconductor package substrate 2 uses a high thermal conductive material (e.g., graphene) as the solder resist layer, and has the thermal conductivity further increased. Therefore, the insulation layer 25 not only has the solder resist function, but can also improve the heat dissipating performance of the semiconductor package substrate 2 and stabilize the overall performance and lifespan of the electronic package 4.
In the semiconductor package substrate 2 and the electronic package 4 having the semiconductor package substrate 2 according to the present disclosure, the first conductive element 26 a that is used to be grounded can be in contact with the metal sheet 23 via the structural features inside the metal sheet 23 and the first holes 230, to allow the heat generated during the signal transmission process to be dissipated by the metal sheet 23 and the first conductive element 26 a, and thereby improving the heat dissipating performance of the semiconductor package substrate 2. Compared with the prior art, the semiconductor package substrate 2 according to the present disclosure has great heat dissipating performance, and can prevent the entire electronic package 4 from heating up. Therefore, the semiconductor package substrate 2 according to the present disclosure can meet the heat dissipating requirement of the electronic package 4, and ensure the overall performance (e.g., the transmission speed or calculation speed) and lifespan of the electronic package 4.
The foregoing descriptions of the detailed embodiments are illustrated to disclose the features and functions of the present disclosure and not restrictive of the scope of the present disclosure. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the present disclosure should fall within the scope of the appended claims.

Claims (8)

What is claimed is:
1. A semiconductor package substrate, comprising:
a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, the circuit structure comprising:
at least one dielectric layer; and
a circuit layer formed on the at least one dielectric layer,
wherein the circuit layer on the ball planting side includes a plurality of first solder pads and a plurality of second solder pads;
a metal sheet having a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom;
a bonding material bonding the metal sheet onto the ball planting side of the circuit structure, wherein the bonding material is an adhesive material electrically isolating between the metal sheet and the circuit structure;
an insulation layer formed on the metal sheet and a hole wall of each of the second holes, and being free from being formed on a hole wall of each of the first holes;
a plurality of first conductive elements bonded onto the first solder pads in the first holes and being in contact with the metal sheet; and
a plurality of second conductive elements bonded onto the second solder pads in the second holes and being in contact with the insulation layer and in no contact with the metal sheet.
2. An electronic package, comprising:
the semiconductor package substrate of claim 1; and
at least an electronic component disposed on the chip mounting side of the circuit structure.
3. The electronic package of claim 2, further comprising an encapsulation layer formed on the semiconductor package substrate and bonding the electronic component onto the semiconductor package substrate.
4. The electronic package of claim 2, further comprising a plurality of conductive bumps, wherein the electronic component is disposed on the chip mounting side of the circuit structure via the conductive bumps.
5. A method for fabricating a semiconductor package substrate, comprising:
providing a circuit structure having a chip mounting side and a ball planting side opposing the chip mounting side, wherein the circuit structure comprises:
at least one dielectric layer;
a circuit layer formed on the at least one dielectric layer; and
a plurality of first solder pads and a plurality of second solder pads disposed on the circuit layer on the ball planting side;
bonding a metal sheet onto the ball planting side of the circuit structure via a bonding material;
forming on the metal sheet a plurality of first holes for the first solder pads to be exposed therefrom, and a plurality of second holes for the second solder pads to be exposed therefrom;
forming an insulation layer on the ball planting side of the circuit structure and the metal sheet; and
removing a portion of the insulation layer on the first solder pads in the first holes and the second solder pads in the second holes, with the first and second solder pads exposed from the first and second holes, respectively, and the insulation layer remained on a hole wall of each of the second holes.
6. The method of claim 5, further comprising disposing on the first solder pads in the first holes a plurality of first conductive elements in contact with the metal sheet.
7. The method of claim 5, further comprising disposing on the second solder pads in the second holes a plurality of second conductive elements in contact with the insulation layer and in no contact with the metal sheet.
8. The method of claim 5, further comprising disposing a plurality of conductive bumps on the chip mounting side of the circuit structure, and bonding the conductive bumps to an electronic component.
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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050062147A1 (en) * 2003-09-19 2005-03-24 Casio Computer Co., Ltd. Semiconductor device having heat dissipation layer
US20070262441A1 (en) * 2006-05-09 2007-11-15 Chi-Ming Chen Heat sink structure for embedded chips and method for fabricating the same
US20080210459A1 (en) * 2007-03-02 2008-09-04 Phoenix Precision Technology Corporation Warpage-proof circuit board structure
US20130342231A1 (en) * 2012-06-21 2013-12-26 Michael Alfano Semiconductor substrate with onboard test structure
US20150060114A1 (en) * 2013-09-02 2015-03-05 Samsung Electro-Mechanics Co., Ltd. Rigid flexible pcb and method for manufacturing the same
US20190371704A1 (en) * 2018-05-30 2019-12-05 Unimicron Technology Corp. Package carrier having a mesh gas-permeable structure disposed in the through hole

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330471A (en) * 1995-06-05 1996-12-13 Fujitsu Ltd Semiconductor device and its manufacture
KR0163871B1 (en) * 1995-11-25 1998-12-01 김광호 Heat sink solder ball array package
JP2751913B2 (en) * 1996-03-28 1998-05-18 日本電気株式会社 Package for semiconductor device
JPH10112472A (en) * 1996-10-07 1998-04-28 Toshiba Corp Semiconductor device and its manufacture
JP5228843B2 (en) * 2008-11-28 2013-07-03 富士通株式会社 Semiconductor device mounting substrate and semiconductor device
KR101103302B1 (en) * 2009-10-08 2012-01-11 엘지이노텍 주식회사 Printed circuit board and method for manufacturing same
WO2013054504A1 (en) * 2011-10-13 2013-04-18 住友ベークライト株式会社 Semiconductor package and semiconductor device
TW201448139A (en) * 2013-06-03 2014-12-16 Powertech Technology Inc Embedded substrate package and the method of making the same
TWI550801B (en) * 2013-11-13 2016-09-21 南茂科技股份有限公司 Package structure and manufacturing method of the same
TWI579994B (en) * 2014-06-26 2017-04-21 Siliconware Precision Industries Co Ltd Package structure
TWI612650B (en) * 2015-01-16 2018-01-21 恆勁科技股份有限公司 Electronic package structure
TW201640590A (en) * 2015-05-04 2016-11-16 矽品精密工業股份有限公司 Electronic package structure and the manufacture thereof
TW201822331A (en) * 2016-08-18 2018-06-16 鳳凰先驅股份有限公司 Electronic package
TWI591788B (en) * 2016-08-18 2017-07-11 恆勁科技股份有限公司 Method for manufacturing electronic package
TWI613729B (en) * 2016-09-23 2018-02-01 恆勁科技股份有限公司 Substrate structure and the manufacture thereof
US10515827B2 (en) * 2017-10-31 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package with recessed interposer substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050062147A1 (en) * 2003-09-19 2005-03-24 Casio Computer Co., Ltd. Semiconductor device having heat dissipation layer
US20070262441A1 (en) * 2006-05-09 2007-11-15 Chi-Ming Chen Heat sink structure for embedded chips and method for fabricating the same
US20080210459A1 (en) * 2007-03-02 2008-09-04 Phoenix Precision Technology Corporation Warpage-proof circuit board structure
US20130342231A1 (en) * 2012-06-21 2013-12-26 Michael Alfano Semiconductor substrate with onboard test structure
US20150060114A1 (en) * 2013-09-02 2015-03-05 Samsung Electro-Mechanics Co., Ltd. Rigid flexible pcb and method for manufacturing the same
US20190371704A1 (en) * 2018-05-30 2019-12-05 Unimicron Technology Corp. Package carrier having a mesh gas-permeable structure disposed in the through hole

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