TWI579994B - Package structure - Google Patents
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- TWI579994B TWI579994B TW103122045A TW103122045A TWI579994B TW I579994 B TWI579994 B TW I579994B TW 103122045 A TW103122045 A TW 103122045A TW 103122045 A TW103122045 A TW 103122045A TW I579994 B TWI579994 B TW I579994B
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- Prior art keywords
- package structure
- metal edge
- edge portion
- encapsulant
- electronic component
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- 229910052751 metal Inorganic materials 0.000 claims description 166
- 239000002184 metal Substances 0.000 claims description 166
- 239000008393 encapsulating agent Substances 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000084 colloidal system Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000011152 fibreglass Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 156
- 238000000034 method Methods 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 19
- 235000012431 wafers Nutrition 0.000 description 19
- 230000008569 process Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 9
- 239000007769 metal material Substances 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000003685 thermal hair damage Effects 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000002679 ablation Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- JHJNPOSPVGRIAN-SFHVURJKSA-N n-[3-[(1s)-1-[[6-(3,4-dimethoxyphenyl)pyrazin-2-yl]amino]ethyl]phenyl]-5-methylpyridine-3-carboxamide Chemical compound C1=C(OC)C(OC)=CC=C1C1=CN=CC(N[C@@H](C)C=2C=C(NC(=O)C=3C=C(C)C=NC=3)C=CC=2)=N1 JHJNPOSPVGRIAN-SFHVURJKSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明提供一種封裝結構，尤指一種具有散熱功能及圍繞電子元件之周圍金屬邊緣部的封裝結構。 The present invention provides a package structure, and more particularly to a package structure having a heat dissipation function and surrounding a metal edge portion of the electronic component.
習知用於板材(Substrate Panel)結構或晶圓形式之排列結構的半導體封裝件切單技術是使用刀切方式，但是其最大可切單版面尺寸僅止於12吋，約300毫米見方大小，而若使用雷射切單技術，則最大可切單版面尺寸可以達到500毫米見方。 It is conventional to use a knife-cutting method for a semiconductor package singulation technique for a Substrate Panel structure or a wafer-type arrangement structure, but the maximum singable stencil size is only about 12 吋, about 300 mm square. With the laser singulation technology, the maximum singable stencil size can reach 500 mm square.
請參照第1及1’圖，其分別係例如為由習知之扇出(fan out)結構的半導體封裝件所組成之整版面之封裝結構的剖視圖及俯視圖，但為了方便說明，第1圖僅顯示第1’圖之一部分。整版面之封裝結構1’係由陣列排列之複數封裝結構1所組成，封裝結構1係包括晶片11、封裝膠體10、導電開口131、介電層132及線路層133。 Please refer to FIG. 1 and FIG. 1 respectively, which are respectively a cross-sectional view and a plan view of a package structure of a full-face surface composed of a conventional semiconductor package having a fan out structure, but for convenience of description, FIG. 1 only shows Show a part of the 1' diagram. The package structure 1' of the entire layout is composed of a plurality of package structures 1 arranged in an array. The package structure 1 includes a wafer 11, an encapsulant 10, a conductive opening 131, a dielectric layer 132, and a wiring layer 133.
如上所述之封裝膠體10具有相對之第一表面10a及第二表面10b，複數晶片11係嵌埋於封裝膠體10中，並外露出第一表面10a，而晶片11具有相對之非作用面11b及作用面11a，而作用面11a具有電極墊111且作用面11a 外露出第一表面10a。 The encapsulant 10 as described above has a first surface 10a and a second surface 10b opposite thereto, the plurality of wafers 11 are embedded in the encapsulant 10, and the first surface 10a is exposed, and the wafer 11 has a non-active surface 11b. And the action surface 11a, and the active surface 11a has the electrode pad 111 and the active surface 11a The first surface 10a is exposed.
如上所述之介電層132形成在封裝膠體10之第一表面10a及作用面11a上，導電開口131形成在介電層132中且電性連接電極墊111，線路層133形成在介電層132上並電性連接導電開口131，並且線路層133上可形成有銲球15，而導電開口131、介電層132及線路層133係構成一重佈線層(Re-distribution layer，RDL)13。相鄰封裝結構1之間具有一間距P1，以做為後續雷射切單所需空間。而在以雷射(未圖示)切單習知之整版面之封裝結構1’時，由於封裝膠體10及各相鄰重佈線層13係彼此相連，且封裝膠體10之封裝膠體材料及各相鄰重佈線層13中的介電層132之介電材料係為導熱甚差、熔點較低或二者之膨脹係數差異較大的材料，因此，高熱之雷射往往造成介電層與線路層剝離、線路層損傷或封裝結構外觀燒蝕等等的熱損傷問題，從而在應用雷射切單整版面之封裝結構時大大地降低了封裝結構的生產良率及封裝結構的可靠性，並且由於上述生產良率及可靠性問題，仍無法導入用於12吋以上之整版面之封裝結構的雷射切單製程。 The dielectric layer 132 is formed on the first surface 10a and the active surface 11a of the encapsulant 10. The conductive opening 131 is formed in the dielectric layer 132 and electrically connected to the electrode pad 111. The circuit layer 133 is formed on the dielectric layer. The conductive opening 131 is electrically connected to the 132, and the solder ball 15 is formed on the circuit layer 133, and the conductive opening 131, the dielectric layer 132 and the wiring layer 133 form a redistribution layer (RDL) 13. 1 between adjacent package structure having a pitch P 1, as the space required subsequent to laser singulation. When the package structure 1' of the entire layout is cut by a laser (not shown), since the encapsulant 10 and the adjacent redistribution layers 13 are connected to each other, and the encapsulant colloid material and the phases of the encapsulant 10 are assembled. The dielectric material of the dielectric layer 132 in the adjacent heavy wiring layer 13 is a material having poor thermal conductivity, a low melting point, or a large difference in expansion coefficients between the two. Therefore, a high heat laser often causes a dielectric layer and a circuit layer. Thermal damage problems such as peeling, damage to the wiring layer or ablation of the package structure, etc., thereby greatly reducing the production yield of the package structure and the reliability of the package structure when applying the laser-cut single-package package structure, and The above-mentioned production yield and reliability problems still cannot be imported into a laser singulation process for a package structure of a full-face surface of 12 吋 or more.
有鑒於上述習知技術之缺失，本發明提供一種封裝件，係包括：具有相對之非作用面及作用面的電子元件，該作用面具有複數電極墊；用以包覆該電子元件且具有外露出該作用面的第一表面及相對該第一表面之第二表面的封裝膠體；形成在該封裝膠體及該作用面上的介電層；形 成在該介電層中且電性連接該些電極墊的複數導電開口；形成在該介電層上並電性連接該些導電開口的線路層；以及連接於該封裝膠體的金屬邊緣部，其中，該金屬邊緣部所圍繞之範圍係用以定義出一封裝結構，且該金屬邊緣部係電性獨立於該線路層及電子元件。 In view of the above-mentioned shortcomings of the prior art, the present invention provides a package comprising: an electronic component having a relatively non-active surface and an active surface, the active surface having a plurality of electrode pads; a first surface of the active surface and an encapsulant opposite to the second surface of the first surface; a dielectric layer formed on the encapsulant and the active surface; a plurality of conductive openings formed in the dielectric layer and electrically connected to the electrode pads; a circuit layer formed on the dielectric layer and electrically connecting the conductive openings; and a metal edge portion connected to the encapsulant, The range around the metal edge portion is used to define a package structure, and the metal edge portion is electrically independent of the circuit layer and the electronic component.
本發明亦提供一種整版面之封裝結構，係包括：承載板；具有相對之非作用面及作用面之複數電子元件，該作用面具有複數電極墊；包覆該些電子元件的封裝膠體，且該封裝膠體具有外露出該作用面的第一表面及相對該第一表面之第二表面，該第二表面連接該承載板；形成在該封裝膠體及該作用面上的介電層；形成在該介電層中且電性連接該些電極墊的複數導電開口；形成在該介電層上並電性連接該些導電開口的線路層；以及連接於該封裝膠體的複數金屬邊緣部，其中，各該金屬邊緣部所圍繞之範圍係用以定義出一封裝結構，且該金屬邊緣部係電性獨立於該線路層及電子元件。 The present invention also provides a package structure of a full-page, comprising: a carrier plate; a plurality of electronic components having opposite non-active surfaces and active surfaces, the active surface having a plurality of electrode pads; an encapsulant covering the electronic components, and The encapsulant has a first surface exposing the active surface and a second surface opposite to the first surface, the second surface is connected to the carrier plate; a dielectric layer formed on the encapsulant and the active surface; a plurality of conductive openings in the dielectric layer and electrically connected to the electrode pads; a circuit layer formed on the dielectric layer and electrically connecting the conductive openings; and a plurality of metal edge portions connected to the encapsulant, wherein The range around the metal edge portion is used to define a package structure, and the metal edge portion is electrically independent of the circuit layer and the electronic component.
本發明又提供一種封裝結構，係包括：具有線路層及絕緣層的基板本體；連接於該基板本體且具有相對之非作用面及作用面的電子元件，其中，該作用面具有電性連接該線路層的複數電極墊；以及連接於該基板本體的金屬邊緣部，其中，該金屬邊緣部所圍繞之範圍係用以定義出一封裝結構，且該金屬邊緣部係電性獨立於該線路層及電子元件。 The present invention further provides a package structure, comprising: a substrate body having a circuit layer and an insulating layer; and an electronic component connected to the substrate body and having a relatively non-active surface and an active surface, wherein the active surface has an electrical connection a plurality of electrode pads of the circuit layer; and a metal edge portion connected to the substrate body, wherein the metal edge portion is surrounded by a range for defining a package structure, and the metal edge portion is electrically independent of the circuit layer And electronic components.
本發明復提供一種整版面之封裝結構，係包括：具有 線路層及絕緣層的基板本體；連接於該基板本體且具有相對之非作用面及作用面的複數電子元件，而該些電子元件係對該基板本體為分離排列，其中，該作用面具有電性連接該線路層的複數電極墊；以及連接於該基板本體的複數金屬邊緣部，其中，各該金屬邊緣部所圍繞之範圍係用以定義出一封裝結構，且該金屬邊緣部係電性獨立於該線路層及該些電子元件。 The present invention provides a package structure of a full-page, comprising: having a substrate body of the circuit layer and the insulating layer; a plurality of electronic components connected to the substrate body and having opposite non-active surfaces and active surfaces, and the electronic components are separately arranged on the substrate body, wherein the active surface has electricity And a plurality of metal edge portions connected to the circuit layer; and a plurality of metal edge portions connected to the substrate body, wherein a range around the metal edge portion is used to define a package structure, and the metal edge portion is electrically connected Independent of the circuit layer and the electronic components.
本發明的封裝結構及其製法係藉由圍繞電子元件之各周圍金屬邊緣部而避免習知技術之在雷射燒灼相鄰周圍金屬邊緣部之間的介電材料、封裝膠體或其二者時所造成的諸多熱損傷問題，故本發明可大為提高封裝結構的生產良率及提升封裝結構的可靠性，從而可在12吋以上之整版面的封裝結構使用雷射切單製程。 The package structure of the present invention and its method of manufacture avoids the dielectric material, encapsulant, or both between the adjacent peripheral metal edge portions during laser ablation by surrounding the peripheral metal edge portions of the electronic component. The invention has many problems of thermal damage, so the invention can greatly improve the production yield of the package structure and improve the reliability of the package structure, so that the laser singulation process can be used in the package structure of the full-face surface of 12 吋 or more.
1、1’、2、2’、2a、2b‧‧‧封裝結構 1, 1', 2, 2', 2a, 2b‧‧‧ package structure
3‧‧‧雷射 3‧‧‧Laser
4‧‧‧第一阻層 4‧‧‧First barrier layer
5‧‧‧第二阻層 5‧‧‧second barrier layer
10、20‧‧‧封裝膠體 10, 20‧‧‧Package colloid
10a、20a‧‧‧第一表面 10a, 20a‧‧‧ first surface
10b、20b‧‧‧第二表面 10b, 20b‧‧‧ second surface
11‧‧‧晶片 11‧‧‧ wafer
11a、21a、51a‧‧‧作用面 11a, 21a, 51a‧‧‧ action surface
11b、21b、51b‧‧‧非作用面 11b, 21b, 51b‧‧‧ non-active surfaces
111、211、511‧‧‧電極墊 111, 211, 511‧‧ ‧ electrode pads
13、23‧‧‧重佈線層 13, 23‧‧‧Rewiring layer
131、231‧‧‧導電開口 131, 231‧‧‧ conductive openings
132、232、232’‧‧‧介電層 132, 232, 232'‧‧‧ dielectric layer
133、233、761‧‧‧線路層 133, 233, 761‧‧‧ circuit layer
15、25‧‧‧銲球 15, 25‧‧‧ solder balls
20c‧‧‧側表面 20c‧‧‧ side surface
201‧‧‧凹槽 201‧‧‧ Groove
21、51‧‧‧電子元件 21, 51‧‧‧ Electronic components
2321‧‧‧介電層凹部 2321‧‧‧ Dielectric layer recess
27‧‧‧承載板 27‧‧‧Bearing board
29‧‧‧金屬邊緣部 29‧‧‧Metal edge
29a‧‧‧附加金屬邊緣部 29a‧‧‧Additional metal edge
291‧‧‧缺口 291‧‧‧ gap
292‧‧‧延伸部 292‧‧‧Extension
76‧‧‧基板本體 76‧‧‧Substrate body
762‧‧‧絕緣層 762‧‧‧Insulation
78‧‧‧銲線 78‧‧‧welding line
D1、D2‧‧‧厚度 D 1 , D 2 ‧‧‧ thickness
P1、P2、P’‧‧‧間距 P 1 , P 2 , P'‧‧‧ spacing
第1及1’圖係分別為習知之整版面之封裝結構的剖視圖及俯視圖；第2A至2C圖係本發明之封裝結構的製法之一態樣的剖視圖，其中，第2B’圖係第2B圖的俯視圖，第2C’圖係第2C圖之另一態樣；第3A至3D圖係本發明之封裝結構的製法之另一態樣的剖視圖，其中，第3D’圖係第3D圖之另一態樣，而第3D”圖亦係第3D圖之另一態樣；第4A至4C圖係本發明之封裝結構的製法之另一態樣的剖視圖，其中，第4B’及4C’圖係與第4B及4C圖相關 之另一製法態樣；第5A至5C圖係本發明之封裝結構的製法之另一態樣的剖視圖，其中，第5B’圖係第5B圖的俯視圖；第6圖係本發明之封裝結構的另一態樣的剖視圖；以及第7A至7B圖係本發明之封裝結構的製法之另一態樣的剖視圖，其中，第7A’圖係與第7A圖相關之另一製法態樣。 1 and 1' are respectively a cross-sectional view and a plan view of a conventional package structure; 2A to 2C are cross-sectional views showing one aspect of the manufacturing method of the package structure of the present invention, wherein the 2B' diagram is 2B FIG. 3A to 3D are cross-sectional views showing another aspect of the method of fabricating the package structure of the present invention, wherein the 3D' figure is a 3D view. In another aspect, the 3D" diagram is another aspect of the 3D diagram; and 4A to 4C are cross-sectional views of another aspect of the method of fabricating the package structure of the present invention, wherein 4B' and 4C' The diagram is related to Figures 4B and 4C 5A to 5C are cross-sectional views showing another aspect of the method of fabricating the package structure of the present invention, wherein FIG. 5B is a plan view of FIG. 5B; and FIG. 6 is a package structure of the present invention. A cross-sectional view of another aspect of the invention; and Figures 7A through 7B are cross-sectional views of another aspect of the method of fabricating the package structure of the present invention, wherein the 7A' pattern is another aspect of the method associated with Figure 7A.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.
請參照第2A至2C及2B’圖，第2A至2C圖係本發明之封裝結構的製法之一態樣的剖視圖，而第2B’圖係第2B圖的俯視圖，第2C’圖係第2C圖之另一態樣，但為了方便說明，第2B圖僅顯示第2B’圖之一部分。 2A to 2C and 2B', FIG. 2A to FIG. 2C are cross-sectional views showing one aspect of the manufacturing method of the package structure of the present invention, and FIG. 2B' is a plan view of FIG. 2B, and FIG. 2C' is a second embodiment. Another aspect of the figure, but for convenience of explanation, FIG. 2B only shows a part of the 2B' diagram.
如第2A圖所示，本發明之封裝結構2的製法係首先提供其上形成有封裝膠體20的承載板27，封裝膠體20具有連接承載板27之第二表面20b及與其相對之第一表面20a，第一表面20a嵌埋且外露出複數電子元件21，其具有相對之非作用面21b及作用面21a，其中，作用面21a具有 複數電極墊211且作用面21a外露出第一表面20a。 As shown in FIG. 2A, the manufacturing method of the package structure 2 of the present invention first provides a carrier board 27 on which the encapsulant 20 is formed. The encapsulant 20 has a second surface 20b connecting the carrier board 27 and a first surface opposite thereto. 20a, the first surface 20a is embedded and exposed to the plurality of electronic components 21 having opposing non-active surfaces 21b and active surfaces 21a, wherein the active surface 21a has The plurality of electrode pads 211 and the active surface 21a expose the first surface 20a.
詳而言之但不限於此，如上所述之承載板27上可具有黏著層或離型層(皆未圖示)，以在製程中使封裝膠體20可暫時接置於承載板27上或在製程中可方便使承載板27其上之封裝膠體20從承載板27上剝離，然而，黏著層及離型層的設置方式已為習知，在此不再贅述；並且，複數電子元件21可為各種習知之半導體元件的形式，且係分離地嵌埋於封裝膠體20中，而半導體元件可例如為晶粒、晶片或已封裝之半導體元件(如晶片接置於矽中介層)等等，而晶粒及晶片可為單一或多層層疊的形式，亦可為單一或多層層疊之晶粒或晶片接置於例如為中介板上的形式。又為了使封裝結構2更加薄化或方便使用紅外線偵測電子元件21之電極墊211的位置，故第二表面20b可外露出電子元件21之非作用面21b。 In detail, but not limited to, the carrier board 27 as described above may have an adhesive layer or a release layer (all not shown) to temporarily place the encapsulant 20 on the carrier board 27 during the process or In the process, the encapsulating glue 20 on the carrier board 27 can be easily peeled off from the carrier board 27. However, the manner of setting the adhesive layer and the release layer is conventional, and will not be described herein; and, the plurality of electronic components 21 It can be in the form of various conventional semiconductor components, and is embedded in the encapsulant 20 separately, and the semiconductor component can be, for example, a die, a wafer or a packaged semiconductor component (such as a wafer placed on a germanium interposer), etc. The die and the wafer may be in the form of a single or multi-layer laminate, or a single or multi-layer laminated die or wafer may be placed in a form such as an interposer. Moreover, in order to make the package structure 2 thinner or to conveniently use the position of the electrode pad 211 of the infrared detecting electronic component 21, the second surface 20b can expose the non-active surface 21b of the electronic component 21.
接著如第2B圖所示，於電子元件21之作用面21a上形成電性連接電極墊211的複數導電開口231，並形成連接於封裝膠體20的複數金屬邊緣部29，而各金屬邊緣部29之平面投影圍繞電子元件21之平面投影，以使各金屬邊緣部29所圍繞之範圍定義出一封裝結構2，金屬邊緣部29之平面投影形狀可為具有封閉路徑的形狀，而特定而言，係矩形或方形(即長方形或正方形)，且在電子元件21之作用面21a及封裝膠體20上形成介電層232，其對應露出導電開口231，另在介電層232上形成電性連接導電開口231的線路層233，而於承載板27上構成如第2B’圖所 示的一整版面之封裝結構2’，整版面之封裝結構2’係由分離排列於承載板27上之複數封裝結構2所組成，更特定而言，整版面之封裝結構2’係由以陣列方式排列於承載板27上之複數封裝結構2所組成，而金屬邊緣部29之厚度D1與封裝結構2之厚度D2的比例介於0.1與1之間，另金屬邊緣部29係電性獨立於線路層233及電子元件21。 Next, as shown in FIG. 2B, a plurality of conductive openings 231 electrically connected to the electrode pads 211 are formed on the active surface 21a of the electronic component 21, and a plurality of metal edge portions 29 connected to the encapsulant 20 are formed, and the metal edge portions 29 are formed. The planar projection is projected around the plane of the electronic component 21 such that the range around which the metal edge portions 29 surround defines a package structure 2, and the planar projection shape of the metal edge portion 29 may be a shape having a closed path, and specifically, A rectangular or square shape (ie, a rectangle or a square) is formed, and a dielectric layer 232 is formed on the active surface 21a of the electronic component 21 and the encapsulant 20, which correspondingly exposes the conductive opening 231, and electrically connected on the dielectric layer 232. The wiring layer 233 of the opening 231 forms a full-package encapsulation structure 2' as shown in FIG. 2B' on the carrier board 27. The encapsulation structure 2' of the full-page surface is a plurality of packages which are separately arranged on the carrier board 27. structure composed of two, more particularly, the layout of the entire package 2 'arranged in an array based on a carrier plate on the plurality of package 27 consisting of 2, and the metal thickness of the edge portion 29 of the D 1 and 2 of the package thickness The ratio of D 2 is between 0.1 and 1, and the metal edge portion 29 is electrically independent of the wiring layer 233 and the electronic component 21.
詳而言之但不限於此，導電開口231、介電層232及線路層233係構成重佈線層(Re-distribution layer，RDL)23，而其與複數金屬邊緣部29之形成方式可依製程策略不同而變化，以下提供數種非限制實施例以供參照。 Specifically, but not limited thereto, the conductive opening 231, the dielectric layer 232, and the wiring layer 233 constitute a Re-distribution layer (RDL) 23, and the formation of the plurality of metal edge portions 29 can be performed according to the process. The strategy varies from one to several, and several non-limiting embodiments are provided below for reference.
在形成重佈線層23及複數金屬邊緣部29之一非限制實施例中，可先在封裝膠體20及電子元件21之作用面21a上形成材料例如為熱傳導係數(thermal conductivity)大於204瓦/(公尺*絕對溫度)(W/(m*K))的金屬、金屬合金或金屬混合物的金屬材料層(未圖示)，而更特定而言，金屬材料層之材料為銅、鋁、金、銀、鈦等等或其組合，之後圖案化該金屬材料層以形成電性連接電極墊211的導電開口231及分別位於複數電子元件21周圍之封裝膠體20的第一表面20a上的環繞的金屬材料層，而導電開口231之平面投影形狀的非限制性實施例可為多角形、橢圓形、圓形或梅花形，特定而言，導電開口231係為導電盲孔，另外，相鄰封裝結構2之間具有一間距P2，且其寬度可大於或等於後續雷射切單所需空間之間距P1；其後可在電子元件21之作用面21a及第一表面20a上形成介電層232，其 對應露出導電開口231及金屬邊緣部29，或者亦可採取其他適合的製程策略而使金屬邊緣部29的之厚度D1小於欲形成之介電層232的厚度，以在形成介電層232後使金屬邊緣部29嵌設於介電層232中(未圖示此情況)；最後在介電層232上形成電性連接導電開口231的線路層233並在環繞的金屬材料層上對應形成額外的金屬材料層(未圖示)，以使金屬邊緣部29的厚度大於導電開口231的厚度或等於導電開口231與線路層233之厚度和，又或者在另一實施例中，金屬邊緣部29可突出於線路層233，即金屬邊緣部29之頂面高於線路層233。 In a non-limiting embodiment in which the redistribution layer 23 and the plurality of metal edge portions 29 are formed, a material such as a thermal conductivity greater than 204 watts/(4) can be formed on the encapsulation 20 and the active surface 21a of the electronic component 21. Metal material layer (not shown) of metal, metal alloy or metal mixture (W/(m*K)), and more specifically, material of metal material layer is copper, aluminum, gold , silver, titanium, etc. or a combination thereof, after which the metal material layer is patterned to form a conductive opening 231 electrically connected to the electrode pad 211 and a surrounding surface on the first surface 20a of the encapsulant 20 surrounding the plurality of electronic components 21, respectively The metal material layer, and the non-limiting embodiment of the planar projection shape of the conductive opening 231 may be polygonal, elliptical, circular or quincunx. In particular, the conductive opening 231 is a conductive blind hole, and, in addition, adjacent packages 2 structure having a distance between P 2, and having a width equal to the distance or the space may be greater than the required single laser cut subsequent P 1; thereafter dielectric may be formed on the electronic component 21 of the acting surface 21a and the first surface 20a Layer 232, which corresponds to the exposed guide Opening 231 and the metal edge portions 29, or may take the thickness of the dielectric layer is less than 232 to be formed of other suitable process strategy metal edge portion 29 of thickness D, so that the edges of the metal layer after forming the dielectric 232 The portion 29 is embedded in the dielectric layer 232 (not shown); finally, a wiring layer 233 electrically connected to the conductive opening 231 is formed on the dielectric layer 232 and an additional metal material is formed on the surrounding metal material layer. a layer (not shown) such that the thickness of the metal edge portion 29 is greater than the thickness of the conductive opening 231 or equal to the thickness of the conductive opening 231 and the wiring layer 233, or in another embodiment, the metal edge portion 29 may protrude from The wiring layer 233, that is, the top surface of the metal edge portion 29 is higher than the wiring layer 233.
然而，在另一實施例中，可在形成線路層233時遮蔽金屬邊緣部29，以使金屬邊緣部29之厚度等於導電開口231之厚度。而在形成線路層233後，本發明可在線路層233上形成或接置銲球25。 However, in another embodiment, the metal edge portion 29 may be shielded when the wiring layer 233 is formed such that the thickness of the metal edge portion 29 is equal to the thickness of the conductive opening 231. After forming the wiring layer 233, the present invention can form or attach the solder balls 25 on the wiring layer 233.
另外，在以另一製程策略形成重佈線層23與複數金屬邊緣部29的實施例中，可先在封裝膠體20及電子元件21之作用面21a上形成圖案化之介電層232，接著形成導電開口231、線路層233及金屬邊緣部29。 In addition, in the embodiment in which the redistribution layer 23 and the plurality of metal edge portions 29 are formed by another process strategy, the patterned dielectric layer 232 may be formed on the encapsulation 20 and the active surface 21a of the electronic component 21, and then formed. Conductive opening 231, wiring layer 233 and metal edge portion 29.
值得注意的是，無論採取何種非限制性製程策略以使金屬邊緣部29的厚度大於或等於導電開口231的厚度、使金屬邊緣部29的厚度等於導電開口231與線路層233的厚度和、使金屬邊緣部29嵌設於介電層232中、或者使金屬邊緣部29突出於線路層233，僅須依照使金屬邊緣部29之厚度D1與封裝結構2之厚度D2的比例介於0.1與1之間 的規範即可，因此，只要遵循以上規範，可依需求變化製程策略而得到本發明的金屬邊緣部29之厚度D1。 It should be noted that no matter what non-limiting process strategy is adopted, the thickness of the metal edge portion 29 is greater than or equal to the thickness of the conductive opening 231, and the thickness of the metal edge portion 29 is equal to the thickness of the conductive opening 231 and the wiring layer 233, an edge portion of the metal 29 is embedded in the dielectric layer 232, or the edge portion 29 of the metal layer 233 protrudes to the circuit, only the edge portion of the metal to be in accordance with the thickness D 29 of the ratio of the thickness of the package 1 and D 2 is between the 2 The specification between 0.1 and 1 is sufficient. Therefore, as long as the above specifications are followed, the thickness D 1 of the metal edge portion 29 of the present invention can be obtained by changing the process strategy as required.
再者，請參照其為第2B圖之俯視圖的第2B’圖，其中金屬邊緣部29之平面投影形狀可如封裝結構2a般具有缺口291，且金屬邊緣部29可如封裝結構2b般復具有往電子元件21之平面投影方向延伸的延伸部292，而延伸部292的作用在於可增加金屬邊緣部29在雷射燒灼時之散熱面積。 Furthermore, please refer to FIG. 2B' which is a top view of FIG. 2B, wherein the planar projection shape of the metal edge portion 29 can have a notch 291 like the package structure 2a, and the metal edge portion 29 can have the same as the package structure 2b. The extension portion 292 extends toward the plane projection direction of the electronic component 21, and the extension portion 292 functions to increase the heat dissipation area of the metal edge portion 29 during laser cauterization.
此外，在另一實施例中，金屬邊緣部29之外側與封裝膠體2之側表面20c間的間距P’小於50微米，而更特定而言，間距P’介於0.5微米與50微米之間，即間距P2之寬度為間距P1之寬度與間距P’之二倍寬度的和。在間距P’介於0.5微米與50微米之間的情況下，相鄰金屬邊緣部29之間可具有介電層232。 Further, in another embodiment, the pitch P' between the outer side of the metal edge portion 29 and the side surface 20c of the encapsulant 2 is less than 50 micrometers, and more specifically, the pitch P' is between 0.5 micrometers and 50 micrometers. That is, the width of the pitch P 2 is the sum of the width of the pitch P 1 and the width of the pitch P′. Where the pitch P' is between 0.5 microns and 50 microns, a dielectric layer 232 may be present between adjacent metal edge portions 29.
接著，移除承載板27。 Next, the carrier board 27 is removed.
最後，如第2C圖所示，以雷射3沿任二相鄰之金屬邊緣部29間之路徑燒灼，以對整版面之封裝結構2’進行切單而構成複數封裝結構2。詳而言之，其係以雷射3燒灼相鄰金屬邊緣部29之間的間距P2內的介電層232、封裝膠體20或其二者，此時，由於各封裝結構2之外緣具有金屬邊緣部29，故可改善雷射3燒灼對各封裝結構2所造成之熱損傷問題。 Finally, as shown in FIG. 2C, the laser 3 is cauterized along the path between any two adjacent metal edge portions 29 to form a plurality of package structures 2 by singulating the package structure 2' of the entire layout. In detail, it is used to burn the dielectric layer 232, the encapsulant 20 or both in the distance P 2 between the adjacent metal edge portions 29 by the laser 3, at this time, due to the outer edge of each package structure 2 The metal edge portion 29 has the problem of thermal damage caused by the laser burning of the laser 3 to each package structure 2.
而如第2C圖所示之本發明的封裝結構2係包括：電子元件21、封裝膠體20、介電層232、導電開口231、線 路層233及金屬邊緣部29。 The package structure 2 of the present invention as shown in FIG. 2C includes: an electronic component 21, an encapsulant 20, a dielectric layer 232, a conductive opening 231, and a line. The road layer 233 and the metal edge portion 29.
如上所述之電子元件21具有相對之非作用面21b及作用面21a，作用面21a具有電極墊211，而電子元件21係嵌埋於封裝膠體20中且電子元件21之作用面21a可由封裝膠體20之第一表面20a所外露出並由第二表面20b覆蓋，或者，電子元件21之非作用面21b亦可由第二表面20b外露出。 The electronic component 21 as described above has a non-active surface 21b and an active surface 21a. The active surface 21a has an electrode pad 211, and the electronic component 21 is embedded in the encapsulant 20 and the active surface 21a of the electronic component 21 can be encapsulated. The first surface 20a of the 20 is exposed and covered by the second surface 20b, or the non-active surface 21b of the electronic component 21 may be exposed from the second surface 20b.
如上所述之介電層232係形成在封裝膠體20及作用面21a上，而導電開口231係形成在介電層232中且電性連接該些電極墊211，線路層233係形成在介電層232上並電性連接導電開口231。 The dielectric layer 232 is formed on the encapsulant 20 and the active surface 21a, and the conductive opening 231 is formed in the dielectric layer 232 and electrically connected to the electrode pads 211. The circuit layer 233 is formed on the dielectric layer. The conductive opening 231 is electrically connected to the layer 232.
如上所述之金屬邊緣部29係形成在封裝膠體20上，各該金屬邊緣部29所圍繞之範圍係定義出一封裝結構2，且金屬邊緣部29之平面投影圍繞電子元件21之平面投影，另金屬邊緣部29係電性獨立於線路層233及電子元件21。詳而言之但不限於此，形成金屬邊緣部29之材料係例如為熱傳導係數大於204W/(m*K)的金屬、金屬合金或金屬混合物，而更特定而言，金屬邊緣部29之材料為銅、鋁、金、銀、鈦等等或其組合，而金屬邊緣部29係形成於第一表面20a上且金屬邊緣部29之平面投影形狀可為具有封閉路徑的形狀，而特定而言，係矩形或方形(即長方形或正方形)，另金屬邊緣部29之外側與封裝膠體20之側表面間的間距P’可小於50微米，而更特定而言，間距P’介於0.5微米與50微米之間。在間距P’介於0.5微米與50微米之 間的情況下，相鄰金屬邊緣部29之間可形成有介電層232，並且只要是金屬邊緣部29之厚度D1與封裝結構2之厚度D2的比例介於0.1與1之間，金屬邊緣部29的厚度可大於或等於導電開口231的厚度、可等於導電開口231與線路層233的厚度和、可嵌設於介電層232中或者使金屬邊緣部29突出於線路層233。 The metal edge portion 29 is formed on the encapsulant 20 as described above, and the range surrounded by the metal edge portion 29 defines a package structure 2, and the planar projection of the metal edge portion 29 projects around the plane of the electronic component 21. The metal edge portion 29 is electrically independent of the wiring layer 233 and the electronic component 21. More specifically, but not limited thereto, the material forming the metal edge portion 29 is, for example, a metal, a metal alloy or a metal mixture having a thermal conductivity of more than 204 W/(m*K), and more specifically, a material of the metal edge portion 29. It is copper, aluminum, gold, silver, titanium, or the like, or a combination thereof, and the metal edge portion 29 is formed on the first surface 20a and the planar projection shape of the metal edge portion 29 may be a shape having a closed path, and specifically , rectangular or square (ie, rectangular or square), the distance P' between the outer side of the metal edge portion 29 and the side surface of the encapsulant 20 may be less than 50 micrometers, and more specifically, the pitch P' is between 0.5 micrometers and Between 50 microns. The pitch P 'is interposed between the case of 0.5 microns and 50 microns, may be formed adjacent to the dielectric layer 232 between the edge portion 29 of metal and a metal as long as the thickness D 29 of the edge portions 1 and 2 of the thickness of the package The ratio of D 2 is between 0.1 and 1, and the thickness of the metal edge portion 29 may be greater than or equal to the thickness of the conductive opening 231, may be equal to the thickness of the conductive opening 231 and the wiring layer 233, and may be embedded in the dielectric layer 232. Alternatively, the metal edge portion 29 is protruded from the wiring layer 233.
此外，本發明之封裝結構2的金屬邊緣部29復具有如第2B’圖中所示缺口291及往電子元件21之平面投影方向延伸的延伸部292。 Further, the metal edge portion 29 of the package structure 2 of the present invention has a notch 291 as shown in Fig. 2B' and an extension portion 292 extending in the plane projection direction of the electronic component 21.
請參照第2C’圖，係第2C圖之另一態樣，第2C’圖與第2C圖的差異係在於介電層232復形成有介電層凹部2321且線路層233係嵌設於介電層凹部2321中，以及在間距P’介於0.5微米與50微米之間的情況下，相鄰金屬邊緣部29之間可具有介電層232’(即介電層232復可形成於各相鄰金屬邊緣部29之間，並於雷射3燒灼後，於封裝結構2邊緣留存一層寬度介於0.5微米與50微米之間的介電層232’)。 Referring to FIG. 2C', another aspect of FIG. 2C, the difference between the 2C' and 2C is that the dielectric layer 232 is formed with the dielectric layer recess 2321 and the circuit layer 233 is embedded in the dielectric layer 232. In the electrical layer recess 2321, and in the case where the pitch P' is between 0.5 micrometers and 50 micrometers, the adjacent metal edge portions 29 may have a dielectric layer 232' (ie, the dielectric layer 232 may be formed in each Between adjacent metal edge portions 29, and after laser 3 is cauterized, a dielectric layer 232') having a width between 0.5 microns and 50 microns is left at the edge of the package structure 2.
而在如第2C’圖之線路層233嵌設於介電層凹部2321的情況下，本發明之金屬邊緣部29可嵌設於介電層232中，以使金屬邊緣部29被介電層232覆蓋(未圖示此情況)。 In the case where the wiring layer 233 as shown in FIG. 2C is embedded in the dielectric layer recess 2321, the metal edge portion 29 of the present invention may be embedded in the dielectric layer 232 such that the metal edge portion 29 is dielectric layer. 232 coverage (this is not shown).
請參照第3A至3D圖，係本發明之封裝結構的製法之另一態樣的剖視圖，第3D’圖係第3D圖之另一態樣。 3A to 3D are cross-sectional views showing another aspect of the method of fabricating the package structure of the present invention, and the 3D' is another aspect of the 3D diagram.
在第3A圖中，其與第2A圖之差異係在於所提供之承載板27上的封裝膠體20之第一表面20a形成有凹槽201， 而形成凹槽201之方法可為在封裝膠體20中形成凹部(未標示)之後於該凹部中形成第一阻層4以將該凹部隔成具有寬度為間距P2的凹槽201，如第3A圖所示；或者，直接在封裝膠體20中形成對應欲形成金屬邊緣部29的凹槽201(未圖示此情況)。 In FIG. 3A, the difference from FIG. 2A is that the first surface 20a of the encapsulant 20 on the carrier board 27 is provided with a recess 201, and the method of forming the recess 201 can be in the encapsulant 20. Forming a recess (not labeled) to form a first resist layer 4 in the recess to partition the recess into a recess 201 having a pitch P 2 as shown in FIG. 3A; or directly in the encapsulant 20 A groove 201 corresponding to the metal edge portion 29 is formed (this case is not shown).
在第3B圖中，形成導電開口231、介電層232、線路層233及部分金屬邊緣部29。 In FIG. 3B, a conductive opening 231, a dielectric layer 232, a wiring layer 233, and a portion of the metal edge portion 29 are formed.
在第3C圖中，在介電層232、線路層233及第一阻層4上形成第二阻層5，並在金屬邊緣部29上對應形成例如其材料為熱傳導係數大於204W/(m*K)的金屬、金屬合金或金屬混合物的金屬材料層(未標示)，而更特定而言，金屬材料層之材料為銅、鋁、金、銀、鈦等等或其組合，以增厚金屬邊緣部29。然而值得注意的是，只要金屬邊緣部29之厚度D1與封裝結構2之厚度D2的比例介於0.1與1之間，可使金屬邊緣部29之頂面突出或齊平於線路層233，且金屬邊緣部29之外側與封裝膠體20之側表面20c間可具有小於50微米之間距P’的寬度，而更特定而言，間距P’介於0.5微米與50微米之間；即在間距P’介於0.5微米與50微米之間的情況下，間距P2之寬度為間距P1之寬度與間距P’之二倍寬度的和，且在間距P’為0微米的情況下，金屬邊緣部29之外側與封裝膠體20之側表面20c間亦可不具有間距P’的寬度(未圖示此情況)。 In FIG. 3C, a second resist layer 5 is formed on the dielectric layer 232, the wiring layer 233, and the first resist layer 4, and correspondingly formed on the metal edge portion 29, for example, the material has a heat transfer coefficient greater than 204 W/(m*). K) a layer of metal material of a metal, metal alloy or metal mixture (not labeled), and more particularly, the material of the metal material layer is copper, aluminum, gold, silver, titanium, etc. or a combination thereof to thicken the metal Edge portion 29. However, it should be noted that, as long as the ratio of the thickness of the metal edge portions 29 of the thickness D 1 and D 2 of the package 2 is between 0.1 and 1, allows the metal edges of the top surface 29 of the protruding flush with the wiring layer 233 And the outer side of the metal edge portion 29 and the side surface 20c of the encapsulant 20 may have a width of less than 50 micrometers between P', and more specifically, the pitch P' is between 0.5 micrometers and 50 micrometers; In the case where the pitch P' is between 0.5 micrometers and 50 micrometers, the width of the pitch P 2 is the sum of the width of the pitch P 1 and the width of the pitch P′, and in the case where the pitch P′ is 0 μm, The outer side of the metal edge portion 29 and the side surface 20c of the encapsulant 20 may not have a width P' (this is not shown).
在第3D圖中，於去除第一阻層4與第二阻層5並移除承載板27後可進行雷射切單製程，以形成複數封裝結構 2，而其與第2A圖之差異僅在於金屬邊緣部29係形成在封裝膠體20之第一表面20a所形成之凹槽201中，並且雷射3係燒灼相鄰金屬邊緣部29之間的間距P1中之封裝膠體20。 In the 3D figure, after the first resistive layer 4 and the second resistive layer 5 are removed and the carrier plate 27 is removed, a laser singulation process can be performed to form the plurality of package structures 2, and the difference from the 2A map is only wherein the metal-based edge portion 29 is formed in a recess 201 of the first surface 20a of the encapsulant 20 is formed of, and laser ablation system 3 spacing between adjacent metal edges 29 of portion P 1 in the encapsulant 20.
請參照第3D’圖，係第3D圖之另一態樣，第3D’圖與第3D圖的差異係在於介電層232復形成有介電層凹部2321且線路層233係嵌設於介電層凹部2321中。而在此態樣中，本發明之介電層232可覆蓋金屬邊緣部29(未圖示此情況)。另外請參照第3D”圖，係第3D圖之另一態樣，第3D”圖與第3D圖的差異係在於第3D”圖之金屬邊緣部29係齊平於封裝膠體20，而介電層232係覆蓋金屬邊緣部29，以使金屬邊緣部29嵌設於封裝膠體20中。 Please refer to FIG. 3D′, which is another aspect of FIG. 3D. The difference between the 3D′ and 3D is that the dielectric layer 232 is formed with the dielectric layer recess 2321 and the circuit layer 233 is embedded in the dielectric layer 232. In the electrical layer recess 2321. In this aspect, the dielectric layer 232 of the present invention can cover the metal edge portion 29 (not shown). Please refer to the 3D" figure, which is another aspect of the 3D figure. The difference between the 3D" and the 3D is that the metal edge portion 29 of the 3D" is flush with the encapsulant 20, and the dielectric is dielectric. The layer 232 covers the metal edge portion 29 such that the metal edge portion 29 is embedded in the encapsulant 20.
請參照第4A至4C圖，其係本發明之封裝結構的製法之另一態樣的剖視圖。 Please refer to FIGS. 4A to 4C, which are cross-sectional views showing another aspect of the manufacturing method of the package structure of the present invention.
如第4A圖所示，本態樣之封裝結構2的製法係首先提供其上形成有封裝膠體20、分離排列之複數電子元件21、介電層232、複數導電開口231及線路層233的承載板27，且封裝膠體20之第二表面20b形成有凹槽201。詳而言之，線路層233及介電層232形成於承載板27之一表面，導電開口231形成於介電層232中以電性連接線路層233，而電子元件21具有相對之非作用面21b及作用面21a，作用面21a具有電極墊211且接置於介電層232上，電極墊211電性連接導電開口231，另封裝膠體20形成於介電層232上且包覆電子元件21，而封裝膠體20具有露 出作用面21a的第一表面20a及與其相對之第二表面20b，凹槽201之深度可小於或等於封裝膠體20之厚度。 As shown in FIG. 4A, the manufacturing method of the package structure 2 of the present aspect first provides a carrier board on which the encapsulant 20, the plurality of discrete electronic components 21, the dielectric layer 232, the plurality of conductive openings 231, and the wiring layer 233 are formed. 27, and the second surface 20b of the encapsulant 20 is formed with a groove 201. In detail, the circuit layer 233 and the dielectric layer 232 are formed on one surface of the carrier board 27, the conductive opening 231 is formed in the dielectric layer 232 to electrically connect the circuit layer 233, and the electronic component 21 has a relative non-active surface. 21b and the active surface 21a, the active surface 21a has an electrode pad 211 and is connected to the dielectric layer 232. The electrode pad 211 is electrically connected to the conductive opening 231. The other encapsulant 20 is formed on the dielectric layer 232 and covers the electronic component 21. And the encapsulant 20 has a dew The depth of the groove 201 may be less than or equal to the thickness of the encapsulant 20, the first surface 20a of the active surface 21a and the second surface 20b opposite thereto.
而第4A圖可具有另一態樣(未圖示)，其與第4A圖之差異係在於介電層232復形成有如第2C’圖之介電層凹部2321且線路層233係嵌設於介電層凹部2321中。 4A may have another aspect (not shown), which differs from FIG. 4A in that dielectric layer 232 is formed with dielectric layer recess 2321 as shown in FIG. 2C' and circuit layer 233 is embedded in In the dielectric layer recess 2321.
接著，如第4B圖所示，在封裝膠體20之第二表面20a所形成之凹槽201中形成複數金屬邊緣部29，且金屬邊緣部29係電性獨立於線路層233及電子元件21，而形成金屬邊緣部29之材料係為熱傳導係數大於204W/(m*K)的金屬、金屬合金或金屬混合物，而更特定而言，金屬邊緣部29之材料為銅、鋁、金、銀、鈦等等或其組合，且金屬邊緣部29之平面投影形狀係為圍繞電子元件21之平面投影的具有封閉路徑的形狀，而特定而言，係矩形或方形(即長方形或正方形)，或者金屬邊緣部29之平面投影形狀可具有如第2B’圖中的缺口291及具有往電子元件21之平面投影方向延伸的延伸部(未圖示此情況)，各金屬邊緣部29所圍繞之範圍係用以定義出一封裝結構2。而值得注意的是，金屬邊緣部29之厚度D1與封裝結構2的厚度D2的比例介於0.1與1之間，而相鄰金屬邊緣部29之間可具有封裝膠體20。 Next, as shown in FIG. 4B, a plurality of metal edge portions 29 are formed in the recess 201 formed by the second surface 20a of the encapsulant 20, and the metal edge portion 29 is electrically independent of the wiring layer 233 and the electronic component 21. The material forming the metal edge portion 29 is a metal, metal alloy or metal mixture having a thermal conductivity greater than 204 W/(m*K), and more specifically, the material of the metal edge portion 29 is copper, aluminum, gold, silver, Titanium or the like or a combination thereof, and the planar projection shape of the metal edge portion 29 is a shape having a closed path projected around the plane of the electronic component 21, and specifically, a rectangle or a square (ie, a rectangle or a square), or a metal The planar projection shape of the edge portion 29 may have a notch 291 as shown in FIG. 2B' and an extension portion (not shown) extending in a plane projection direction of the electronic component 21, and the range surrounded by each metal edge portion 29 is Used to define a package structure 2. It is worth noting that the thickness ratio of the metal edge portions 29 of the thickness D 1 and D 2 of the package 2 is between 0.1 and 1, while the adjacent edges of the metal portion 20 may have between 29 and encapsulant.
接著，如第4C圖所示，移除承載板27並進行雷射切單製程，以形成封裝結構2，且金屬邊緣部29之外側與封裝膠體20之側表面20c間可具有小於50微米之間距P’的寬度，而更特定而言，間距P’介於0.5微米與50微米之間； 即在間距P’介於0.5微米與50微米之間的情況下，間距P2之寬度為間距P1之寬度與間距P’之二倍寬度的和，或者，在間距P’為0微米的情況下，金屬邊緣部29之外側與封裝膠體20之側表面20c間不具有間距P’的寬度(未圖示此情況)。 Next, as shown in FIG. 4C, the carrier board 27 is removed and subjected to a laser singulation process to form the package structure 2, and the outer side of the metal edge portion 29 and the side surface 20c of the encapsulant 20 may have less than 50 micrometers. the pitch P 'width, but more particularly, the pitch P' is between 0.5 and 50 microns; i.e., the pitch P 'is interposed between the case of 0.5 microns and 50 microns, the pitch width P 2 of the pitch The sum of the width of P 1 and the width of the pitch P′, or, in the case where the pitch P′ is 0 μm, the width of the outer side of the metal edge portion 29 and the side surface 20 c of the encapsulant 20 does not have a pitch P′. (This is not shown).
此外，如第4A至4C圖之態樣可具有另一種實施例，其與第4A至4C圖之態樣的差異係在於重佈線層23係嵌埋且外露於封裝膠體20(未圖示此情況)。 In addition, the embodiment of FIGS. 4A to 4C may have another embodiment, and the difference from the aspect of FIGS. 4A to 4C is that the redistribution layer 23 is embedded and exposed to the encapsulant 20 (not shown). Happening).
請參照第4B’及4C’圖，其係與第4B及4C圖相關之本發明之封裝結構的製法之另一態樣的剖視圖。第4B’圖與第4B圖相異之處係在於封裝膠體20中並未形成有凹槽201，故複數金屬邊緣部29係直接形成在封裝膠體20之第二表面20b上。之後如第4C’圖所示，移除承載板27並進行雷射切單製程，以形成複數封裝結構2。 Referring to Figures 4B' and 4C', which are cross-sectional views of another aspect of the method of fabricating the package of the present invention associated with Figures 4B and 4C. The difference between the 4B' and 4B is that the recess 201 is not formed in the encapsulant 20, so that the plurality of metal edge portions 29 are directly formed on the second surface 20b of the encapsulant 20. Thereafter, as shown in Fig. 4C', the carrier plate 27 is removed and subjected to a laser singulation process to form a plurality of package structures 2.
請參照第5A至5C及5B’圖，第5A至5C圖係本發明之封裝結構的製法之另一態樣的剖視圖，而第5B’圖係第5B圖的俯視圖，而為了方便說明，第5B圖僅顯示第5B’圖之一部分。 5A to 5C and 5B', FIGS. 5A to 5C are cross-sectional views showing another aspect of the manufacturing method of the package structure of the present invention, and FIG. 5B' is a plan view of FIG. 5B, and for convenience of explanation, Figure 5B shows only part of the 5B' diagram.
如第5A圖所示，首先提供其上形成有封裝膠體20的承載板27，封裝膠體20具有連接承載板27之第二表面20b及與其相對之第一表面20a，第一表面20a嵌埋且外露出複數電子元件51，其具有相對之非作用面51b及作用面51a，其中，作用面51a具有複數電極墊511且外露出第一表面20a，而非作用面51b連接承載板27，且複數電子元 件51排列於承載板27上。 As shown in FIG. 5A, a carrier board 27 having an encapsulant 20 formed thereon is provided. The encapsulant 20 has a second surface 20b connecting the carrier board 27 and a first surface 20a opposite thereto. The first surface 20a is embedded and The plurality of electronic components 51 are exposed, and have a non-active surface 51b and an active surface 51a. The active surface 51a has a plurality of electrode pads 511 and exposes the first surface 20a, and the non-active surface 51b is connected to the carrier 27, and Electronic element The member 51 is arranged on the carrier plate 27.
詳而言之但不限於此，如上所述之承載板27可為晶圓、塑膠板、玻璃纖維板、金屬板、陶瓷板或其組合，並且，複數電子元件51可為晶片或連接於晶圓上之晶粒，且電子元件51係分離排列地嵌埋於封裝膠體20中。 In detail, but not limited to, the carrier board 27 as described above may be a wafer, a plastic board, a fiberglass board, a metal board, a ceramic board or a combination thereof, and the plurality of electronic components 51 may be a wafer or a wafer. The upper die and the electronic component 51 are embedded in the encapsulant 20 in a separate arrangement.
接著如第5B圖所示，可以多種製程策略形成如第2B、2C’及3C圖中的導電開口231、複數金屬邊緣部29、介電層232及線路層233，而於承載板27上構成一整版面之封裝結構2’，且在承載板27為晶圓及電子元件51為晶粒的情況下，線路層233上可形成例如為凸塊的導電元件(未圖示)。 Then, as shown in FIG. 5B, the conductive opening 231, the plurality of metal edge portions 29, the dielectric layer 232, and the wiring layer 233 in FIGS. 2B, 2C', and 3C can be formed by various process strategies, and are formed on the carrier board 27. A full-package package structure 2', and in the case where the carrier plate 27 is a wafer and the electronic component 51 is a die, a conductive element (not shown) such as a bump may be formed on the circuit layer 233.
特定而言，整版面之封裝結構2’可由以陣列方式排列之複數封裝結構2所組成，或者，在承載板27為晶圓及電子元件51為晶粒的情況下，整版面之封裝結構2’可由以如第5B’所示之晶圓形式排列之複數封裝結構2所組成，且金屬邊緣部29之平面投影形狀可具有如封裝結構2a的缺口291，另外，金屬邊緣部29可如封裝結構2b般具有往電子元件21之平面投影方向延伸的延伸部292。 In particular, the package structure 2' of the full-page surface may be composed of a plurality of package structures 2 arranged in an array, or in the case where the carrier plate 27 is a wafer and the electronic component 51 is a die, the package structure of the full-page surface 2 'A plurality of package structures 2 arranged in the form of a wafer as shown in FIG. 5B', and the planar projection shape of the metal edge portion 29 may have a notch 291 such as the package structure 2a, and in addition, the metal edge portion 29 may be as packaged The structure 2b has an extension 292 extending toward the plane projection direction of the electronic component 21.
最後，如第5C圖所示，移除承載板27並以雷射3沿任二相鄰之金屬邊緣部29間之路徑燒灼，以對整版面之封裝結構2’進行切單而構成複數封裝結構2，而以雷射3對整版面之封裝結構2’進行切單之詳細內容已在上文說明，故不再贅述。 Finally, as shown in FIG. 5C, the carrier plate 27 is removed and the laser 3 is cauterized along the path between any two adjacent metal edge portions 29 to singulate the package structure 2' of the entire layout to form a plurality of packages. Structure 2, and the details of aligning the package structure 2' of the entire layout with the laser 3 have been described above, and therefore will not be described again.
另外，本發明之封裝結構亦可組合如第2A至2C圖、 第3A至3D圖、第4A至4C圖及第5A至5C圖之各種組件及製程步驟以形成如第6圖所示之另一態樣的封裝結構，其係使封裝膠體20於連接金屬邊緣部29之側之相對側復連接有電性獨立於線路層233與電子元件21的附加金屬邊緣部29a，舉例而言，於金屬邊緣部29連接於封裝膠體20之第一表面20a側時，附加金屬邊緣部29a係連接於封裝膠體20之第二表面20b側，而於金屬邊緣部29連接於封裝膠體20之第二表面20b側時，附加金屬邊緣部29a係連接於封裝膠體20之第一表面20a側(未圖示此情況)，其中，附加金屬邊緣部29a之厚度與封裝結構2之厚度D2的比例、形狀、材料及各附加金屬邊緣部29a之間的間距等特性可類似於金屬邊緣部29。 In addition, the package structure of the present invention may also combine various components and process steps as shown in FIGS. 2A to 2C, 3A to 3D, 4A to 4C, and 5A to 5C to form another as shown in FIG. An aspect of the package structure is such that the opposite side of the side of the encapsulating colloid 20 on the side of the connecting metal edge portion 29 is electrically connected independently of the additional metal edge portion 29a of the circuit layer 233 and the electronic component 21, for example, When the metal edge portion 29 is connected to the first surface 20a side of the encapsulant 20, the additional metal edge portion 29a is connected to the second surface 20b side of the encapsulant 20, and the metal edge portion 29 is connected to the second surface of the encapsulant 20. On the side of the 20b side, the additional metal edge portion 29a is connected to the first surface 20a side of the encapsulant 20 (this is not shown), wherein the ratio of the thickness of the additional metal edge portion 29a to the thickness D 2 of the package structure 2 The characteristics such as the spacing between the material and each of the additional metal edge portions 29a may be similar to the metal edge portion 29.
請參照第7A至7B及7A’圖，第7A至7B圖係本發明之封裝結構的製法之另一態樣的剖視圖，而第7A’圖則係與第7A圖相關之另一製法態樣。 Please refer to FIGS. 7A to 7B and 7A'. FIGS. 7A to 7B are cross-sectional views showing another aspect of the manufacturing method of the package structure of the present invention, and FIG. 7A' is another manufacturing method related to FIG. 7A. .
如第7A圖所示，首先提供其上連接有複數電子元件21及金屬邊緣部29的基板本體76，而基板本體76包括絕緣層762及其上的線路層761，且電子元件21具有相對之非作用面21b及作用面21a，作用面21a具有電性連接線路層761的複數電極墊211，另電子元件21係對基板本體76為分離排列，再者，基板本體76上可形成有封裝膠體20，其包覆電子元件21並連接有金屬邊緣部29，且封裝膠體20具有外露出電子元件21的第一表面20a及與其相對之第二表面20b，其中，金屬邊緣部29所圍繞之範圍係用以 定義出一封裝結構2，另金屬邊緣29部係電性獨立於線路層761及電子元件21。 As shown in FIG. 7A, a substrate body 76 having a plurality of electronic components 21 and a metal edge portion 29 connected thereto is first provided, and the substrate body 76 includes an insulating layer 762 and a wiring layer 761 thereon, and the electronic component 21 has a relative The non-acting surface 21b and the active surface 21a, the active surface 21a has a plurality of electrode pads 211 electrically connected to the wiring layer 761, and the other electronic components 21 are arranged separately from the substrate body 76. Further, the substrate body 76 may be formed with an encapsulant. 20, which covers the electronic component 21 and is connected with the metal edge portion 29, and the encapsulant 20 has a first surface 20a exposing the electronic component 21 and a second surface 20b opposite thereto, wherein the range surrounded by the metal edge portion 29 Used A package structure 2 is defined, and the metal edge 29 is electrically independent of the circuit layer 761 and the electronic component 21.
詳而言之但不限於此，如上所述之基板本體76可為應用於封裝結構之所有類型的封裝基板，而封裝基板的類型已為所屬技術領域中具有通常知識者所知曉，在此不再贅述，而於第7A圖之態樣中，基板本體66包括絕緣層762及其上的線路層761，絕緣層762可為具有絕緣特性的材料，更特定而言可為介電材料。而電子元件21可為各種習知之半導體元件的形式，而半導體元件可例如為晶粒、晶片或已封裝之半導體元件(如晶片接置於矽中介層)等等，而晶粒及晶片可為單一或多層層疊的形式，亦可為單一或多層層疊之晶粒及晶片接置於例如為中介板上的形式，且電子元件21具有相對之非作用面21b及作用面21a，並且電子元件21可於其作用面21a具有複數電極墊211，以藉由銲線78電性連接線路層761，然而，本發明亦可使用覆晶接合(flipchip bonding)方式使電極墊211電性連接線路層761，而覆晶接合方式已為所屬技術領域中具有通常知識者所知曉，在此不再贅述。另外，電子元件21對基板本體76而言為分離排列以組成整版面之封裝結構2’，特定而言，整版面之封裝結構2’可以陣列方式排列，更特定而言，其可為板材(Substrate Panel)結構或晶圓形式之排列結構。 In detail, but not limited thereto, the substrate body 76 as described above may be all types of package substrates applied to the package structure, and the type of the package substrate is known to those of ordinary skill in the art, and is not here. Further, in the aspect of FIG. 7A, the substrate body 66 includes an insulating layer 762 and a wiring layer 761 thereon, and the insulating layer 762 may be a material having insulating properties, more specifically, a dielectric material. The electronic component 21 can be in the form of various conventional semiconductor components, and the semiconductor component can be, for example, a die, a wafer, or a packaged semiconductor component (eg, a wafer is placed on the germanium interposer), and the die and the wafer can be In a single or multi-layered form, the single or multi-layer laminated die and the wafer are placed in a form such as an interposer, and the electronic component 21 has a relatively non-active surface 21b and an active surface 21a, and the electronic component 21 The active surface 21a has a plurality of electrode pads 211 for electrically connecting the circuit layer 761 by the bonding wires 78. However, the present invention can also electrically connect the electrode pads 211 to the wiring layer 761 by using a flip chip bonding method. The flip chip bonding method is known to those of ordinary skill in the art and will not be described herein. In addition, the electronic component 21 is a package structure 2 ′ that is separately arranged to form a full-face surface for the substrate body 76 . In particular, the package structure 2 ′ of the full-page layout may be arranged in an array manner, and more specifically, may be a plate material ( Substrate Panel) An arrangement of structures or wafers.
進一步詳而言之但不限於此，封裝膠體20包覆電子元件21並連接有金屬邊緣部29，特定而言，封裝膠體20具有第一表面20a及與其相對之第二表面20b，且封裝膠體 20之第一表面20a接觸基板本體76，並外露出嵌埋於封裝膠體20中之電子元件21的非作用面21b，而電子元件21之非作用面21b可接置於位在基板本體76上的置晶墊(未圖示)，在此情況下，封裝膠體20之第一表面20a外露出置晶墊。然而，須注意的是在覆晶接合的情況下，第一表面20a外露出作用面21a且第二表面20b外露出非作用面21b。另外，金屬邊緣部29可依實際需求而採取適當製程策略來形成於各種位置，舉例而言，該等位置可為嵌埋於基板本體76中並齊平於基板本體76之表面以連接封裝膠體20、嵌埋於基板本體76中並延伸至封裝膠體20中、嵌埋於封裝膠體20中並由第一表面20a露出、嵌埋於封裝膠體20內、嵌埋於封裝膠體20中並齊平第二表面20b、嵌埋於封裝膠體20中並突出於第二表面20b或如以上之組合，例如，如第7A’圖之非限制性範例所示地使封裝膠體20於連接金屬邊緣部29之側之相對側復連接有電性獨立於線路層761及電子元件21的附加金屬邊緣部29a，如第7A’圖所示，封裝膠體20之第一表面20a側連接有金屬邊緣部29，故封裝膠體20之第二表面20b側連接有附加金屬邊緣部29a，或者，若封裝膠體20之第二表面20b側連接有金屬邊緣部29，則封裝膠體20之第一表面20a側連接有附加金屬邊緣部29a(未圖示此情況)，又或是可在封裝膠體20內或基板本體76中形成類似於金屬邊緣部29的其它金屬邊緣部(未圖示)。 More specifically, but not limited to, the encapsulant 20 encloses the electronic component 21 and is connected with a metal edge portion 29. Specifically, the encapsulant 20 has a first surface 20a and a second surface 20b opposite thereto, and the encapsulant is encapsulated. The first surface 20a of the second surface 20a contacts the substrate body 76 and exposes the inactive surface 21b of the electronic component 21 embedded in the encapsulant 20, and the non-active surface 21b of the electronic component 21 can be placed on the substrate body 76. A pad (not shown), in which case the first surface 20a of the encapsulant 20 is exposed to the outside of the pad. However, it should be noted that in the case of flip chip bonding, the first surface 20a exposes the active surface 21a and the second surface 20b exposes the non-active surface 21b. In addition, the metal edge portion 29 can be formed in various positions according to actual needs, for example, the position can be embedded in the substrate body 76 and flush with the surface of the substrate body 76 to connect the encapsulant. 20, embedded in the substrate body 76 and extending into the encapsulant 20, embedded in the encapsulant 20 and exposed by the first surface 20a, embedded in the encapsulant 20, embedded in the encapsulant 20 and flush The second surface 20b, embedded in the encapsulant 20 and protruding from the second surface 20b or a combination thereof, for example, causes the encapsulant 20 to be joined to the metal edge portion 29 as shown in the non-limiting example of FIG. 7A'. The opposite side of the side is electrically connected to the additional metal edge portion 29a of the circuit layer 761 and the electronic component 21. As shown in FIG. 7A', the metal edge portion 29 is connected to the first surface 20a side of the encapsulant 20. Therefore, the second surface 20b side of the encapsulant 20 is connected with an additional metal edge portion 29a, or if the metal edge portion 29 is connected to the second surface 20b side of the encapsulant 20, the first surface 20a side of the encapsulant 20 is attached with an additional Metal edge portion 29a ( This case is not shown, or another metal edge portion (not shown) similar to the metal edge portion 29 may be formed in the encapsulant 20 or in the substrate body 76.
然而值得注意的是，各金屬邊緣部29之平面投影形狀 可為具有封閉路徑的形狀，或者金屬邊緣部29之平面投影形狀可具有如第2B’或5B’圖中的缺口291。另外，金屬邊緣部29可如第2B’或5B’圖所示地具有往電子元件21之平面投影方向延伸的延伸部292。 However, it is worth noting that the planar projection shape of each metal edge portion 29 The shape may have a closed path, or the planar projection shape of the metal edge portion 29 may have a notch 291 as in the 2B' or 5B' diagram. Further, the metal edge portion 29 may have an extending portion 292 extending toward the plane projection direction of the electronic component 21 as shown in the second B' or 5B'.
另外，金屬邊緣部29之厚度D1與封裝結構2之厚度D2的比例、金屬邊緣部29之材料及各金屬邊緣部29之間的間距P2等特性已於上述各態樣中詳述，在此不再贅述。 Further, the thickness ratio of the metal edge portions 29 of the D 1 and D 2 of the thickness of the package 2, the spacing 29 between the edge portion 29 of the metal material and each metal edge portion P 2 has characteristics such as detailed in the above aspects , will not repeat them here.
最後，如第7B圖所示，以雷射3沿任二相鄰之金屬邊緣部29間的路徑燒灼，以對整版面之封裝結構2’進行切單而構成如第7B圖所示的複數封裝結構2，而以雷射3對整版面之封裝結構2’進行切單之詳細內容已在上文說明，故不再贅述。 Finally, as shown in FIG. 7B, the laser 3 is cauterized along a path between any two adjacent metal edge portions 29 to singulate the package structure 2' of the entire layout to form a complex number as shown in FIG. 7B. The details of the package structure 2 and the singulation of the package structure 2' of the full-face by the laser 3 have been described above, and therefore will not be described again.
綜上所述，相較於先前技術，由於本發明係藉由圍繞電子元件之各周圍金屬邊緣部而避免習知技術之在雷射燒灼相鄰各周圍金屬邊緣部之間的介電材料、封裝膠體或其二者時所造成的介電層與線路層剝離、線路層損傷或封裝結構外觀燒蝕等等的諸多熱損傷問題，從而在應用雷射切單整版面之封裝結構時，大為提高封裝結構的生產良率及提升封裝結構的可靠性，並因此可在12吋以上之整版面之封裝結構使用雷射切單製程。 In summary, compared to the prior art, the present invention avoids the dielectric material between the adjacent peripheral metal edge portions of the laser to be ablated by the prior art by surrounding the peripheral metal edge portions of the electronic component. Many thermal damage problems caused by dielectric layer and circuit layer peeling, circuit layer damage or package structure ablation caused by encapsulation of the colloid or both, so that when applying a laser-cut single-panel package structure, In order to improve the production yield of the package structure and improve the reliability of the package structure, it is possible to use a laser singulation process in a package structure of more than 12 整.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as follows. Listed around.
2‧‧‧封裝結構 2‧‧‧Package structure
3‧‧‧雷射 3‧‧‧Laser
20‧‧‧封裝膠體 20‧‧‧Package colloid
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
20c‧‧‧側表面 20c‧‧‧ side surface
21‧‧‧電子元件 21‧‧‧Electronic components
21a‧‧‧作用面 21a‧‧‧Action surface
21b‧‧‧非作用面 21b‧‧‧Non-active surface
211‧‧‧電極墊 211‧‧‧electrode pad
23‧‧‧重佈線層 23‧‧‧Rewiring layer
231‧‧‧導電開口 231‧‧‧Electrical opening
232‧‧‧介電層 232‧‧‧Dielectric layer
233‧‧‧線路層 233‧‧‧Line layer
25‧‧‧銲球 25‧‧‧ solder balls
29‧‧‧金屬邊緣部 29‧‧‧Metal edge
D1、D2‧‧‧厚度 D 1 , D 2 ‧‧‧ thickness
P1、P2、P’‧‧‧間距 P 1 , P 2 , P'‧‧‧ spacing
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| TWI621224B (en) * | 2017-07-14 | 2018-04-11 | 欣興電子股份有限公司 | Package structure and manufacturing method thereof |
| TWI674647B (en) * | 2016-08-29 | 2019-10-11 | 上海兆芯集成電路有限公司 | Chip package array and chip package |
| TWI697081B (en) * | 2019-06-10 | 2020-06-21 | 恆勁科技股份有限公司 | Semiconductor package substrate, and manufacturing method and electronic package thereof |
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| TW543126B (en) * | 2002-06-17 | 2003-07-21 | Taiwan Semiconductor Mfg | Method for wafer level chip scale package |
| TW201001651A (en) * | 2008-06-19 | 2010-01-01 | Fupo Electronics Corp | A dielectric layer having bumps structure and its package body and manufacturing method |
| TW201119002A (en) * | 2009-11-27 | 2011-06-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
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| TW543126B (en) * | 2002-06-17 | 2003-07-21 | Taiwan Semiconductor Mfg | Method for wafer level chip scale package |
| TW201001651A (en) * | 2008-06-19 | 2010-01-01 | Fupo Electronics Corp | A dielectric layer having bumps structure and its package body and manufacturing method |
| TW201119002A (en) * | 2009-11-27 | 2011-06-01 | Advanced Semiconductor Eng | Semiconductor package and manufacturing method thereof |
| TW201310555A (en) * | 2011-08-25 | 2013-03-01 | Chipmos Technologies Inc | Semiconductor package structure and manufacturing method thereof |
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| TW201601272A (en) | 2016-01-01 |
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