TWI508197B - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

Info

Publication number
TWI508197B
TWI508197B TW102141421A TW102141421A TWI508197B TW I508197 B TWI508197 B TW I508197B TW 102141421 A TW102141421 A TW 102141421A TW 102141421 A TW102141421 A TW 102141421A TW I508197 B TWI508197 B TW I508197B
Authority
TW
Taiwan
Prior art keywords
encapsulant
semiconductor package
conductive
package
wafer
Prior art date
Application number
TW102141421A
Other languages
Chinese (zh)
Other versions
TW201519335A (en
Inventor
陳彥亨
詹慕萱
林畯棠
紀傑元
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW102141421A priority Critical patent/TWI508197B/en
Publication of TW201519335A publication Critical patent/TW201519335A/en
Application granted granted Critical
Publication of TWI508197B publication Critical patent/TWI508197B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體封裝件及其製法Semiconductor package and its manufacturing method

本發明提供一種封裝件及其製法，尤指一種半導體封裝件及其製法。The invention provides a package and a manufacturing method thereof, in particular to a semiconductor package and a manufacturing method thereof.

隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，遂發展出許多封裝技術。With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, many packaging technologies have been developed.

請參照第1A圖至第1H圖，係為習知技術中形成半導體封裝件之各步驟製程的剖視圖。Referring to FIGS. 1A to 1H, there are shown cross-sectional views of various steps of forming a semiconductor package in the prior art.

如第1A圖所示，首先提供一其上形成有第一黏著層122a的第一承載板12a，第一承載板12a之材質可為玻璃、金屬及陶瓷等等。As shown in FIG. 1A, a first carrier 12a having a first adhesive layer 122a formed thereon may be provided. The material of the first carrier 12a may be glass, metal, ceramics or the like.

之後，如第1B圖所示地將具有作用面132及形成在作用面132處之銲墊134的晶片13接置於第一黏著層122a上。Thereafter, the wafer 13 having the active surface 132 and the pads 134 formed at the active surface 132 is placed on the first adhesive layer 122a as shown in FIG. 1B.

而後，如第1C圖所示地於第一黏著層122a上形成封裝膠體11以包覆晶片13，並在之後於封裝膠體11上接置第二承載板12b，其中，第二承載板12b係可選擇性地在 其表面上形成有第二黏著層122b，以藉由第二黏著層122b接置封裝膠體11。Then, the encapsulant 11 is formed on the first adhesive layer 122a to cover the wafer 13 as shown in FIG. 1C, and then the second carrier 12b is attached to the encapsulant 11, wherein the second carrier 12b is Optional A second adhesive layer 122b is formed on the surface thereof to connect the encapsulant 11 by the second adhesive layer 122b.

之後，如第1D圖所示地將第一黏著層122a及第一承載板12a從作用面132及封裝膠體11的表面上移除。Thereafter, the first adhesive layer 122a and the first carrier 12a are removed from the surface of the active surface 132 and the encapsulant 11 as shown in FIG. 1D.

接著如第1E圖所示地將線路重佈層15形成在作用面132及封裝膠體11的外露表面上，並使線路重佈層15電性連接晶片13。更具體而言，線路重佈層15係具有介電層150、線路(未標元件符號)、第一電性連接墊152、導電盲孔154及第二電性連接墊156，其中，介電層150係形成在作用面132及封裝膠體11的外露表面上，而介電層150內係在與該外露表面相接的一側形成有電性連接於銲墊134的第一電性連接墊152，此外第一電性連接墊152與封裝膠體11連接側之另一側上係形成有與其電性連接之導電盲孔154，而導電盲孔154與第一電性連接墊152電性連接側的另一側上則形成有第二電性連接墊156。Next, as shown in FIG. 1E, the circuit redistribution layer 15 is formed on the exposed surface of the active surface 132 and the encapsulant 11, and the circuit redistribution layer 15 is electrically connected to the wafer 13. More specifically, the circuit redistribution layer 15 has a dielectric layer 150, a line (unmarked component symbol), a first electrical connection pad 152, a conductive blind via 154, and a second electrical connection pad 156, wherein the dielectric layer The layer 150 is formed on the exposed surface of the active surface 132 and the encapsulant 11 , and the first electrical connection pad electrically connected to the bonding pad 134 is formed on the side of the dielectric layer 150 on the side contacting the exposed surface. 152. Further, on the other side of the connection side of the first electrical connection pad 152 and the encapsulant 11, a conductive via 154 electrically connected thereto is formed, and the conductive via 154 is electrically connected to the first electrical connection pad 152. A second electrical connection pad 156 is formed on the other side of the side.

隨後，如第1F圖所示地將形成於第三承載板12c上的第三黏著層122c接置於線路重佈層15上。Subsequently, the third adhesive layer 122c formed on the third carrier 12c is placed on the line redistribution layer 15 as shown in Fig. 1F.

接著，如第1G圖所示地將第二承載板12b及第二黏著層122b一併移除。Next, the second carrier 12b and the second adhesive layer 122b are collectively removed as shown in FIG. 1G.

最後，如第1H圖所示地在封裝膠體11中以雷射鑽孔的方式形成封裝膠體開孔112，以外露第一電性連接墊152。後續將於該封裝膠體開孔112中形成導電材料，並藉由該導電材料電性連接另一封裝結構，而形成半導體封裝件(省略後續步驟之圖式)。Finally, as shown in FIG. 1H, the encapsulation opening 112 is formed by laser drilling in the encapsulant 11 to expose the first electrical connection pad 152. A conductive material is formed in the encapsulation opening 112, and the other package structure is electrically connected to the semiconductor package to form a semiconductor package (the following steps are omitted).

然而，於第1H圖之步驟中，由於習知技術之雷射能量不易控制或其功率不穩定，故容易使線路重佈層中之第一電性連接墊152因雷射燒蝕而造成斷路等狀況。However, in the step of FIG. 1H, since the laser energy of the prior art is difficult to control or its power is unstable, it is easy to cause the first electrical connection pad 152 in the circuit redistribution layer to be broken due to laser ablation. And so on.

因此，如何克服上述習知以雷射鑽孔方式形成封裝膠體開孔容易造成線路重佈層斷路的缺點，是本領域技術人員的一大課題。Therefore, how to overcome the above-mentioned drawbacks that the formation of the encapsulation opening by the laser drilling method is likely to cause the circuit redistribution layer to be broken is a major problem for those skilled in the art.

有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件的製法，係包括以下步驟：將具有作用面之晶片接置於一其上形成有第一黏著層的第一承載板上，且該作用面係連接該第一黏著層；將擋止結構形成在該第一黏著層未連接該晶片之區域上；於該第一黏著層上形成包覆該晶片與擋止結構的封裝膠體，並於該封裝膠體上接置第二承載板；將該第一黏著層及該第一承載板移除，以外露該作用面與擋止結構；將電性連接該半導體晶片與連接擋止結構的線路重佈層形成於該封裝膠體外露該作用面之表面上；將一第三承載板接置於該線路重佈層上；將該第二承載板移除；形成封裝膠體開孔以外露該擋止結構；以及移除該第三承載板。In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for fabricating a semiconductor package, comprising the steps of: placing a wafer having an active surface on a first carrier plate on which a first adhesive layer is formed, and The active surface is connected to the first adhesive layer; the blocking structure is formed on the region where the first adhesive layer is not connected to the wafer; and the encapsulant covering the wafer and the stopper structure is formed on the first adhesive layer, And attaching a second carrier to the encapsulant; removing the first adhesive layer and the first carrier, exposing the active surface and the blocking structure; electrically connecting the semiconductor wafer and the connecting stop structure a circuit redistribution layer is formed on the surface of the encapsulating body to expose the active surface; a third carrier plate is placed on the circuit redistribution layer; the second carrier plate is removed; and the encapsulation colloid is formed to be exposed The blocking structure; and removing the third carrier plate.

另外，本發明提供一種半導體封裝件，係包括：具有複數個封裝膠體開孔的封裝膠體；嵌埋於該封裝膠體中的晶片，且該晶片具有外露於該封裝膠體的作用面；嵌埋於該封裝膠體中的擋止結構，其係外露於該封裝膠體外露該作用面之表面，且該擋止結構之位置對應該封裝膠體開 孔，而形成該擋止結構之材料係金屬或導電膠；形成於該封裝膠體外露該作用面的表面上的線路重佈層，該線路重佈層係電性連接該晶片與擋止結構；以及形成於該封裝膠體開孔中以電性連接該擋止結構的導電材料。In addition, the present invention provides a semiconductor package comprising: a package colloid having a plurality of package colloidal openings; a wafer embedded in the encapsulant, the wafer having an active surface exposed to the encapsulant; embedded in The blocking structure in the encapsulant is exposed on the surface of the encapsulating surface of the encapsulating body, and the position of the blocking structure corresponds to the encapsulation of the encapsulant a hole, and the material forming the stopper structure is a metal or a conductive paste; a circuit redistribution layer formed on a surface of the encapsulant exposed to the active surface, the circuit redistribution layer electrically connecting the wafer and the stopper structure; And a conductive material formed in the encapsulation opening to electrically connect the blocking structure.

本發明可藉由將擋止結構嵌埋於封裝膠體中並使其位置對應後續欲設置封裝膠體開孔之處，而使形成該封裝膠體開孔時所使用之雷射功率不穩定時不會對該線路重佈層造成損傷，從而提高生產的良率。The invention can embed the blocking structure in the encapsulant and make the position corresponding to the subsequent opening of the encapsulating colloid, so that the laser power used when forming the encapsulation opening is unstable. Damage to the redistribution layer of the line, thereby increasing the yield of production.

1‧‧‧半導體封裝件1‧‧‧Semiconductor package

11‧‧‧封裝膠體11‧‧‧Package colloid

112‧‧‧封裝膠體開孔112‧‧‧Package colloid opening

12a‧‧‧第一承載板12a‧‧‧First carrier board

12b‧‧‧第二承載板12b‧‧‧Second carrier board

12c‧‧‧第三承載板12c‧‧‧ third carrier board

122a‧‧‧第一黏著層122a‧‧‧First adhesive layer

122b‧‧‧第二黏著層122b‧‧‧second adhesive layer

122c‧‧‧第三黏著層122c‧‧‧ third adhesive layer

13‧‧‧晶片13‧‧‧ wafer

132‧‧‧作用面132‧‧‧Action surface

134‧‧‧銲墊134‧‧‧ solder pads

14‧‧‧擋止結構14‧‧‧stop structure

15‧‧‧線路重佈層15‧‧‧Line redistribution

150‧‧‧介電層150‧‧‧ dielectric layer

152‧‧‧第一電性連接墊152‧‧‧First electrical connection pad

154‧‧‧導電盲孔154‧‧‧ Conductive blind holes

156‧‧‧第二電性連接墊156‧‧‧Second electrical connection pad

157‧‧‧介電層開口157‧‧‧ Dielectric opening

17a‧‧‧第一導電元件17a‧‧‧First conductive element

17b‧‧‧第三導電元件17b‧‧‧ Third conductive element

18‧‧‧導電材料18‧‧‧Electrical materials

2‧‧‧封裝結構2‧‧‧Package structure

22‧‧‧第二導電元件22‧‧‧Second conductive element

第1A圖至第1H圖係說明習知技術中形成半導體封裝件之各步驟的剖視圖；第2A圖至第2J圖係說明本發明之半導體封裝件的製法之各步驟的剖視圖，其中，第2I’圖係第2I圖之另一實施態樣；以及第3A圖與第3B圖係說明本發明之半導體封裝件的製法之另一實施例之剖視圖。1A to 1H are cross-sectional views illustrating respective steps of forming a semiconductor package in the prior art; and FIGS. 2A to 2J are cross-sectional views illustrating respective steps of a method of fabricating the semiconductor package of the present invention, wherein 2I Another embodiment of the drawing of Fig. 2I; and Figs. 3A and 3B are cross-sectional views showing another embodiment of the method of fabricating the semiconductor package of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

請參閱第2A圖至第2J圖，其係說明根據本發明之半 導體封裝件之製法的剖視圖。Please refer to FIG. 2A to FIG. 2J, which illustrate the half according to the present invention. A cross-sectional view of a method of making a conductor package.

首先請參照第2A圖，提供一其上形成有第一黏著層122a的第一承載板12a，其中，第一承載板12a之材質可為玻璃、金屬及陶瓷等等，但本發明不限於此。之後，在第一黏著層122a上接置晶片13，而晶片13係具有接置於第一黏著層122a上的作用面132，且作用面132係形成有銲墊134。First, please refer to FIG. 2A to provide a first carrier 12a on which the first adhesive layer 122a is formed. The material of the first carrier 12a may be glass, metal, ceramic, etc., but the invention is not limited thereto. . Thereafter, the wafer 13 is attached to the first adhesive layer 122a, and the wafer 13 has an active surface 132 attached to the first adhesive layer 122a, and the active surface 132 is formed with a solder pad 134.

接著請參照第2B圖，其係將擋止結構14形成在第一黏著層122a未連接晶片13之區域上，其中形成擋止結構14之材料係金屬或導電膠，而該擋止結構14可選擇性地使用膠體形態的材料來形成，進一步而言，可使用金屬膠或導電膠來形成該擋止結構14，且擋止結構14投影至第一承載板12a的圖案可為圓形或矩形，但本發明不限於此。而本發明之另一實施例中可先將擋止結構14形成在第一黏著層122a上，再將晶片13接置於第一黏著層122a未形成擋止結構14之區域上。Referring to FIG. 2B , the blocking structure 14 is formed on a region where the first adhesive layer 122 a is not connected to the wafer 13 , wherein the material of the blocking structure 14 is metal or conductive paste, and the blocking structure 14 can be The material in the colloidal form is selectively formed. Further, the metal structure or the conductive paste may be used to form the blocking structure 14, and the pattern of the blocking structure 14 projected onto the first carrier 12a may be circular or rectangular. However, the invention is not limited thereto. In another embodiment of the present invention, the stopper structure 14 is first formed on the first adhesive layer 122a, and the wafer 13 is placed on the region where the first adhesive layer 122a does not form the stopper structure 14.

請參照第2C圖，其中係於該第一黏著層122a上形成封裝膠體11以包覆晶片13與擋止結構14，並在之後於封裝膠體11上接置第二承載板12b，其中，第二承載板12b係可選擇性地在其表面上形成有第二黏著層122b，以藉由第二黏著層122b接置封裝膠體11。而在本發明之另一實施例中，係將其上形成有封裝膠體11之第二承載板12b壓合至第一黏著層122a的表面上。Please refer to FIG. 2C , in which the encapsulant 11 is formed on the first adhesive layer 122 a to cover the wafer 13 and the blocking structure 14 , and then the second carrier 12 b is attached to the encapsulant 11 , wherein The second carrier 12b is selectively formed with a second adhesive layer 122b on its surface to receive the encapsulant 11 by the second adhesive layer 122b. In another embodiment of the present invention, the second carrier 12b on which the encapsulant 11 is formed is press-bonded to the surface of the first adhesive layer 122a.

請參照第2D圖，其中係接著將第一黏著層122a及第 一承載板12a從作用面132、擋止結構14及封裝膠體11的表面上移除，以至少外露作用面132、銲墊134、擋止結構14及一部分封裝膠體11。Please refer to FIG. 2D, in which the first adhesive layer 122a and the first layer are A carrier plate 12a is removed from the surface of the active surface 132, the stop structure 14, and the encapsulant 11 to expose at least the active surface 132, the pad 134, the stop structure 14, and a portion of the encapsulant 11.

請參照第2E圖，其係將線路重佈層15形成在作用面132、擋止結構14及封裝膠體11的外露表面上，並使線路重佈層15電性連接半導體之晶片13及電性連接擋止結構14。更具體而言，線路重佈層15係具有介電層150、線路(未標示元件符號)、第一電性連接墊152、導電盲孔154及第二電性連接墊156，其中，介電層150係形成在作用面132、擋止結構14及封裝膠體11的外露表面上，而介電層150內係在與該外露表面相接的一側形成有電性連接於晶片13之銲墊134及擋止結構14的第一電性連接墊152，此外第一電性連接墊152連接銲墊134及擋止結構14之側的另一側係形成有與其電性連接之導電盲孔154，而導電盲孔154與第一電性連接墊152連接之側的另一側形成有第二電性連接墊156。並且介電層150內係在其與封裝膠體11連接側的另一側形成有介電層開口157，以將第二電性連接墊156外露。Referring to FIG. 2E, the circuit redistribution layer 15 is formed on the exposed surface of the active surface 132, the stopper structure 14 and the encapsulant 11, and the circuit redistribution layer 15 is electrically connected to the semiconductor wafer 13 and the electrical The blocking structure 14 is connected. More specifically, the circuit redistribution layer 15 has a dielectric layer 150, a line (not labeled with a component symbol), a first electrical connection pad 152, a conductive blind via 154, and a second electrical connection pad 156, wherein the dielectric layer The layer 150 is formed on the exposed surface of the active surface 132, the blocking structure 14 and the encapsulant 11, and the dielectric layer 150 is formed on the side contacting the exposed surface to form a pad electrically connected to the wafer 13. 134 and the first electrical connection pad 152 of the blocking structure 14 , and the other side of the first electrical connection pad 152 connecting the pad 134 and the blocking structure 14 is formed with a conductive blind hole 154 electrically connected thereto The other side of the side where the conductive blind via 154 is connected to the first electrical connection pad 152 is formed with a second electrical connection pad 156. And a dielectric layer opening 157 is formed in the dielectric layer 150 on the other side of the connection side with the encapsulant 11 to expose the second electrical connection pad 156.

請參照第2F圖，其係於該線路重佈層15上接置一第三承載板12c，其中，第三承載板12c係可選擇性地在其表面上形成有第三黏著層122c，以藉由第三黏著層122c接置線路重佈層15，並移除該第二承載板12b與第二黏著層122b。Referring to FIG. 2F, a third carrier plate 12c is attached to the circuit redistribution layer 15, wherein the third carrier plate 12c is selectively formed with a third adhesive layer 122c on the surface thereof. The circuit redistribution layer 15 is attached by the third adhesive layer 122c, and the second carrier plate 12b and the second adhesive layer 122b are removed.

請參照第2G圖，其係在封裝膠體11中以例如為雷射 鑽孔的方式形成封裝膠體開孔112，以外露擋止結構14。在此步驟中，擋止結構14可避免習知技術中雷射鑽孔時因雷射功率不穩定而過大之功率對第一電性連接墊152所造成的傷害，從而避免線路重佈層15斷路。Please refer to FIG. 2G, which is, for example, a laser in the encapsulant 11 The way of drilling forms the encapsulation opening 112, the exposed stop structure 14. In this step, the blocking structure 14 can avoid the damage caused by the excessive power of the laser power due to the instability of the laser power to the first electrical connection pad 152 during the laser drilling in the prior art, thereby avoiding the line redistribution layer 15 . Open circuit.

請參照第2H圖，其係在封裝膠體開孔112中形成第一導電元件17a，以使其與擋止結構14電性連接，而導電元件可為導電凸塊或銲球等形式，且第一導電元件17a係位於封裝膠體開孔112中，或者，第一導電元件17a可選擇性地凸出於封裝膠體開孔112外(未圖示此情況)。Referring to FIG. 2H, the first conductive element 17a is formed in the encapsulation opening 112 to be electrically connected to the blocking structure 14. The conductive element may be in the form of a conductive bump or a solder ball. A conductive element 17a is located in the encapsulation opening 112, or the first conductive element 17a can be selectively protruded from the encapsulation opening 112 (not shown).

請參照第2I圖，其係將第三承載板12c與第三黏著層122c從第二電性連接墊156及介電層150的表面上移除。請參照第2J圖，其係於第二電性連接墊156上接置例如銲球的第三導電元件17b，並於該封裝膠體14上方接置一封裝結構2，該封裝結構2之底部上接置複數個第二導電元件22，而封裝結構2係經由封裝膠體開孔112中的第一導電元件17a與第二導電元件22電性連接線路重佈層15。在另一實施例中，係可選擇性地不在其底部上接置複數個第二導電元件22，以使封裝結構2僅經由第一導電元件17a電性連接線路重佈層15(未圖示此情況)。Referring to FIG. 2I, the third carrier layer 12c and the third adhesive layer 122c are removed from the surfaces of the second electrical connection pads 156 and the dielectric layer 150. Referring to FIG. 2J, a third conductive element 17b, such as a solder ball, is attached to the second electrical connection pad 156, and a package structure 2 is attached over the package body 14. The package structure 2 is on the bottom. A plurality of second conductive elements 22 are connected, and the package structure 2 is electrically connected to the circuit redistribution layer 15 via the first conductive elements 17a and the second conductive elements 22 in the package adhesive opening 112. In another embodiment, the plurality of second conductive elements 22 are selectively not disposed on the bottom portion thereof, so that the package structure 2 is electrically connected to the circuit redistribution layer 15 only via the first conductive elements 17a (not shown). This situation).

或者，本發明之半導體封裝件之製法的另一實施態樣係參照第2I’圖，其與上述之半導體封裝件之製法的相異之處係在於：直接在第2H圖之結構上接置一封裝結構2，以構成如第2I’圖之結構，之後，將第三承載板12c與第三黏著層122c從第二電性連接墊156及介電層150的表面 上移除，並在第二電性連接墊156上接置例如銲球的第三導電元件17b，以形成如第2J圖的態樣。Alternatively, another embodiment of the method of fabricating the semiconductor package of the present invention is directed to FIG. 2I, which differs from the method of fabricating the semiconductor package described above in that the structure is directly attached to the structure of the second embodiment. a package structure 2 to form a structure as in FIG. 2I. Thereafter, the third carrier layer 12c and the third adhesive layer 122c are removed from the surface of the second electrical connection pad 156 and the dielectric layer 150. The upper conductive element 17b, for example, a solder ball, is attached to the second electrical connection pad 156 to form a state as shown in FIG. 2J.

或者，於另一實施例中，形成擋止結構14之材料係非導電材料，故於第2G圖之步驟後，再以例如為電漿或溶劑溶解之方式(但本發明不限於此)移除擋止結構14，以外露該第一電性連接墊152，如第3A圖所示，且從而最後所形成之半導體封裝件係以第一導電元件17a直接連接第一電性連接墊152，如第3B圖所示。Alternatively, in another embodiment, the material forming the stop structure 14 is a non-conductive material, so after the step of FIG. 2G, it is dissolved in a manner such as plasma or solvent (but the invention is not limited thereto). Except for the blocking structure 14, the first electrical connection pad 152 is exposed, as shown in FIG. 3A, and thus the finally formed semiconductor package is directly connected to the first electrical connection pad 152 by the first conductive element 17a. As shown in Figure 3B.

本發明之半導體封裝件1係包括封裝膠體11、晶片13、擋止結構14、線路重佈層15及導電材料18。該半導體封裝件1中包含之各組成結構係詳細於下說明。The semiconductor package 1 of the present invention includes an encapsulant 11, a wafer 13, a stopper structure 14, a line redistribution layer 15, and a conductive material 18. The respective constituent structures included in the semiconductor package 1 will be described in detail below.

詳而言之，封裝膠體11係將晶片13及擋止結構14嵌埋於封裝膠體11之一側，並其中形成有複數個封裝膠體開孔112，其中該些封裝膠體開孔112係以雷射鑽孔方式形成，以將擋止結構14外露。In detail, the encapsulant 11 embeds the wafer 13 and the blocking structure 14 on one side of the encapsulant 11 and has a plurality of encapsulant openings 112 formed therein, wherein the encapsulation openings 112 are A shot drilling method is formed to expose the stop structure 14.

晶片13係具有外露於封裝膠體11的作用面132及銲墊134。The wafer 13 has an active surface 132 and a pad 134 exposed to the encapsulant 11 .

擋止結構14係嵌埋於封裝膠體11中，並外露於封裝膠體11外露之作用面132及銲墊134的表面，且擋止結構14之位置係對應封裝膠體開孔112，而形成擋止結構14之材料係金屬或導電膠，且該擋止結構14可選擇性地使用膠體形態的材料來形成，進一步而言，可使用金屬膠或導電膠來形成該擋止結構14。此外，擋止結構14投影至線路重佈層15的圖案係為圓形或矩形，但本發明不限於此。The blocking structure 14 is embedded in the encapsulant 11 and exposed on the exposed surface 132 of the encapsulant 11 and the surface of the pad 134, and the position of the blocking structure 14 corresponds to the encapsulation opening 112 to form a stop. The material of the structure 14 is a metal or a conductive paste, and the stopper structure 14 can be selectively formed using a material in a colloidal form. Further, the metal structure or the conductive paste can be used to form the stopper structure 14. Further, the pattern in which the stopper structure 14 is projected to the line redistribution layer 15 is circular or rectangular, but the present invention is not limited thereto.

線路重佈層15係形成於該封裝膠體11外露該作用面132的表面上，以電性連接該晶片13與擋止結構14，且導電材料18係形成於封裝膠體開孔112中，而導電材料18可以例如以下方式形成，如在封裝膠體開孔112中形成第一導電元件17a，以使其與第一電性連接墊152電性連接，而第一導電元件17a可為導電凸塊或銲球等形式，但本發明並不限於此，且第一導電元件17a可選擇性地位於封裝膠體開孔112中或凸出於封裝膠體開孔112外，而後復可包括封裝結構2，封裝結構2藉由位於其底部之複數個第二導電元件22而電性連接第一導電元件17a。因此，本發明之導電材料18可包括第一導電元件17a或可包括第一導電元件17a與第二導電元件22，該第一導電元件17a係形成於該封裝膠體開孔112中，該第二導電元件22係位於該封裝結構2之底部及該第一導電元件17a之間，並使該封裝結構2電性連接該第一導電元件17a。The circuit redistribution layer 15 is formed on the surface of the encapsulant 11 to expose the active surface 132 to electrically connect the wafer 13 and the blocking structure 14, and the conductive material 18 is formed in the encapsulation opening 112, and is electrically conductive. The material 18 can be formed, for example, in the form of a first conductive element 17a formed in the encapsulation opening 112 to electrically connect to the first electrical connection pad 152, and the first conductive element 17a can be a conductive bump or a solder ball or the like, but the invention is not limited thereto, and the first conductive element 17a may be selectively located in the encapsulation opening 112 or protruded from the encapsulation opening 112, and then may include the package structure 2, the package The structure 2 is electrically connected to the first conductive element 17a by a plurality of second conductive elements 22 at the bottom thereof. Therefore, the conductive material 18 of the present invention may include the first conductive element 17a or may include a first conductive element 17a and a second conductive element 22, the first conductive element 17a being formed in the encapsulation opening 112, the second The conductive element 22 is located between the bottom of the package structure 2 and the first conductive element 17a, and electrically connects the package structure 2 to the first conductive element 17a.

封裝結構2係任何形式之封裝結構，並藉由導電材料18而電性連接擋止結構14，從而形成封裝結構2與線路重佈層15之間的電性連接路徑。The package structure 2 is a package structure of any form, and is electrically connected to the stopper structure 14 by the conductive material 18, thereby forming an electrical connection path between the package structure 2 and the line redistribution layer 15.

而在本發明之另一實施例中，線路重佈層15上可接置與其電性連接的複數第三導電元件17b，該些第三導電元件17b可為導電凸塊或銲球等形式，但本發明並不限於此。In another embodiment of the present invention, the circuit redistribution layer 15 can be connected to a plurality of third conductive elements 17b electrically connected thereto, and the third conductive elements 17b can be in the form of conductive bumps or solder balls. However, the invention is not limited to this.

綜上所述，相較於習知技術，由於本發明係藉由將擋止結構形成在第一黏著層未連接晶片之區域上並使封裝膠體將其包覆，該擋止結構之位置係對應後續線路重佈層之 第一電性連接墊，從而在以雷射鑽孔的方式形成封裝膠體開孔的期間避免因雷射功率不穩所致之對第一電性連接墊所造成的傷害，進而提升線路重佈層的良率與產品可靠度。In summary, compared to the prior art, since the present invention is formed by forming a stopper structure on a region where the first adhesive layer is not connected to the wafer and encapsulating the encapsulant, the position of the stopper structure is Corresponding to the subsequent line redistribution layer The first electrical connection pad prevents damage to the first electrical connection pad caused by laser power instability during the formation of the encapsulation opening by laser drilling, thereby improving the line redistribution Layer yield and product reliability.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1‧‧‧半導體封裝件1‧‧‧Semiconductor package

11‧‧‧封裝膠體11‧‧‧Package colloid

112‧‧‧封裝膠體開孔112‧‧‧Package colloid opening

13‧‧‧晶片13‧‧‧ wafer

14‧‧‧擋止結構14‧‧‧stop structure

15‧‧‧線路重佈層15‧‧‧Line redistribution

152‧‧‧第一電性連接墊152‧‧‧First electrical connection pad

157‧‧‧介電層開口157‧‧‧ Dielectric opening

17a‧‧‧第一導電元件17a‧‧‧First conductive element

17b‧‧‧第三導電元件17b‧‧‧ Third conductive element

18‧‧‧導電材料18‧‧‧Electrical materials

2‧‧‧封裝結構2‧‧‧Package structure

22‧‧‧第二導電元件22‧‧‧Second conductive element

Claims (15)

一種半導體封裝件的製法，係包括：於一其上形成有第一黏著層的第一承載板上接置具有作用面之晶片，且該作用面係連接該第一黏著層；將擋止結構形成在該第一黏著層未連接該晶片之區域上；於該第一黏著層上形成包覆該晶片與擋止結構的封裝膠體，並於該封裝膠體上接置第二承載板；移除該第一黏著層及該第一承載板，以外露該作用面與擋止結構；於該封裝膠體外露該作用面之表面上形成電性連接該半導體晶片與連接擋止結構的線路重佈層；於該線路重佈層上接置一第三承載板；移除該第二承載板；形成外露該擋止結構的封裝膠體開孔；以及移除該第三承載板。A method of manufacturing a semiconductor package, comprising: mounting a wafer having an active surface on a first carrier plate on which a first adhesive layer is formed, and the active surface is connected to the first adhesive layer; Forming on the region where the first adhesive layer is not connected to the wafer; forming an encapsulant covering the wafer and the stopper structure on the first adhesive layer, and attaching the second carrier on the encapsulant; removing The first adhesive layer and the first carrier plate expose the active surface and the blocking structure; forming a circuit redistribution layer electrically connecting the semiconductor wafer and the connection blocking structure on the surface of the working surface of the encapsulant And a third carrier plate is disposed on the circuit redistribution layer; the second carrier plate is removed; an encapsulation opening for exposing the blocking structure is formed; and the third carrier plate is removed. 如申請專利範圍第1項所述之半導體封裝件的製法，於移除該第三承載板後或於移除該第三承載板前，復包括於該封裝膠體上方接置一封裝結構，該封裝結構係經由該封裝膠體開孔電性連接該線路重佈層。The method of manufacturing the semiconductor package of claim 1, after the third carrier is removed or before the third carrier is removed, a package structure is disposed above the package. The structure is electrically connected to the circuit redistribution layer via the encapsulation opening. 如申請專利範圍第2項所述之半導體封裝件的製法，復包括在形成該封裝膠體開孔後，於該封裝膠體開孔中形成第一導電元件，其係電性連接該線路重佈層且用以電性連接該封裝結構。The method for manufacturing a semiconductor package according to claim 2, further comprising forming a first conductive component in the opening of the encapsulant after forming the opening of the encapsulant, and electrically connecting the re-layer of the circuit And used to electrically connect the package structure. 如申請專利範圍第3項所述之半導體封裝件的製法，復包括於接置該封裝結構前，於該封裝結構之底部上接置複數用以電性連接該線路重佈層的第二導電元件，且接置該封裝結構復包括使該第一導電元件電性連接該第二導電元件。The method for manufacturing a semiconductor package according to claim 3, further comprising: before the connecting the package structure, connecting a plurality of second conductive materials electrically connected to the circuit redistribution layer on the bottom of the package structure; The component, and the connecting the package structure comprises electrically connecting the first conductive component to the second conductive component. 如申請專利範圍第1項所述之半導體封裝件的製法，復包括於移除該第三承載板後，於該線路重佈層上接置複數第三導電元件。The method for manufacturing a semiconductor package according to claim 1, further comprising: after removing the third carrier, connecting a plurality of third conductive elements on the circuit redistribution layer. 如申請專利範圍第1項所述之半導體封裝件的製法，其中，該封裝膠體開孔係藉由雷射來形成。The method of fabricating a semiconductor package according to claim 1, wherein the encapsulation opening is formed by laser. 如申請專利範圍第1項所述之半導體封裝件的製法，其中，形成該擋止結構之材料係金屬或導電膠。The method of fabricating a semiconductor package according to claim 1, wherein the material forming the stopper structure is a metal or a conductive paste. 如申請專利範圍第1項所述之半導體封裝件的製法，其中，形成該擋止結構之材料係非導電材料，且於形成該封裝膠體開孔後，復包括移除該擋止結構。The method of manufacturing the semiconductor package of claim 1, wherein the material forming the blocking structure is a non-conductive material, and after forming the opening of the encapsulant, the removing structure is removed. 如申請專利範圍第8項所述之半導體封裝件的製法，其中，移除該擋止結構之方式係藉由溶劑或電漿為之。The method of fabricating a semiconductor package according to claim 8, wherein the blocking structure is removed by a solvent or a plasma. 如申請專利範圍第1項所述之半導體封裝件的製法，其中，該擋止結構投影至該第一承載板的圖案係為圓形或矩形。The method of fabricating a semiconductor package according to claim 1, wherein the pattern projected onto the first carrier by the blocking structure is circular or rectangular. 一種半導體封裝件，係包括：封裝膠體，係具有複數封裝膠體開孔；晶片，係嵌埋於該封裝膠體中，且具有外露於該封裝膠體的作用面； 擋止結構，係嵌埋於該封裝膠體中，並外露於該封裝膠體外露該作用面之表面，且該擋止結構之位置對應該封裝膠體開孔，形成該擋止結構之材料係金屬或導電膠；線路重佈層，係形成於該封裝膠體外露該作用面的表面上，以電性連接該晶片與擋止結構；以及導電材料，係形成於該封裝膠體開孔中，以電性連接該擋止結構。A semiconductor package comprising: an encapsulant having a plurality of encapsulation openings; a wafer embedded in the encapsulant and having an active surface exposed to the encapsulant; The blocking structure is embedded in the encapsulant and exposed on the surface of the encapsulating body, and the position of the blocking structure corresponds to the encapsulation opening, and the material forming the blocking structure is metal or a conductive paste; a circuit redistribution layer formed on a surface of the encapsulating glue exposed to the active surface to electrically connect the wafer and the blocking structure; and a conductive material formed in the opening of the encapsulant, electrically Connect the stop structure. 如申請專利範圍第11項所述之半導體封裝件，復包括封裝結構，係位於該封裝膠體上方，且電性連接該導電材料。The semiconductor package of claim 11, further comprising a package structure disposed above the encapsulant and electrically connected to the conductive material. 如申請專利範圍第11項所述之半導體封裝件，其中，該導電材料復包括第一導電元件與第二導電元件，該第一導電元件係形成於該封裝膠體開孔中，該第二導電元件係位於該封裝結構之底部及該第一導電元件之間，並使該封裝結構電性連接該第一導電元件。The semiconductor package of claim 11, wherein the conductive material comprises a first conductive element and a second conductive element, the first conductive element being formed in the encapsulation opening, the second conductive The component is located between the bottom of the package structure and the first conductive component, and electrically connects the package structure to the first conductive component. 如申請專利範圍第11項所述之半導體封裝件，復包括接置於該線路重佈層上的複數第三導電元件。The semiconductor package of claim 11, further comprising a plurality of third conductive elements attached to the circuit redistribution layer. 如申請專利範圍第11項所述之半導體封裝件，其中，該擋止結構投影至該線路重佈層的圖案係為圓形或矩形。The semiconductor package of claim 11, wherein the pattern of the stop structure projected onto the line redistribution layer is circular or rectangular.
TW102141421A 2013-11-14 2013-11-14 Semiconductor package and manufacturing method thereof TWI508197B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW102141421A TWI508197B (en) 2013-11-14 2013-11-14 Semiconductor package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW102141421A TWI508197B (en) 2013-11-14 2013-11-14 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201519335A TW201519335A (en) 2015-05-16
TWI508197B true TWI508197B (en) 2015-11-11

Family

ID=53721041

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102141421A TWI508197B (en) 2013-11-14 2013-11-14 Semiconductor package and manufacturing method thereof

Country Status (1)

Country Link
TW (1) TWI508197B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720049A (en) * 2014-12-15 2016-06-29 英特尔公司 Opossum-die package-on-package apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112635412A (en) * 2020-12-21 2021-04-09 苏州日月新半导体有限公司 Semiconductor structure and method for manufacturing semiconductor structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201227921A (en) * 2010-12-21 2012-07-01 Powertech Technology Inc Stack structure for packages
TW201308553A (en) * 2011-08-10 2013-02-16 Advanced Semiconductor Eng Wafer level package and manufacturing method thereof
US8390108B2 (en) * 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8390108B2 (en) * 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
TW201227921A (en) * 2010-12-21 2012-07-01 Powertech Technology Inc Stack structure for packages
TW201308553A (en) * 2011-08-10 2013-02-16 Advanced Semiconductor Eng Wafer level package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105720049A (en) * 2014-12-15 2016-06-29 英特尔公司 Opossum-die package-on-package apparatus

Also Published As

Publication number Publication date
TW201519335A (en) 2015-05-16

Similar Documents

Publication Publication Date Title
TWI460834B (en) Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof
US9412714B2 (en) Wire bond support structure and microelectronic package including wire bonds therefrom
TWI418003B (en) Package structure having embedded electronic component and fabrication method thereof
TWI413223B (en) Package substrate having semiconductor component embedded therein and fabrication method thereof
TWI646642B (en) Chip package structure and method of manufacturing same
US10002823B2 (en) Packaging substrate and method of fabricating the same
TWI614848B (en) Electronic package and method of manufacture thereof
JP2009026805A (en) Semiconductor device and its manufacturing method
TWI556379B (en) Semiconductor package and manufacturing method thereof
US9607860B2 (en) Electronic package structure and fabrication method thereof
TW201603215A (en) Package structure and method of manufacture
TW202013634A (en) Electronic package and manufacturing method thereof
KR101179386B1 (en) Fabricating method of package substrate
TWI567888B (en) Package structure and method of manufacture
TWI624020B (en) Electronic package and method for fabricating the same
TWI508197B (en) Semiconductor package and manufacturing method thereof
TWI567843B (en) Package substrate and the manufacture thereof
TWI624011B (en) Package structure and the manufacture thereof
TWI438880B (en) Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof
US10043757B2 (en) Semiconductor package structure and method of fabricating the same
TWI546931B (en) Method for manufacturing semiconductor device
US9373526B2 (en) Chip package and method for forming the same
TWI541952B (en) Semiconductor package and manufacturing method thereof
TWI591788B (en) Method for manufacturing electronic package
TWI776678B (en) Semiconductor package and manufacturing method thereof