TWI546931B - Method for manufacturing semiconductor device - Google Patents

Description

Semiconductor device manufacturing method

The present invention relates to a method of fabricating a semiconductor device.

At present, a semiconductor device having a plurality of wafers is manufactured by first arranging a first wafer on a top surface of an interposer; then, arranging a second wafer on the bottom surface of the interposer Then, the interposer having the first wafer and the second wafer is mounted on a circuit substrate such that the interposer is located between the second wafer and the circuit substrate. However, in the above method, the second wafer is first mounted on the interposer and then electrically connected to the circuit substrate, which easily causes the second wafer to collide or damage during the process, resulting in electrical failure and scrap.

In view of the above, it is necessary to provide a method of fabricating a semiconductor device to improve electrical connection performance between a wafer and a circuit substrate.

A method of fabricating a semiconductor device, comprising the steps of: providing a circuit carrier, the circuit carrier comprising a circuit substrate formed with a conductive line and a first wafer, the circuit substrate having a plurality of first electrical properties exposed a contact pad, the first wafer has opposite active and inactive surfaces, the first wafer is embedded in the circuit substrate, electrically connected to the conductive line in the circuit substrate, and the active surface is relatively non- An active surface is adjacent to the plurality of first electrical contact pads; an interposer is provided, the interposer has a plurality of exposed first electrical connection pads, and the interposer is mounted on the circuit carrier The first electrical connection pads of the plurality of first electrical connection pads of the interposer are electrically connected to a first electrical contact pad through a first conductive member; and provide a second a wafer, and the second wafer is mounted on a side of the interposer away from the circuit carrier, such that the second wafer is electrically connected to the circuit carrier through the interposer.

In the method of fabricating the semiconductor device of the present invention, the first wafer in the circuit carrier is buried in the circuit substrate, and then the interposer is mounted on the circuit carrier, such that the first wafer and the circuit substrate are The electrical connection performance is high, thereby avoiding the first failure of the first wafer to be mounted on the interposer, and then causing electrical failure and scrapping caused by the collision or damage of the first wafer when the first wafer is mounted on the circuit substrate, thereby improving The production efficiency of the semiconductor device reduces the manufacturing cost of the semiconductor device. In addition, the first wafer is buried in the circuit substrate, which reduces the thickness of the circuit carrier, thereby reducing the overall thickness of the semiconductor device having the circuit carrier, which meets the requirements of light weight and low cost in the market.

10. . . Circuit carrier

11. . . Circuit substrate

13. . . First wafer

111. . . Base

113. . . First conductive line pattern

115. . . Second conductive line pattern

117. . . First solder mask

119. . . Second solder mask

11a. . . First inner conductive line pattern

11b. . . Second inner conductive circuit pattern

11c, 11d, 11e, 25. . . Conductive hole

111a. . . First surface

111b. . . Second surface

112. . . Containing groove

116. . . First electrical contact pad

118. . . Solder pad

131, 301. . . Active surface

133, 303. . . Inactive surface

134, 31. . . Electrode pad

20. . . Intermediary board

201. . . Bottom

203. . . Top surface

twenty one. . . First electrical connection pad

twenty three. . . Second electrical connection pad

26. . . First conductive member

30. . . Second chip

33. . . Second conductive member

40. . . Encapsulant

50. . . Solder ball

100. . . Semiconductor device

1 is a cross-sectional view of a circuit carrier provided by an embodiment of the present technical solution.

Figure 2 is an enlarged view of a portion II of Figure 1.

3 is a cross-sectional view showing the interposer in the embodiment of the present invention after the interposer is mounted on the circuit carrier shown in FIG. 1.

4 is a cross-sectional view showing a second wafer after being assembled on the interposer of FIG. 3 according to an embodiment of the present technology.

FIG. 5 is a cross-sectional view of the interposer of FIG. 4 after the encapsulant is disposed on the interposer of FIG. 4 according to an embodiment of the present disclosure.

FIG. 6 is a cross-sectional view of the semiconductor device obtained after the ball is implanted on the pad of the circuit carrier shown in FIG. 5 according to an embodiment of the present application.

The method for fabricating the semiconductor device provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.

A method of fabricating a semiconductor device provided by an embodiment of the present technical solution includes the following steps:

In the first step, referring to Figures 1 and 2, a circuit carrier 10 is provided. The circuit carrier 10 includes a circuit substrate 11 and a first wafer 13 embedded in the circuit substrate 11.

The circuit substrate 11 may be a double-sided circuit board or a multi-layer circuit board formed with a conductive line, and has a substrate 111, a first conductive line pattern 113, a second conductive line pattern 115, a first solder resist layer 117, and a second solder resist. Layer 119. In the present embodiment, the circuit substrate 11 is a four-layer circuit board having a first inner conductive trace pattern 11a and a second inner conductive trace pattern 11b. The first inner conductive trace pattern 11a is electrically connected to the second inner conductive trace pattern 11b through the conductive via 11c in the substrate 111.

The substrate 111 has opposing first and second surfaces 111a, 111b. The substrate 111 also has a receiving recess 112. The receiving groove 112 is recessed from the partial first surface 111a toward the second surface 111b for receiving the first wafer 13.

The first conductive line pattern 113 is formed on the first surface 111a of the substrate 111. The first conductive line pattern 113 is electrically connected to the first inner layer conductive line pattern 11a through the conductive holes 11d in the substrate 111.

The second conductive line pattern 115 is formed on the second surface 111b of the substrate 111. The second conductive trace pattern 115 is electrically connected to the second inner conductive trace pattern 11b through the conductive vias 11e in the substrate 111.

The first solder resist layer 117 covers the surface and the gap of the first conductive trace pattern 113, and the second solder resist layer 119 covers the surface and the gap of the second conductive trace pattern 115, and is disposed on the first solder resist layer 117. And the second solder resist layer 119 is formed with a plurality of open regions to define a bare copper surface in the open region of the first solder resist layer 117 as a first electrical contact pad 116, and the second solder resist layer 119 The bare copper surface in the open area is the pad 118.

The first wafer 13 is received in the receiving recess 112. The first wafer 13 has opposing active faces 131 and inactive faces 133. The active surface 131 has a plurality of electrode pads 134 thereon. Each of the plurality of electrode pads 134 is electrically connected to the first conductive line pattern 113.

The circuit carrier 10 can be fabricated by first providing the circuit substrate 11 and the first wafer 13; secondly, placing the first wafer 13 in the receiving recess 112 such that the active surface 131 of the first wafer 13 is The inactive surface 133 is adjacent to the plurality of first electrical contact pads 116; the first conductive line pattern 113 is formed on the first surface 111a and the plurality of electrode pads 134 by a semi-additive method, and the second conductive layer is formed on the second surface 111b. a line pattern 115 electrically connecting the first conductive line pattern 113 and the first inner layer conductive line pattern 11a, electrically connecting the second conductive line pattern 115 and the second inner layer conductive line pattern 11b; and the first conductive line pattern 113 A first solder resist layer 117 is formed in the gap, a second solder resist layer 119 is formed on the second conductive trace pattern 115 and the gap thereof, and a plurality of open regions are formed in the first solder resist layer 117 and the second solder resist layer 119. The bare copper surface in the open area of the first solder resist layer 117 is defined as the first electrical contact pad 116, and the bare copper surface in the open area of the second solder resist layer 119 is the solder pad 118. In this way, the circuit carrier board 10 can be obtained.

In the second step, referring to FIG. 3, an interposer 20 is provided. The area of the interposer 20 is larger than the projected area of the receiving recess 112 on the first surface 111a, and has an opposite bottom surface 201 and a top surface 203. The material of the interposer 20 is glass, which has a plurality of exposed first electrical connection pads 21 and a plurality of second electrical connection pads 23. The plurality of first electrical connection pads 21 are located on the side of the bottom surface 201 of the interposer 20, and the plurality of second electrical connection pads 23 are located on the top surface 203 of the interposer 20, and the plurality of first electrical connection pads The at least one first electrical connection pad 21 of the 21 is electrically connected to the at least one second electrical connection pad 23 of the plurality of second electrical connection pads 23 through the conductive holes 25 in the interposer 20 . In this embodiment, the number of the plurality of first electrical connection pads 21 is the same as the number of the plurality of first electrical contact pads 116, and the number of the plurality of first electrical connection pads 21 is less than the plurality of second electrical connections. The number of pads 23.

The interposer 20 is mounted on the circuit carrier 10 such that each of the plurality of first electrical connection pads 21 of the interposer 20 passes through a first conductive member 26 and has a first The contact pads 116 are electrically connected. The first conductive member 26 may be a solder ball or a bump. In the embodiment, the first conductive member 26 is a solder ball.

In the third step, referring to FIG. 4, a second wafer 30 is provided. The second wafer 30 has opposing active faces 301 and inactive faces 303. The active surface 301 has a plurality of exposed electrode pads 31 thereon.

The second wafer 30 is mounted on the side of the interposer 20 remote from the circuit carrier 10. In this embodiment, the second wafer 30 is mounted on the interposer 20 by flip chip packaging, and each of the plurality of electrode pads 31 of the second wafer 30 is provided with a second conductive member 33 and a first The two electrical connection pads 23 are electrically connected. The second conductive member 33 may be a solder ball or a bump. In the embodiment, the second conductive member 33 is a solder ball.

In the fourth step, referring to FIG. 5, an encapsulant 40 is disposed on the side of the interposer 20 remote from the circuit carrier 10. The encapsulant covers the second wafer 30, the interposer 20, and the first surface 111a of the circuit carrier 10 exposed from the interposer 20 to protect the second wafer 30 and the interposer 20 from damage. The material of the encapsulant 40 is an epoxy molding compound.

In the fifth step, referring to FIG. 6, a solder ball 50 is implanted on each of the plurality of pads 118 by a printing coating method. The material of the solder ball 50 generally includes mainly tin. In this embodiment, the diameter of the solder ball 50 is larger than the diameter of the first conductive member 26, and the diameter of the first conductive member 26 is larger than the diameter of the second conductive member 33. Of course, the solder ball 50 can also be formed by other ball-planting methods, such as spray solder paste ball, laser ball-planting, etc., and is not limited to this embodiment. Thus, the semiconductor device 100 having the first wafer 12 and the interposer 20 can be obtained.

In the manufacturing method of the semiconductor device 100 in the present technical solution, the first wafer 13 in the circuit carrier 10 is directly mounted on the circuit substrate 11, and then the interposer 20 is mounted on the circuit carrier 10, so that The electrical connection between the wafer 13 and the circuit substrate 11 is high, and the electricity generated when the first wafer 13 is first mounted on the interposer 20 and the interposer 20 is mounted on the circuit substrate 11 can be avoided. The lack of sexual conditions improves the production efficiency of semiconductor devices and reduces the manufacturing cost of semiconductor devices. In addition, the first wafer 13 is received in the receiving recess 112, which reduces the overall thickness of the semiconductor device and meets the requirements of light weight and low cost of the market products.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10. . . Circuit carrier

118. . . Solder pad

20. . . Intermediary board

30. . . Second chip

40. . . Encapsulant

50. . . Solder ball

100. . . Semiconductor device

Claims (8)

A method of fabricating a semiconductor device, comprising the steps of:
Providing a circuit carrier, the circuit carrier comprising a circuit substrate formed with a conductive line and a first wafer, the circuit substrate having a plurality of exposed first electrical contact pads, the first wafer having a relative The active surface and the inactive surface, the first wafer is embedded in the circuit substrate, electrically connected to the conductive line in the circuit substrate, and the active surface is closer to the plurality of the active surface than the active surface An electrical contact pad;
Providing an interposer having a plurality of exposed first electrical connection pads and mounting the interposer on the circuit carrier board such that the plurality of first electrical properties of the interposer Each of the first electrical connection pads in the connection pad is electrically connected to a first electrical contact pad through a first conductive member; and a second wafer is provided, and the second wafer is mounted on the The interposer is remote from a side of the circuit carrier such that the second wafer is electrically connected to the circuit carrier through the interposer. The method of fabricating a semiconductor device according to claim 1, wherein the semiconductor device is fabricated after the step of disposing the second wafer on a side of the interposer away from the circuit carrier. The method also includes the step of providing an encapsulant on a side of the interposer remote from the circuit carrier, the encapsulant covering the second wafer, the interposer, and a surface of the circuit carrier exposed from the interposer. The method for fabricating a semiconductor device according to claim 2, wherein the material of the encapsulant is an epoxy molding compound. The method of fabricating the semiconductor device of claim 2, wherein the circuit carrier further has a plurality of exposed pads on a side away from the interposer, after the step of disposing the encapsulant The method of fabricating the semiconductor device further includes the step of implanting a solder ball on each of the plurality of pads. The method of fabricating a semiconductor device according to claim 1, wherein the interposer has opposite top and bottom surfaces, and the plurality of first electrical connection pads are exposed on a bottom side of the interposer The interposer further has a plurality of second electrical connection pads, the plurality of second electrical connection pads being exposed on a top side of the interposer, and the plurality of second electrical connection pads The at least one second electrical connection pad is electrically connected to the at least one first electrical connection pad of the plurality of first electrical connection pads through at least one conductive hole in the interposer, a second wafer is mounted on a side of the interposer away from the circuit carrier, at least one of the second wafer and the plurality of second electrical connection pads in the interposer The connection pads are electrically connected. The method of fabricating a semiconductor device according to claim 5, wherein the second wafer has an active surface, and the active surface of the second wafer has a plurality of electrode pads, and the second wafer is In the step of disposing the interposer on a side away from the circuit carrier, each of the plurality of electrode pads of the second wafer passes through a second conductive member and the interposer One of the second electrical connection pads is electrically connected. The method of fabricating a semiconductor device according to claim 1, wherein the first conductive member is a solder ball, and the diameter of the first conductive member is smaller than a diameter of a solder ball on the solder pad. The method of fabricating a semiconductor device according to claim 1, wherein the first conductive member is a bump.