TW201445696A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- TW201445696A TW201445696A TW102119231A TW102119231A TW201445696A TW 201445696 A TW201445696 A TW 201445696A TW 102119231 A TW102119231 A TW 102119231A TW 102119231 A TW102119231 A TW 102119231A TW 201445696 A TW201445696 A TW 201445696A
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- interposer
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- electrical connection
- circuit carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
Description
本發明涉及半導體器件的製作方法。The present invention relates to a method of fabricating a semiconductor device.
目前,具有多個晶片的半導體器件的製作方法為:首先,將一個第一晶片構裝於一個中介板(interposer)的頂面上;然後,將一個第二晶片構裝於該中介板的底面上;接著,將構裝有第一晶片及第二晶片的中介板構裝於一個電路基板上,使得中介板位於該第二晶片與電路基板之間。然而,上述方法中,先將第二晶片構裝於中介板上,再電連接至電路基板,容易在過程中造成第二晶片碰撞或者損害,而導致電性失效與報廢。At present, a semiconductor device having a plurality of wafers is manufactured by first arranging a first wafer on a top surface of an interposer; then, arranging a second wafer on the bottom surface of the interposer Then, the interposer having the first wafer and the second wafer is mounted on a circuit substrate such that the interposer is located between the second wafer and the circuit substrate. However, in the above method, the second wafer is first mounted on the interposer and then electrically connected to the circuit substrate, which easily causes the second wafer to collide or damage during the process, resulting in electrical failure and scrap.
有鑒於此,有必要提供一種半導體器件的製作方法,以提高晶片與電路基板之間的電性連接性能。In view of the above, it is necessary to provide a method of fabricating a semiconductor device to improve electrical connection performance between a wafer and a circuit substrate.
一種半導體器件的製作方法,包括步驟:提供一個電路載板,所述電路載板包括一個形成有導電線路的電路基板及一個第一晶片,所述電路基板具有暴露出的多個第一電性接觸墊,所述第一晶片具有相對的主動面及非主動面,所述第一晶片埋入所述電路基板,與所述電路基板中的導電線路電性相連,且所述主動面較非主動面靠近所述多個第一電性接觸墊;提供一個中介板,所述中介板具有暴露出的多個第一電性連接墊,並將所述中介板構裝於所述電路載板上,使得所述中介板的多個第一電性連接墊中的每個第一電性連接墊均通過一個第一導電構件與一個第一電性接觸墊電性相連;及提供一個第二晶片,並將所述第二晶片構裝在所述中介板遠離所述電路載板的一側,使得所述第二晶片通過所述中介板與所述電路載板電性相連。A method of fabricating a semiconductor device, comprising the steps of: providing a circuit carrier, the circuit carrier comprising a circuit substrate formed with a conductive line and a first wafer, the circuit substrate having a plurality of first electrical properties exposed a contact pad, the first wafer has opposite active and inactive surfaces, the first wafer is embedded in the circuit substrate, electrically connected to the conductive line in the circuit substrate, and the active surface is relatively non- An active surface is adjacent to the plurality of first electrical contact pads; an interposer is provided, the interposer has a plurality of exposed first electrical connection pads, and the interposer is mounted on the circuit carrier The first electrical connection pads of the plurality of first electrical connection pads of the interposer are electrically connected to a first electrical contact pad through a first conductive member; and provide a second a wafer, and the second wafer is mounted on a side of the interposer away from the circuit carrier, such that the second wafer is electrically connected to the circuit carrier through the interposer.
本技術方案的中的半導體器件的製作方法中,電路載板中的第一晶片埋入電路基板中,而後再將中介板構裝於電路載板上,如此,第一晶片與電路基板之間的電性連接性能較高,進而可以避免先將第一晶片構裝於中介板上,再將第一晶片構裝於電路基板時碰撞或者損害第一晶片所導致的電性失效與報廢,提高了半導體器件的生產效率,降低了半導體器件的製造成本。另外,第一晶片埋入所述電路基板中,降低了電路載板的厚度,進而降低了具有該電路載板的半導體器件的整體厚度,符合市場產品輕薄化和低成本的需求。In the method of fabricating the semiconductor device of the present invention, the first wafer in the circuit carrier is buried in the circuit substrate, and then the interposer is mounted on the circuit carrier, such that the first wafer and the circuit substrate are The electrical connection performance is high, thereby avoiding the first failure of the first wafer to be mounted on the interposer, and then causing electrical failure and scrapping caused by the collision or damage of the first wafer when the first wafer is mounted on the circuit substrate, thereby improving The production efficiency of the semiconductor device reduces the manufacturing cost of the semiconductor device. In addition, the first wafer is buried in the circuit substrate, which reduces the thickness of the circuit carrier, thereby reducing the overall thickness of the semiconductor device having the circuit carrier, which meets the requirements of light weight and low cost in the market.
10...電路載板10. . . Circuit carrier
11...電路基板11. . . Circuit substrate
13...第一晶片13. . . First wafer
111...基底111. . . Base
113...第一導電線路圖形113. . . First conductive line pattern
115...第二導電線路圖形115. . . Second conductive line pattern
117...第一防焊層117. . . First solder mask
119...第二防焊層119. . . Second solder mask
11a...第一內層導電線路圖形11a. . . First inner conductive line pattern
11b...第二內層導電線路圖形11b. . . Second inner conductive circuit pattern
11c、11d、11e、25...導電孔11c, 11d, 11e, 25. . . Conductive hole
111a...第一表面111a. . . First surface
111b...第二表面111b. . . Second surface
112...收容凹槽112. . . Containing groove
116...第一電性接觸墊116. . . First electrical contact pad
118...焊墊118. . . Solder pad
131、301...主動面131, 301. . . Active surface
133、303...非主動面133, 303. . . Inactive surface
134、31...電極墊134, 31. . . Electrode pad
20...中介板20. . . Intermediary board
201...底面201. . . Bottom
203...頂面203. . . Top surface
21...第一電性連接墊twenty one. . . First electrical connection pad
23...第二電性連接墊twenty three. . . Second electrical connection pad
26...第一導電構件26. . . First conductive member
30...第二晶片30. . . Second chip
33...第二導電構件33. . . Second conductive member
40...封裝膠體40. . . Encapsulant
50...焊球50. . . Solder ball
100...半導體器件100. . . Semiconductor device
圖1是本技術方案實施例提供的電路載板的的剖面示意圖。1 is a cross-sectional view of a circuit carrier provided by an embodiment of the present technical solution.
圖2是圖1中II部分的放大圖。Figure 2 is an enlarged view of a portion II of Figure 1.
圖3是本技術方案實施例中將中介板構裝於圖1所示的電路載板後的剖面示意圖。3 is a cross-sectional view showing the interposer in the embodiment of the present invention after the interposer is mounted on the circuit carrier shown in FIG. 1.
圖4是本技術方案實施例提供的在圖3的中介板上構裝一個第二晶片後的剖面示意圖。4 is a cross-sectional view showing a second wafer after being assembled on the interposer of FIG. 3 according to an embodiment of the present technology.
圖5是本技術方案實施例提供的在圖4的中介板上設置封裝膠體後的剖面示意圖。FIG. 5 is a cross-sectional view of the interposer of FIG. 4 after the encapsulant is disposed on the interposer of FIG. 4 according to an embodiment of the present disclosure.
圖6是本技術方案實施例提供的在圖5所示的電路載板的焊墊上植球後所獲得的半導體器件的剖面示意圖。FIG. 6 is a cross-sectional view of the semiconductor device obtained after the ball is implanted on the pad of the circuit carrier shown in FIG. 5 according to an embodiment of the present application.
下面將結合附圖及實施例對本技術方案提供的半導體器件的製作方法作進一步的詳細說明。The method for fabricating the semiconductor device provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.
本技術方案實施例提供的半導體器件的製作方法包括以下步驟:A method of fabricating a semiconductor device provided by an embodiment of the present technical solution includes the following steps:
第一步,請參閱圖1及圖2,提供一個電路載板10。電路載板10包括一個電路基板11及一個埋入電路基板11的第一晶片13。In the first step, referring to Figures 1 and 2, a circuit carrier 10 is provided. The circuit carrier 10 includes a circuit substrate 11 and a first wafer 13 embedded in the circuit substrate 11.
電路基板11可以為形成有導電線路的雙面電路板或者多層電路板,其具有一個基底111、第一導電線路圖形113、第二導電線路圖形115、第一防焊層117及第二防焊層119。本實施例中,電路基板11為四層電路板,基底111內具有第一內層導電線路圖形11a及第二內層導電線路圖形11b。第一內層導電線路圖形11a通過基底111中的導電孔11c與第二內層導電線路圖形11b電性相連。The circuit substrate 11 may be a double-sided circuit board or a multi-layer circuit board formed with a conductive line, and has a substrate 111, a first conductive line pattern 113, a second conductive line pattern 115, a first solder resist layer 117, and a second solder resist. Layer 119. In the present embodiment, the circuit substrate 11 is a four-layer circuit board having a first inner conductive trace pattern 11a and a second inner conductive trace pattern 11b. The first inner conductive trace pattern 11a is electrically connected to the second inner conductive trace pattern 11b through the conductive via 11c in the substrate 111.
基底111具有相對的第一表面111a及第二表面111b。基底111還具有一個收容凹槽112。收容凹槽112由部分第一表面111a向第二表面111b凹陷形成,用於收容第一晶片13。The substrate 111 has opposing first and second surfaces 111a, 111b. The substrate 111 also has a receiving recess 112. The receiving groove 112 is recessed from the partial first surface 111a toward the second surface 111b for receiving the first wafer 13.
第一導電線路圖形113形成於基底111的第一表面111a。第一導電線路圖形113通過基底111中的導電孔11d與第一內層導電線路圖形11a電性相連。The first conductive line pattern 113 is formed on the first surface 111a of the substrate 111. The first conductive line pattern 113 is electrically connected to the first inner layer conductive line pattern 11a through the conductive holes 11d in the substrate 111.
第二導電線路圖形115形成於基底111的第二表面111b。第二導電線路圖形115通過基底111中的導電孔11e與第二內層導電線路圖形11b電性相連。The second conductive line pattern 115 is formed on the second surface 111b of the substrate 111. The second conductive trace pattern 115 is electrically connected to the second inner conductive trace pattern 11b through the conductive vias 11e in the substrate 111.
第一防焊層117覆蓋所述第一導電線路圖形113的表面及間隙,所述第二防焊層119覆蓋所述第二導電線路圖形115的表面及間隙,並於第一防焊層117及第二防焊層119形成有多個開口區,以定義所述第一防焊層117的開口區中裸露的銅面為第一電性接觸墊116,及所述第二防焊層119的開口區中裸露的銅面為焊墊118。The first solder resist layer 117 covers the surface and the gap of the first conductive trace pattern 113, and the second solder resist layer 119 covers the surface and the gap of the second conductive trace pattern 115, and is disposed on the first solder resist layer 117. And the second solder resist layer 119 is formed with a plurality of open regions to define a bare copper surface in the open region of the first solder resist layer 117 as a first electrical contact pad 116, and the second solder resist layer 119 The bare copper surface in the open area is the pad 118.
第一晶片13收容於收容凹槽112中。第一晶片13具有相對的主動面131及非主動面133。所述主動面131上具有多個電極墊134。多個電極墊134中的每個電極墊134均與第一導電線路圖形113電性相連。The first wafer 13 is received in the receiving recess 112. The first wafer 13 has opposing active faces 131 and inactive faces 133. The active surface 131 has a plurality of electrode pads 134 thereon. Each of the plurality of electrode pads 134 is electrically connected to the first conductive line pattern 113.
電路載板10可以通過以下方法製成:首先,提供所述電路基板11及第一晶片13;其次,將第一晶片13放於收容凹槽112中,使得第一晶片13的主動面131較非主動面133靠近多個第一電性接觸墊116;採用半加成法在第一表面111a及多個電極墊134上形成第一導電線路圖形113,在第二表面111b上形成第二導電線路圖形115,並電連接第一導電線路圖形113與第一內層導電線路圖形11a,電連接第二導電線路圖形115與第二內層導電線路圖形11b;在所述第一導電線路圖形113及其間隙形成第一防焊層117,在第二導電線路圖形115及其間隙形成第二防焊層119,並於第一防焊層117及第二防焊層119形成有多個開口區,以定義所述第一防焊層117的開口區中裸露的銅面為第一電性接觸墊116,及所述第二防焊層119的開口區中裸露的銅面為焊墊118。如此,即可獲得電路載板10。The circuit carrier 10 can be fabricated by first providing the circuit substrate 11 and the first wafer 13; secondly, placing the first wafer 13 in the receiving recess 112 such that the active surface 131 of the first wafer 13 is The inactive surface 133 is adjacent to the plurality of first electrical contact pads 116; the first conductive line pattern 113 is formed on the first surface 111a and the plurality of electrode pads 134 by a semi-additive method, and the second conductive layer is formed on the second surface 111b. a line pattern 115 electrically connecting the first conductive line pattern 113 and the first inner layer conductive line pattern 11a, electrically connecting the second conductive line pattern 115 and the second inner layer conductive line pattern 11b; and the first conductive line pattern 113 A first solder resist layer 117 is formed in the gap, a second solder resist layer 119 is formed on the second conductive trace pattern 115 and the gap thereof, and a plurality of open regions are formed in the first solder resist layer 117 and the second solder resist layer 119. The bare copper surface in the open area of the first solder resist layer 117 is defined as the first electrical contact pad 116, and the bare copper surface in the open area of the second solder resist layer 119 is the solder pad 118. In this way, the circuit carrier board 10 can be obtained.
第二步,請參閱圖3,提供一個中介板20。所述中介板20的面積大於收容凹槽112在第一表面111a上的投影的面積,其具有相對的底面201及頂面203。所述中介板20的材料為玻璃,其具有暴露出的多個第一電性連接墊21及多個第二電性連接墊23。所述多個第一電性連接墊21位於中介板20底面201一側,所述多個第二電性連接墊23位於中介板20頂面203一側,且多個第一電性連接墊21中的至少一個第一電性連接墊21通過中介板20中的導電孔25與多個第二電性連接墊23中的至少一個第二電性連接墊23電性相連。本實施例中,多個第一電性連接墊21的數量與多個第一電性接觸墊116的數量相同,且多個第一電性連接墊21的數量小於多個第二電性連接墊23的數量。In the second step, referring to FIG. 3, an interposer 20 is provided. The area of the interposer 20 is larger than the projected area of the receiving recess 112 on the first surface 111a, and has an opposite bottom surface 201 and a top surface 203. The material of the interposer 20 is glass, which has a plurality of exposed first electrical connection pads 21 and a plurality of second electrical connection pads 23. The plurality of first electrical connection pads 21 are located on the side of the bottom surface 201 of the interposer 20, and the plurality of second electrical connection pads 23 are located on the top surface 203 of the interposer 20, and the plurality of first electrical connection pads The at least one first electrical connection pad 21 of the 21 is electrically connected to the at least one second electrical connection pad 23 of the plurality of second electrical connection pads 23 through the conductive holes 25 in the interposer 20 . In this embodiment, the number of the plurality of first electrical connection pads 21 is the same as the number of the plurality of first electrical contact pads 116, and the number of the plurality of first electrical connection pads 21 is less than the plurality of second electrical connections. The number of pads 23.
將中介板20構裝於電路載板10上,使得中介板20的多個第一電性連接墊21中的每個第一電性連接墊21均通過一個第一導電構件26一個第一電性接觸墊116電性相連。所述第一導電構件26可以為焊球,也可以為凸塊。本實施方式中,所述第一導電構件26為焊球。The interposer 20 is mounted on the circuit carrier 10 such that each of the plurality of first electrical connection pads 21 of the interposer 20 passes through a first conductive member 26 and has a first The contact pads 116 are electrically connected. The first conductive member 26 may be a solder ball or a bump. In the embodiment, the first conductive member 26 is a solder ball.
第三步,請參閱圖4,提供一個第二晶片30。第二晶片30具有相對的主動面301及非主動面303。所述主動面301上具有暴露出的多個電極墊31。In the third step, referring to FIG. 4, a second wafer 30 is provided. The second wafer 30 has opposing active faces 301 and inactive faces 303. The active surface 301 has a plurality of exposed electrode pads 31 thereon.
將所述第二晶片30構裝在中介板20遠離電路載板10的一側。本實施例中,第二晶片30通過覆晶封裝的方式構裝於中介板20,且第二晶片30的多個電極墊31中的每個電極墊31均一個第二導電構件33與一個第二電性連接墊23電性相連。所述第二導電構件33可以為焊球,也可以為凸塊。本實施方式中,所述第二導電構件33為焊球。The second wafer 30 is mounted on the side of the interposer 20 remote from the circuit carrier 10. In this embodiment, the second wafer 30 is mounted on the interposer 20 by flip chip packaging, and each of the plurality of electrode pads 31 of the second wafer 30 is provided with a second conductive member 33 and a first The two electrical connection pads 23 are electrically connected. The second conductive member 33 may be a solder ball or a bump. In the embodiment, the second conductive member 33 is a solder ball.
第四步,請參閱圖5,在中介板20遠離電路載板10的一側設置一個封裝膠體40。所述封裝膠體覆蓋第二晶片30、中介板20及從中介板20露出的電路載板10的第一表面111a,以保護第二晶片30及中介板20免受損害。所述封裝膠體40的材料為環氧模塑膠(epoxy molding compound)。In the fourth step, referring to FIG. 5, an encapsulant 40 is disposed on the side of the interposer 20 remote from the circuit carrier 10. The encapsulant covers the second wafer 30, the interposer 20, and the first surface 111a of the circuit carrier 10 exposed from the interposer 20 to protect the second wafer 30 and the interposer 20 from damage. The material of the encapsulant 40 is an epoxy molding compound.
第五步,請參閱圖6,通過印刷塗布的方法在該多個焊墊118中的每個焊墊118上均植一個焊球50。焊球50的材料一般主要包括錫。本實施例中,所述焊球50的直徑大於所述第一導電構件26的直徑,所述第一導電構件26的直徑大於第二導電構件33的直徑。當然,焊球50亦可通過其他植球方法形成,如噴印焊膏植球、鐳射植球等,並不以本實施例為限。如此,即可獲得具有第一晶片12及中介板20的半導體器件100。In the fifth step, referring to FIG. 6, a solder ball 50 is implanted on each of the plurality of pads 118 by a printing coating method. The material of the solder ball 50 generally includes mainly tin. In this embodiment, the diameter of the solder ball 50 is larger than the diameter of the first conductive member 26, and the diameter of the first conductive member 26 is larger than the diameter of the second conductive member 33. Of course, the solder ball 50 can also be formed by other ball-planting methods, such as spray solder paste ball, laser ball-planting, etc., and is not limited to this embodiment. Thus, the semiconductor device 100 having the first wafer 12 and the interposer 20 can be obtained.
本技術方案中的半導體器件100的製作方法中,電路載板10中的第一晶片13直接構裝於電路基板11上,而後再將中介板20構裝於電路載板10上,如此,第一晶片13與電路基板11之間的電性連接性能較高,進而可以避免先將第一晶片13構裝於中介板20上,再將中介板20構裝於電路基板11時所產生的電性不佳狀況的缺失,提高了半導體器件的生產效率,降低了半導體器件的製造成本。另外,第一晶片13收容於收容凹槽112中,降低了半導體器件的整體厚度,符合市場產品輕薄化和低成本的需求。In the manufacturing method of the semiconductor device 100 in the present technical solution, the first wafer 13 in the circuit carrier 10 is directly mounted on the circuit substrate 11, and then the interposer 20 is mounted on the circuit carrier 10, so that The electrical connection between the wafer 13 and the circuit substrate 11 is high, and the electricity generated when the first wafer 13 is first mounted on the interposer 20 and the interposer 20 is mounted on the circuit substrate 11 can be avoided. The lack of sexual conditions improves the production efficiency of semiconductor devices and reduces the manufacturing cost of semiconductor devices. In addition, the first wafer 13 is received in the receiving recess 112, which reduces the overall thickness of the semiconductor device and meets the requirements of light weight and low cost of the market products.
綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
10...電路載板10. . . Circuit carrier
118...焊墊118. . . Solder pad
20...中介板20. . . Intermediary board
30...第二晶片30. . . Second chip
40...封裝膠體40. . . Encapsulant
50...焊球50. . . Solder ball
100...半導體器件100. . . Semiconductor device
Claims (8)
提供一個電路載板,所述電路載板包括一個形成有導電線路的電路基板及一個第一晶片,所述電路基板具有暴露出的多個第一電性接觸墊,所述第一晶片具有相對的主動面及非主動面,所述第一晶片埋入所述電路基板,與所述電路基板中的導電線路電性相連,且所述主動面較所述非主動面靠近所述多個第一電性接觸墊;
提供一個中介板,所述中介板具有暴露出的多個第一電性連接墊,並將所述中介板構裝於所述電路載板上,使得所述中介板的多個第一電性連接墊中的每個第一電性連接墊均通過一個第一導電構件與一個第一電性接觸墊電性相連;及
提供一個第二晶片,並將所述第二晶片構裝在所述中介板遠離所述電路載板的一側,使得所述第二晶片通過所述中介板與所述電路載板電性相連。A method of fabricating a semiconductor device, comprising the steps of:
Providing a circuit carrier, the circuit carrier comprising a circuit substrate formed with a conductive line and a first wafer, the circuit substrate having a plurality of exposed first electrical contact pads, the first wafer having a relative The active surface and the inactive surface, the first wafer is embedded in the circuit substrate, electrically connected to the conductive line in the circuit substrate, and the active surface is closer to the plurality of the active surface than the active surface An electrical contact pad;
Providing an interposer having a plurality of exposed first electrical connection pads and mounting the interposer on the circuit carrier board such that the plurality of first electrical properties of the interposer Each of the first electrical connection pads in the connection pad is electrically connected to a first electrical contact pad through a first conductive member; and a second wafer is provided, and the second wafer is mounted on the The interposer is remote from a side of the circuit carrier such that the second wafer is electrically connected to the circuit carrier through the interposer.
The method of fabricating a semiconductor device according to claim 1, wherein the first conductive member is a bump.
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CN113013152A (en) * | 2019-12-18 | 2021-06-22 | 台达电子企业管理(上海)有限公司 | Substrate, manufacturing method applicable to substrate and power module |
US11610844B2 (en) | 2017-10-11 | 2023-03-21 | Octavo Systems Llc | High performance module for SiP |
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US7648911B2 (en) * | 2008-05-27 | 2010-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias |
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US11610844B2 (en) | 2017-10-11 | 2023-03-21 | Octavo Systems Llc | High performance module for SiP |
CN113013152A (en) * | 2019-12-18 | 2021-06-22 | 台达电子企业管理(上海)有限公司 | Substrate, manufacturing method applicable to substrate and power module |
US11901114B2 (en) | 2019-12-18 | 2024-02-13 | Delta Electronics (Shanghai) Co., Ltd. | Substrate, manufacturing method, and power module with same |
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