TWI407542B - Substrate having semiconductor chip embedded therein and fabrication method thereof - Google Patents

Abstract

The invention provides a package substrate having a semiconductor chip embedded therein and a method of fabricating the same, comprising providing a core board having a first surface and a second surface, wherein an opening is formed penetrating through the core board; forming a first dielectric layer with an opening on the second surface of the core board; compressing a metal layer on the first dielectric layer at positions not connecting the second surface, wherein the metal layer comprises a rough surface and a non-rough surface and the rough surface is compressed on the first dielectric layer so as to expose the rough surface from the opening of the core board and that of the dielectric layer; mounting a semiconductor chip on an adhesive layer disposed on the rough surface, thereby preventing deviation of the chip in the subsequent processes of building up the layers that would otherwise affect precision of alignment.

Description

Circuit board embedded with semiconductor components and method of manufacturing same

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board embedding a semiconductor component and a method of fabricating the same.

With the vigorous development of the electronics industry, electronic products are also developing in the direction of light, thin, short, small, high accumulation and multi-functionality. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, the package shape of semiconductor wafers is gradually encapsulated by single-chip ball grid array (BGA) or flip chip (FC) package. It has evolved into a modular package form, and the package structure has various forms such as SIP (System Integrated Package) and SiB (System in Board).

However, the modular package forms are flip chip or wire bonding, and a single semiconductor chip is electrically connected to the package substrate, or is adhered to the substrate by surface mount technology (SMT). The surface of the semiconductor wafer is disposed on the substrate, which is disadvantageous for the size reduction of the modular structure and the improvement of performance.

For this reason, the industry has proposed a method of embedding a semiconductor element in a substrate; please refer to the schematic diagram of a conventional substrate for embedding a semiconductor element as shown in FIGS. 1A to 1D.

As shown in FIG. 1A, a first carrier 11 is disposed, and a second carrier 12 is disposed on the first carrier 11, and the second carrier 12 has an opposite first surface 12a and a second surface. 12b, and forming at least one through the first surface 12a and the second surface in the second carrier 12 The opening 120 of the second carrier 12 is joined to the first carrier 11 and encloses one end of the opening 120 of the second carrier 12 .

As shown in FIG. 1B, a semiconductor wafer 13 is provided. The semiconductor wafer 13 has an opposite active surface 13a and a non-active surface 13b. The active surface 13a has a plurality of electrode pads 131, and is adhered by an adhesive layer 14. The non-active surface 13b of the semiconductor wafer 13 is placed on the first carrier 11 in the opening 120 of the second carrier 12.

As shown in FIG. 1C, a dielectric layer 15 is formed on the active surface 13a of the second carrier 12 and the semiconductor wafer 13, and the dielectric layer 15 is filled in the opening 120 of the second carrier 12 and the semiconductor. In the gap between the wafers 13 , the semiconductor wafer 13 is fixed in the opening 120; however, when the dielectric layer 15 is hot pressed, the semiconductor wafer 13 is liable to be biased in the opening 120 due to uneven pressure. Shift e.

As shown in FIG. 1D, a wiring layer 16 is formed on the dielectric layer 15, and a plurality of conductive vias 161 are formed in the dielectric layer 15 to electrically connect the electrode pads 131 of the semiconductor wafer 13; When the dielectric layer 15 is formed by hot pressing, the semiconductor wafer 13 is offset by e, which causes the conductive blind via 161 to be connected to the electrode pad 131, and the electrode pad 131 cannot be electrically connected even if the deviation is too large.

As can be seen from the above, the semiconductor wafer 13 is placed on the first carrier 11 in the opening 120 of the second carrier 12 by the adhesive layer 14 to form the dielectric layer 15 and fill the semiconductor wafer 13 and When the gap between the openings 120 of the second carrier 12 is still placed in the opening The semiconductor wafer 13 in 120 is offset; therefore, the semiconductor wafer 13 is offset in the opening 120, causing the conductive blind via 161 to be connected to the alignment offset of the electrode pad 131, and even being electrically disconnected due to excessive deviation The electrode pad 131, in turn, affects the reliability of the electrical connection.

Therefore, how to propose a circuit board embedded with a semiconductor component to avoid the offset of the semiconductor component housed in the opening of the core board in the conventional circuit board embedding process has become an urgent problem to be overcome in the industry.

In view of the above-mentioned various deficiencies of the prior art, it is a primary object of the present invention to provide a circuit board in which a semiconductor element is embedded and a method of fabricating the same, which can effectively fix a semiconductor wafer in an opening of a core board to avoid offset.

In order to achieve the above, the present invention provides a circuit board embedded with a semiconductor component, comprising: a core plate having a first surface and a corresponding second surface, and having at least one through the first surface and the second a core plate opening of the surface; a first dielectric layer is formed on the second surface of the core plate, the first dielectric layer has a dielectric layer opening corresponding to the opening of the core plate; and the metal layer is pressed against the first layer a dielectric layer is not attached to the surface of the second surface, the metal layer has a roughened surface and a non-roughened surface, and the roughened surface is pressed onto the first dielectric layer to make the metal layer The roughened surface is exposed in the opening of the core plate and the opening of the dielectric layer; the adhesive layer is disposed on the roughened surface of the opening of the core plate and the opening of the dielectric layer; and the semiconductor wafer is attached to the adhesive layer on.

According to the above circuit board embedding a semiconductor component, the core board is an insulating board or a circuit board having a line; the metal layer is a copper foil; the semiconductor The body wafer has an opposite active surface and an inactive surface, and the active surface has an electrode pad, and the non-active surface is adhered to the roughened surface of the core plate opening and the dielectric layer opening by an adhesive layer.

According to the above structure, the first surface of the core board and the active surface of the semiconductor wafer are formed with a build-up structure, and the build-up structure includes at least one second dielectric layer disposed on the second dielectric layer. a circuit layer, and a conductive via hole disposed in the second dielectric layer, the conductive via hole is electrically connected to the circuit layer and the electrode pad of the semiconductor chip, and has electricity in the outermost circuit layer of the layered structure The contact pad is covered with a solder resist layer on the outermost layer of the build-up structure, and the solder resist layer has a plurality of openings to correspondingly expose the respective electrical contact pads.

According to the above, the second dielectric layer fills the gap between the semiconductor wafer and the core plate opening, and the gap between the semiconductor wafer and the dielectric layer opening.

The present invention provides a circuit board manufacturing method for embedding a semiconductor device, comprising: providing a core board having a first surface and a corresponding second surface, and having at least one through the first surface and the first a core plate opening of the two surfaces; a first dielectric layer is formed on the second surface, and the first dielectric layer has a dielectric layer opening to correspond to the core plate opening; and the first dielectric layer is not connected Pressing a metal layer on the surface of the second surface, the metal layer having a roughened surface and a non-roughened surface, and pressing the roughened surface on the first dielectric layer to roughen the metal layer The surface is exposed in the opening of the core plate and the opening of the dielectric layer; an adhesive layer is formed on the roughened surface of the opening of the core plate and the opening of the dielectric layer; and the semiconductor wafer is bonded to the adhesive layer.

According to the circuit board manufacturing method for embedding a semiconductor device, the core board is an insulating board or a circuit board having a line; the metal layer is a copper foil; the semiconductor wafer has a relative active surface and a non-active surface. The surface has an electrode pad and is placed on the adhesive layer with an inactive surface.

According to the above method, the first surface of the core board and the active surface of the semiconductor wafer are formed with a build-up structure, and the build-up structure includes at least one second dielectric layer formed on the second dielectric layer. a circuit layer, and a conductive via hole formed in the second dielectric layer, the conductive via hole is electrically connected to the circuit layer and the electrode pad of the semiconductor wafer, and the outermost circuit layer of the buildup structure is formed A plurality of electrical contact pads are formed, and a solder resist layer is formed on an outermost layer of the build-up structure, and a plurality of openings are formed in the solder resist layer to correspondingly expose the respective electrical contact pads.

According to the above, the second dielectric layer fills the gap between the semiconductor wafer and the core plate opening, and the gap between the semiconductor wafer and the dielectric layer opening.

A circuit board embedding a semiconductor device according to the present invention, and a method for manufacturing a first dielectric layer and a metal layer having a dielectric layer opening on a second surface of a core plate having a core plate opening, wherein the metal layer is thick The surface of the semiconductor wafer is bonded to the first dielectric layer, and the non-active surface of the semiconductor wafer is bonded to the roughened surface by an adhesive layer, and the roughened surface is used to improve the between the semiconductor wafer and the metal layer. The bonding is avoided to avoid the problem that the semiconductor wafer is offset in the subsequent formation of the build-up structure, so that the conductive blind holes in the wiring layer of the build-up structure can be electrically connected to the electrode pads of the semiconductor wafer to avoid generation. Poor electrical connection, and can improve the reliability of electrical connection degree.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure herein.

2A to 2F are cross-sectional views showing a circuit board in which a semiconductor element is embedded in the present invention and a method of manufacturing the same.

As shown in FIG. 2A, firstly, a core board 20 having a corresponding first surface 20a and a second surface 20b is provided, and the core board 20 is an insulating board or a circuit board having a line, and has at least one through The core plate opening 200 of the first surface 20a and the second surface 20b.

As shown in FIG. 2B, a first dielectric layer 21 is formed on the second surface 20b of the core board 20, and the first dielectric layer 21 has a dielectric layer opening 210 corresponding to the core board opening 200.

As shown in FIG. 2C, a metal layer 22 is press-bonded on the surface of the first dielectric layer 21 where the second surface 20b is not connected, and the metal layer 22 has a roughened surface 22a and a non-roughened surface 22b. And the roughened surface 22a is pressed onto the first dielectric layer 21, and the roughened surface 22a of the metal layer 22 is exposed in the core plate opening 200 and the dielectric layer opening 210; wherein the metal layer 22 It is made of copper foil.

As shown in FIG. 2D, a semiconductor wafer 24 is bonded to the roughened surface 22a of the metal layer 22 in the core plate opening 200 and the dielectric layer opening 210. The semiconductor wafer 24 has an active surface 24a and The non-acting surface 24b corresponding thereto has a plurality of electrode pads on the active surface 24a 241.

As shown in FIG. 2E, a first layer 20a of the core board 20 and an active surface 24a of the semiconductor wafer 24 are formed with a build-up structure 25, and the build-up structure 25 includes at least one second dielectric layer 251. a circuit layer 252 on the second dielectric layer 251, and a conductive via 253 formed in the second dielectric layer 251. The conductive via 253 is electrically connected to the circuit layer 252 and the electrode of the semiconductor wafer 24. The pad 241 is further formed with an electrical contact pad 254 on the outermost circuit layer 252 of the build-up structure 25, and a solder resist layer 26 is formed on the outermost layer of the build-up structure 25, and the solder resist layer 26 is formed with A plurality of openings 260 are formed to correspondingly expose the respective electrical contact pads 254; the second dielectric layer 251 is filled in the gap between the semiconductor wafer 24 and the core plate opening 200, and between the semiconductor wafer 24 and the dielectric layer opening 210. The semiconductor wafer 24 is fixed in the core plate opening 200 and the dielectric layer opening 210.

The present invention provides a circuit board embedded with a semiconductor component, comprising: a core plate 20 having a first surface 20a and a corresponding second surface 20b, and having at least one through the first surface 20a and the second surface a core plate opening 200 of 20b; a first dielectric layer 21 is formed on the second surface 20b of the core plate 20, the first dielectric layer 21 has a dielectric layer opening 210 corresponding to the core plate opening 200; a metal layer 22, press-bonded to the surface of the first dielectric layer 21 not connected to the second surface 20b, the metal layer 22 having a roughened surface 22a and a non-roughened surface 22b, and pressed by the roughened surface 22a On the first dielectric layer 21, the roughened surface 22a of the metal layer 22 is exposed in the core plate opening 200 and the dielectric layer opening 210; the adhesive layer 23, which is disposed on the roughened surface 22a of the core plate opening 200 and the dielectric layer opening 210; and the semiconductor wafer 24 is attached to the adhesive layer 23.

According to the circuit board embedded with the semiconductor component, the core board 20 is an insulating board or a circuit board having a line; the metal layer 22 is a copper foil; the semiconductor wafer 24 has an opposite active surface 24a and an inactive surface 24b. The active surface 24a has an electrode pad 241, and is attached to the roughened surface 22a by an inactive surface 24b.

Further, according to the above configuration, the adhesive layer 23 is formed to be formed between the non-active surface 24b of the semiconductor wafer 24 and the roughened surface 22a.

According to the above structure, the first surface 20a of the core board 20 and the active surface 24a of the semiconductor wafer 24 are formed with a build-up structure 25, and the build-up structure 25 includes at least one second dielectric layer 251. a circuit layer 252 on the second dielectric layer 251, and a conductive via 253 disposed in the second dielectric layer 251. The conductive via 253 is electrically connected to the circuit layer 252 and the electrode of the semiconductor wafer 24. The pad 241 has an electrical contact pad 254 on the outermost circuit layer 252 of the build-up structure 25, and a solder resist layer 26 is disposed on the outermost layer of the build-up structure 25, and the solder resist layer 26 has a plurality of openings. a hole 260 correspondingly exposing each of the electrical contact pads 254; the second dielectric layer 251 is filled between the semiconductor wafer 24 and the core plate opening 200, and between the semiconductor wafer 24 and the dielectric layer opening 210 In the gap.

In summary, the circuit board with embedded semiconductor components of the present invention and the method for fabricating the same are formed on the second surface of the core plate having the opening of the core plate. a first dielectric layer and a metal layer of the electrical layer, wherein the metal layer is pressed onto the first dielectric layer with a roughened surface, and the non-active surface of the semiconductor wafer is bonded to the thick layer by an adhesive layer The roughening surface is used to improve the bonding between the semiconductor wafer and the metal layer to avoid the problem that the semiconductor wafer is offset in the subsequent formation of the build-up structure, thereby making the line of the build-up structure The conductive blind holes in the layer can accurately electrically connect the electrode pads of the semiconductor wafer to avoid the occurrence of electrical connection failure, and can improve the reliability of the electrical connection.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

11‧‧‧First carrier board

12‧‧‧Second carrier board

120‧‧‧ openings

12a, 20a‧‧‧ first surface

12b, 20b‧‧‧ second surface

13, 24‧‧‧ semiconductor wafer

13a, 24a‧‧‧ action surface

13b, 24b‧‧‧ non-active surface

131, 241‧‧ ‧ electrode pads

14, 23‧‧‧ adhesive layer

15‧‧‧Dielectric layer

16, 252‧‧‧ circuit layer

161, 253‧‧ ‧ conductive blind holes

20‧‧‧ core board

200‧‧‧ core plate opening

21‧‧‧First dielectric layer

210‧‧‧Dielectric layer opening

22‧‧‧metal layer

22a‧‧‧ roughened surface

22b‧‧‧non-roughened surface

25‧‧‧Additional structure

251‧‧‧Second dielectric layer

254‧‧‧Electrical contact pads

26‧‧‧ solder mask

260‧‧‧ openings

e‧‧‧Offset difference

1A to 1D are schematic cross-sectional views showing a method of manufacturing a conventional core circuit board; and Figs. 2A to 2E are schematic cross-sectional views showing a circuit board in which a semiconductor element is embedded and a method of manufacturing the same.

20‧‧‧ core board

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧ core plate opening

24‧‧‧Semiconductor wafer

24a‧‧‧Action surface

24b‧‧‧Non-active surface

241‧‧‧electrode pads

21‧‧‧First dielectric layer

210‧‧‧Dielectric layer opening

22‧‧‧metal layer

22a‧‧‧ roughened surface

23‧‧‧Adhesive layer

Claims (14)

A circuit board embedded with a semiconductor component, comprising: a core plate having a first surface and a corresponding second surface, and having at least one core plate opening extending through the first surface and the second surface; An electrical layer is formed on the second surface of the core board, the first dielectric layer has a dielectric layer opening corresponding to the opening of the core board; and the metal layer is press-bonded to the first dielectric layer On the surface of the two surfaces, the metal layer has a roughened surface and a non-roughened surface, and the roughened surface is pressed onto the first dielectric layer, so that the roughened surface of the metal layer is exposed to the core plate opening. And the dielectric layer opening; the adhesive layer is disposed on the roughened surface of the core plate opening and the dielectric layer opening; and the semiconductor wafer is attached to the adhesive layer. The circuit board of the embedded semiconductor component of claim 1, wherein the core board is an insulating board or a circuit board having a line. A circuit board for embedding a semiconductor device according to claim 1, wherein the metal layer is a copper foil. The circuit board of the embedded semiconductor device of claim 1, wherein the semiconductor wafer has an opposite active surface and an inactive surface, and the active surface has an electrode pad, and the non-active surface is adhered to the active layer. The core plate opening and the roughened surface in the opening of the dielectric layer. A circuit board for embedding a semiconductor device according to item 4 of the patent application, The first surface of the core board and the active surface of the semiconductor wafer are formed with a build-up structure. The circuit board of the embedded semiconductor device of claim 5, wherein the build-up structure comprises at least a second dielectric layer, a circuit layer disposed on the second dielectric layer, and a conductive via hole in the two dielectric layers, the conductive blind via is electrically connected to the electrode layer of the circuit layer and the semiconductor wafer, and has an electrical contact pad on the outermost circuit layer of the buildup structure, and the build-up layer is The outermost layer of the structure is covered with a solder resist layer, and the solder resist layer has a plurality of openings to correspondingly expose the respective electrical contact pads. The circuit board of the embedded semiconductor device of claim 6, wherein the second dielectric layer fills a gap between the semiconductor wafer and the core plate opening, and between the semiconductor wafer and the dielectric layer opening In the gap. A circuit board manufacturing method for embedding a semiconductor component, comprising: providing a core board having a first surface and a corresponding second surface, and having at least one core penetrating the first surface and the second surface a first dielectric layer is formed on the second surface, and the first dielectric layer has a dielectric layer opening to correspond to the opening of the core plate; the second surface is not connected to the first dielectric layer Pressing a metal layer on the surface thereof, the metal layer having a roughened surface and a non-roughened surface, and pressing the roughened surface on the first dielectric layer to expose the roughened surface of the metal layer The core plate opening and the dielectric layer opening; An adhesive layer is formed on the roughened surface of the core plate opening and the dielectric layer opening; and the semiconductor wafer is bonded to the adhesive layer. The method of manufacturing a circuit board for embedding a semiconductor device according to claim 8, wherein the core board is an insulating board or a circuit board having a line. The method of manufacturing a circuit board for embedding a semiconductor device according to claim 8, wherein the metal layer is a copper foil. The method of manufacturing a circuit board for embedding a semiconductor device according to claim 8, wherein the semiconductor wafer has an opposite active surface and an inactive surface, and the active surface has an electrode pad, and the non-active surface is attached to the adhesive layer. on. The circuit board manufacturing method for embedding a semiconductor device according to claim 10, wherein the first surface of the core plate and the active surface of the semiconductor wafer are formed with a build-up structure. The method of manufacturing a circuit board for embedding a semiconductor device according to claim 12, wherein the build-up structure comprises at least a second dielectric layer, a circuit layer formed on the second dielectric layer, and a layer formed thereon a conductive via hole in the second dielectric layer, the conductive via hole is electrically connected to the circuit layer and the electrode pad of the semiconductor wafer, and a plurality of electrical contact pads are formed on the outermost circuit layer of the buildup structure, and The outermost layer of the buildup structure is formed with a solder resist layer, and a plurality of openings are formed in the solder resist layer to correspondingly expose the respective electrical contact pads. The method of manufacturing a circuit board for embedding a semiconductor device according to claim 13, wherein the second dielectric layer fills the semiconductor wafer and the core A gap between the opening of the core plate and a gap between the semiconductor wafer and the opening of the dielectric layer.