TW201410089A - Package on package structure and method for manufacturing same - Google Patents

Abstract

The present disclosure relates to a method for manufacturing a package on package structure. The method includes the following steps. First, a connection substrate is provided. The connection substrate defines a plurality of plating through holes. Solder paste is printed on each end of the two ends of each plating through hole. Second, a first package device is arranged on one side of the connection substrate, and a second package device is arranged on the other side of the connection substrate, thereby obtaining a stack structure. Third, solder paste are cured to make the first package device and the second package device soldered at the two opposite sides of the connection substrate, respectively. A package on package structure is thus obtained. The present disclosure also relates to a package on package structure manufactured by the above method.

Description

Cascading package structure and manufacturing method thereof

The present invention relates to a semiconductor package technology, and more particularly to a package-on-package (POP) structure and a method of fabricating the same.

As the size of semiconductor devices continues to decrease, laminated package structures having semiconductor devices are also receiving increasing attention. The package structure is generally made by a laminate manufacturing method. In the conventional laminate manufacturing method, in order to achieve high-density integration and small-area mounting, the upper and lower package devices are usually electrically connected by solder balls. However, the solder balls are prone to cracks, thus reducing the yield and reliability of the package package structure.

The invention provides a highly reliable laminated package structure and a manufacturing method thereof.

A method for fabricating a package structure includes the steps of: providing a connection substrate, wherein the connection substrate has opposite first and second surfaces, and the connection substrate is provided with a plurality of first conductive holes, each of the first conductive a hole is formed through the first surface and the second surface, and solder paste is printed on both ends of each of the first conductive holes; a first package device is disposed on a side of the first surface of the connection substrate, Forming a second package device on a side of the second surface of the connection substrate to form a stacked structure, the first package device comprising a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier The first circuit carrier has a plurality of exposed first pads, the plurality of first pads are in one-to-one correspondence with the plurality of first conductive holes, and each of the first pads is adjacent to the corresponding one a solder paste at one end of the first conductive via, the second package device includes a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier, the second circuit carrier having an exposed Multiple fifth pads, a plurality of fifth pads are also in one-to-one correspondence with the plurality of first conductive vias, and each of the fifth pads is adjacent to the solder paste at the other end of the corresponding first conductive via; and curing each of the first conductive a solder paste at both ends of the hole, such that each of the first pads is soldered to one end of a corresponding one of the first conductive holes by a cured solder paste, and each of the fifth pads is soldered to a first one corresponding thereto by the cured solder paste The other end of the conductive hole is such that the first packaged device and the second packaged device are soldered to opposite sides of the connection substrate, respectively, to form a stacked package structure.

A method for fabricating a package structure includes the steps of: providing a connection substrate, the connection substrate having opposite first and second surfaces, wherein the connection substrate is provided with a plurality of first conductive holes and a plurality of second conductive Each of the first conductive holes and each of the second conductive holes penetrates the first surface and the second surface, and each of the first conductive holes and each of the second conductive holes are printed with a solder paste; A first package device is disposed on a side of the first surface of the connection substrate, and a second package device is disposed on a side of the second surface of the connection substrate to form a stacked structure, wherein the first package device includes a circuit carrier board and a first semiconductor wafer and a second semiconductor wafer mounted on the first circuit carrier, the first circuit carrier has a plurality of first pads and a plurality of second pads, The first pad and the plurality of second pads are exposed on the same side of the first circuit carrier, the plurality of first pads are electrically connected to the first semiconductor chip, and the plurality of first conductive holes One-to-one correspondence, each first pad is relied on a solder paste at one end of the first conductive via, the plurality of second pads electrically connected to the second semiconductor wafer, and one-to-one corresponding to the plurality of second conductive vias, each second solder The pads are all adjacent to the solder paste at one end of the corresponding second conductive via, the second package device comprising a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier, the second circuit carrier Having a plurality of fifth pads and a plurality of sixth pads, the plurality of fifth pads and the plurality of sixth pads being exposed on a same side of the second circuit carrier, the plurality of fifth pads The disk is in one-to-one correspondence with the plurality of first conductive holes, and each of the fifth pads is adjacent to the solder paste at the other end of the corresponding first conductive hole, the plurality of sixth pads and the plurality of The second conductive holes are in one-to-one correspondence, and each of the sixth pads is adjacent to the solder paste at the other end of the corresponding second conductive hole; and the solder paste at both ends of each of the first conductive holes and each of the second conductive holes are cured Solder paste at the end, such that each of the first pads is soldered to a corresponding one of the first conductive holes by the cured solder paste One end, each fifth pad is soldered to the other end of a corresponding one of the first conductive holes by the cured solder paste, and each of the second pads is soldered to a second conductive hole corresponding thereto by the cured solder paste One end of each of the sixth pads is soldered to the other end of a second conductive hole corresponding thereto by the cured solder paste, so that the first package device and the second package device are respectively soldered on opposite sides of the connection substrate to form A stacked package structure.

A stacked package structure includes a connection substrate, a first package device, and a second package device. The connection substrate has opposite first and second surfaces. A plurality of first conductive holes are disposed in the connection substrate. Each of the first conductive holes penetrates the first surface and the second surface and a solder paste is disposed at both ends of each of the first conductive holes. The first package device includes a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier. The first circuit carrier has a plurality of first pads, and the plurality of first pads are in one-to-one correspondence with the plurality of first conductive holes. Each of the first pads is soldered to one end of a corresponding one of the first conductive holes by solder paste, so that the first package device is soldered to the first surface side of the connection substrate. The second package device includes a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier. The second circuit carrier has a plurality of fifth pads. The plurality of fifth pads are also in one-to-one correspondence with the plurality of first conductive holes, and each of the fifth pads is soldered to the other end of the corresponding one of the first conductive holes by solder paste, so that the second The package device is soldered to one side of the second surface of the connection substrate.

A stacked package structure includes a connection substrate, a first package device, and a second package device. The connection substrate has opposite first and second surfaces. A plurality of first conductive holes and a plurality of second conductive holes are disposed in the connection substrate. Each of the first conductive holes and each of the second conductive holes penetrates the first surface and the second surface, and each of the first conductive holes and each of the second conductive holes are provided with solder paste. The first package device includes a first circuit carrier and a first semiconductor wafer and a second semiconductor wafer mounted on the first circuit carrier. The first circuit carrier has a plurality of first pads and a plurality of second pads. The plurality of first pads and the plurality of second pads are exposed on the same side of the first circuit carrier. The plurality of first pads are electrically connected to the first semiconductor wafer and are in one-to-one correspondence with the plurality of first conductive holes. The plurality of second pads are electrically connected to the second semiconductor wafer and are in one-to-one correspondence with the plurality of second conductive holes. Each of the first pads is soldered to one end of a corresponding one of the first conductive vias by solder paste. Each of the second pads is soldered to one end of a second conductive hole corresponding thereto by solder paste, so that the first package device is soldered to one side of the first surface of the connection substrate. The second package device includes a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier. The second circuit carrier has a plurality of fifth pads and a plurality of sixth pads. The plurality of fifth pads and the plurality of sixth pads are exposed on the same side of the second circuit carrier. The plurality of fifth pads are in one-to-one correspondence with the plurality of first conductive holes. The plurality of sixth pads are in one-to-one correspondence with the plurality of second conductive holes. Each of the fifth pads is soldered to the other end of a corresponding one of the first conductive vias by a solder paste, and each of the sixth pads is soldered to the other end of the corresponding one of the second conductive vias by a solder paste, thereby making the second The package device is soldered to one side of the second surface of the connection substrate.

In the stacked package structure formed by the above method, the first package device and the second package device are integrally connected through the connection substrate, and the connection substrate and the first package device and the connection substrate and the substrate The second package devices are connected by solder paste provided on the conductive holes in the connection substrate, and are not connected by solder balls, thereby improving the yield and reliability of the package structure. In addition, the above production method is not only simple in production process but also low in production cost.

The laminated package structure and the manufacturing method thereof provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.

The manufacturing method of the package package structure provided by the first embodiment of the present invention includes the following steps:

First step: Please refer to FIG. 1 to FIG. 6 together to provide a connection substrate 10. The connection substrate 10 has opposing first and second surfaces 10a, 10b. The connecting substrate 10 defines a receiving through hole 101 penetrating through the first surface 10a and the second surface 10b. The connecting substrate 10 further includes a plurality of first conductive holes 103 penetrating the first surface 10a and the second surface 10b and a plurality of second conductive holes 105 penetrating the first surface 10a and the second surface 10b. Each of the first conductive vias 103 is located between the plurality of second conductive vias 105 , and the plurality of first conductive vias 103 are located between the plurality of second conductive vias 105 and the receiving vias 101 . Each of the conductive holes 103 and 105 is filled with a plug resin 106, and each of the first conductive holes 103 is provided with a first conductive cap 107 at each end thereof, and each of the second conductive holes 105 is provided at both ends thereof. A second conductive cap 108. Each of the first conductive caps 107 covers and closes a corresponding first conductive via 103, and each of the second conductive caps 108 covers and closes a corresponding second conductive via 105 to enhance the corresponding conductive vias 103, 105 and subsequent steps. Electrical connection reliability between packaged devices. Solder paste 109 is printed on the surface of each of the conductive caps 107, 108 to connect and electrically conduct the connecting substrate 10 and the packaged device in the subsequent step.

In this embodiment, the connection substrate 10 can be formed by the following steps:

First, an insulating substrate 11 as shown in Fig. 1 is provided. The insulating substrate 11 includes the first surface 10a and the second surface 10b. The insulating substrate 11 may be made of a thermosetting resin such as a phenol resin, an epoxy resin or a polyimide, or may be made of a thermoplastic resin such as polyethylene, polypropylene or polyvinyl chloride, or may be made of glass or ceramic. The insulating substrate 11 has a thickness of 100 μm or less. In the present embodiment, the insulating base material 11 is made of polyimide and has a thickness of 80 μm.

Next, as shown in FIG. 2, the receiving through hole 101, the plurality of first through holes 103a, and the plurality of second through holes 105a are formed in the insulating base material 11 by a laser drilling process. Each of the through holes 101, 103a, and 105a penetrates the first surface 10a and the second surface 10b, and the plurality of first through holes 103a are located between the plurality of second through holes 105a and the receiving through holes 101. That is, the plurality of first through holes 103a surround the receiving through holes 101, and the plurality of second through holes 105a surround the plurality of first through holes 103a.

Moreover, referring to FIG. 3, the plurality of first through holes 103a are formed into a plurality of first conductive holes 103, and the plurality of second through holes 105a are formed into a plurality of second conductive holes 105. In this embodiment, a conductive metal layer, such as a copper layer, a silver layer or a gold layer, is formed on each of the plurality of first via holes 103a and the plurality of second via holes 105a by a plating process. A plurality of first conductive vias 103 and a plurality of second conductive vias 105 are obtained. Specifically, a chemical copper layer may be formed on each of the plurality of first through holes 103a and the plurality of second through holes 105a by chemical deposition, and then electroplated on the chemical copper layer. A layer of electroplated copper is formed, and the chemical copper layer and the electroplated copper layer form a conductive metal layer of each of the via holes. In this embodiment, each of the conductive holes includes a through hole portion between the first surface 10a and the second surface 10b, a first hole ring portion at the first surface 10a, and a second hole at the second surface 10b. The ring portion, that is, the conductive metal layer of each of the through hole walls also extends over the first surface 10a and the second surface 10b around the through hole.

Next, referring to FIG. 4, the plug hole resin 106 is filled in each of the plurality of first conductive vias 103 and the plurality of second conductive vias 105 by a resin filling process until the plug resin 106 is used in each of the openings. The first conductive vias 103 and each of the second conductive vias 105 are filled in.

Then, referring to FIG. 5, a first conductive cap 107 is formed on each end of each of the first conductive vias 103 by a plating process, and a second conductive cap 108 is formed on each of the two ends of each of the second conductive vias 105. . Each of the conductive caps covers and closes the corresponding conductive holes, and may be made of metal such as copper, silver or gold. In this embodiment, a chemical copper layer is separately formed on both ends of each conductive hole by chemical deposition, and an electroplated copper layer is formed on the chemical copper layer, and the chemical copper layer and the electroplated copper layer jointly form the conductive layer. cap. Specifically, the first conductive cap 107 is formed in the first conductive via 103, and the first conductive via 103 is located on the first surface of the first surface 10a and the first conductive via 103 is located on the second surface 10b. The surface of the second hole ring portion, the second hole cap 108 is formed in the second conductive hole 105, and the first hole ring portion of the first surface 10a is located at the first hole ring portion and the second conductive hole 105. The surface of the second bore ring portion of the two surfaces 10b. In this embodiment, the diameter of the first conductive cap 107 is larger than the diameter of the first through hole 103a and equal to the diameter of the ring portion of the first conductive hole 103; the diameter of the second conductive cap 108 is larger than the diameter of the second through hole 105a. And equal to the diameter of the ring portion of the second conductive hole 105. It will be understood by those skilled in the art that the first conductive via 103 and the second conductive via 105 can be formed in other manners as shown in the above embodiments. For example, the first through hole 103a and the second through hole 105a may be directly filled by a plating hole filling process to form the plurality of first through holes 103a into a plurality of first conductive holes 103, and the plurality of The two through holes 105a are formed as a plurality of second conductive holes 105. In this embodiment, the resin filling step and the step of forming the conductive cap may be omitted. For example, the conductive paste may be filled and cured in the first through hole 103a and the second through hole 105a to form the plurality of first through holes 103a into a plurality of first conductive holes 103, and a plurality of second The through hole 105a is formed as a plurality of second conductive holes 105. In this embodiment, the resin filling step and the step of forming the conductive cap may be omitted.

Finally, referring to FIG. 6, the solder paste 109 is printed on the surface of each of the first conductive caps 107 by a printing process, and the solder paste 109 is printed on the surface of each of the second conductive caps 108 to obtain the connecting substrate 10.

In the second step, referring to FIG. 7 and FIG. 8, a first package device 20 and a second package device 30 are provided. The first package device 20 includes a first circuit carrier 21, a first semiconductor wafer 22 mounted on the first circuit carrier 21, and a second semiconductor wafer mounted on the first semiconductor wafer 22. And a first encapsulant 24 disposed on the first circuit carrier 21 and covering the first semiconductor wafer 22 and the second semiconductor wafer 23.

The first circuit carrier 21 may be a single-sided circuit board, a double-sided circuit board or a multi-layer circuit board formed with a conductive line, and includes a first substrate 211, a first conductive pattern 212, a second conductive pattern 213, and a first solder resist. Layer 214 and second solder resist layer 215. The first substrate 211 has opposite lower side surfaces 211a and upper side surfaces 211b. The first conductive pattern 212 and the second conductive pattern 213 are respectively disposed on the lower side surface 211a and the upper side surface 211b, and are electrically connected to each other. In this embodiment, the first circuit carrier 21 is a double-sided circuit board, and the first conductive pattern 212 and the second conductive pattern 213 pass through the plurality of third conductive holes 216 and the plurality of fourth in the first circuit carrier 21 The conductive holes 217 are electrically connected.

The first conductive pattern 212 includes a plurality of first pads 2121, a plurality of second pads 2123, and a plurality of conductive lines 2125. Each of the first pads 2121 is located between the plurality of second pads 2123. That is, the plurality of second pads 2123 are disposed around the plurality of first pads 2121. The plurality of first pads 2121 are in one-to-one correspondence with the plurality of first conductive holes 103, and the plurality of second pads 2123 are in one-to-one correspondence with the plurality of second conductive holes 105.

The second conductive pattern 213 includes a plurality of third pads 2131, a plurality of fourth pads 2133, and a plurality of conductive lines 2135. Each of the third pads 2131 is located between the plurality of fourth pads 2133. That is, the plurality of fourth pads 2133 are disposed around the plurality of third pads 2131. A plurality of third pads 2131 are electrically connected to the first semiconductor wafer 22. That is, the first semiconductor wafer 22 is mounted on the first circuit carrier 21 by wire bonding, surface mounted technology or flip chip technology, and The plurality of third pads 2131 are electrically connected to be electrically connected to the first circuit carrier 21 . The plurality of third pads 2131 are in one-to-one correspondence with the plurality of first pads 2121, and each of the third pads 2131 is electrically connected to the first pad 2121 corresponding thereto through a third conductive via 216. A plurality of fourth pads 2133 are electrically connected to the second semiconductor wafer 23. That is, the second semiconductor wafer 23 is mounted on the first circuit carrier 21 by wire bonding technology, surface mount technology or flip chip packaging technology, and is electrically connected to the plurality of fourth pads 2133, thereby A circuit carrier 21 is electrically connected. The plurality of fourth pads 2133 are in one-to-one correspondence with the plurality of second pads 2123, and each of the fourth pads 2133 is electrically connected to the second pad 2123 corresponding thereto through a fourth conductive via 217. In this embodiment, the first semiconductor wafer 22 is electrically connected to the first circuit carrier 21 by a wire bonding technique, and the second semiconductor wafer 23 is electrically connected to the first circuit carrier 21 by a wire bonding technique.

The first solder resist layer 214 covers at least a portion of the first conductive pattern 212 and an underside surface 211a exposed from the first conductive pattern 212. The second solder resist layer 215 covers at least a portion of the second conductive pattern 213 and an upper side surface 211b exposed from the second conductive pattern 213. The first solder resist layer 214 is used to cover the plurality of conductive lines 2125 in the first conductive pattern 212. Each of the plurality of first pads 2121 and the plurality of second pads 2123 exposes at least a portion from the first solder resist layer 214. The second solder resist layer 215 is used to cover the plurality of conductive lines 2135 in the second conductive pattern 213. Each of the plurality of third pads 2131 and the plurality of fourth pads 2133 exposes at least a portion from the second solder resist layer 215.

The first semiconductor wafer 22 can include a memory wafer, a logic wafer, or a digital wafer. In this embodiment, the first semiconductor wafer 22 is a logic wafer that is mounted on the first circuit carrier 21 by a wire bonding technique. The first semiconductor wafer 22 is adhered to the second solder resist layer 215 of the first circuit carrier 21 by the first insulating paste 25 away from the surface of the first substrate 211. The first semiconductor wafer 22 has a plurality of first electrical connection pads 221 that are in one-to-one correspondence with the plurality of third pads 2131. Each of the first electrical connection pads 221 is electrically connected to a corresponding third pad 2131 by a first wire 222 such as a gold wire.

The second semiconductor wafer 23 may be a wafer such as a memory wafer, a logic wafer, or a digital wafer. In the present embodiment, the second semiconductor wafer 23 is a memory wafer that is mounted on the first circuit carrier 21 by a wire bonding technique. The second semiconductor wafer 23 is bonded to the surface of the first semiconductor wafer 22 away from the first circuit carrier 21 by a second insulating paste 26 . The second semiconductor wafer 23 has a plurality of second electrical connection pads 231 corresponding to the plurality of fourth pads 2133. Each of the second electrical connection pads 231 passes through a second wire 232, such as a gold wire, and a corresponding one. The fourth pad 2133 is electrically connected. Preferably, in order to prevent signal interference between the first semiconductor wafer 22 and the second semiconductor wafer 23, a spacer 27 is further disposed between the first semiconductor wafer 22 and the second semiconductor wafer 23, that is, in the second A spacer 27 is disposed in the insulating paste 26. It will be understood by those skilled in the art that the spacer 27 is not a necessary technical feature of the present technical solution. Even if the spacer 27 is omitted, the second semiconductor wafer 23 can be disposed on the first semiconductor wafer 22.

The first encapsulant 24 is disposed on the surface of the second solder resist layer 215 away from the first substrate 211 and covers the first semiconductor wafer 22 and the second semiconductor wafer 23 to protect the first semiconductor The wafer 22 and the second semiconductor wafer 23 are protected from damage. The first encapsulant 24 may be formed on the first circuit carrier 21 by a printing or molding method. The material of the first encapsulant 24 may be an epoxy resin or an epoxy molding compound. In this embodiment, the cross-sectional area of the first encapsulant 24 is the same as the cross-sectional area of the first circuit carrier 21.

The first package device 20 can be obtained by: firstly, providing a double-sided copper-clad substrate, the double-sided copper-clad substrate comprising the first substrate 211 and respectively attached to both sides of the first substrate The upper side copper foil and the lower side copper foil, the first substrate 211 has the lower side surface 211a and the upper side surface 211b, and the upper side copper foil is attached to the upper side surface 211b, the lower side copper foil And affixed to the lower surface 211a; secondly, the plurality of third conductive holes 216 and the plurality of fourth conductive holes 217 are formed in the double-sided copper-clad substrate by a drilling technique and a plating filling technique, each of The third conductive hole 216 and the fourth conductive hole 217 both penetrate the first substrate 211, the upper copper foil and the lower copper foil; again, the lower copper foil is selectively etched to form the first conductive pattern 212, The second conductive pattern 213 is formed by selective etching of the upper copper foil, and each of the third pads 2131 is electrically connected to a first pad 2121 through a third conductive via 216, and each of the fourth pads 2133 Conductively conducting through a fourth conductive via 217 and a second pad 2123; then, Forming a first solder resist layer 214 on at least a portion of the first conductive pattern 212 and a lower side surface 211a exposed from the first conductive pattern 212 by printing, laminating or spraying, and a plurality of first soldering Each of the pads 2121 and the plurality of second pads 2123 are at least partially exposed from the first solder resist layer 214, and are printed, attached or sprayed to at least a portion of the second conductive patterns 213 and A second solder resist layer 215 is formed on the upper side surface 211b of the first substrate 211 exposed from the second conductive pattern 213, and each of the plurality of third pads 2131 and the plurality of fourth pads 2133 The pads are at least partially exposed from the second solder resist layer 215 to form the first circuit carrier 21; then, the first semiconductor wafer 22 is bonded to the second solder resist layer through the first insulating paste 25 The 215 is remote from the surface of the first substrate 211 and is mounted on the first circuit carrier 21 by a wire bonding technique. The plurality of first electrical connection pads 221 of the first semiconductor wafer 22 are electrically connected to the plurality of third electrodes. On the disk 2131; thereafter, the second semiconductor wafer 23 is passed through the second insulating paste 26 is bonded to the surface of the first semiconductor wafer 22 away from the upper surface 211b, and is mounted on the first circuit carrier 21 by a wire bonding technique, and the second electrical connection pads 231 of the second semiconductor wafer 23 are electrically connected to the plurality of Finally, the first solder wafer is formed on the surface of the second solder resist layer 215 of the first circuit carrier 21 away from the first substrate 211 by printing or molding. 22 and the first encapsulant 24 of the second semiconductor wafer 23, thereby obtaining the first package device 20.

The second package device 30 includes a second circuit carrier 31 , a third semiconductor wafer 33 mounted on the second circuit carrier 31 , and a second circuit carrier 31 and covering the third semiconductor wafer 33 . The second encapsulant 35.

The second circuit carrier 31 may be a single-sided circuit board, a double-sided circuit board or a multi-layer circuit board formed with a conductive pattern, and includes a second substrate 311, a third conductive pattern 312, a fourth conductive pattern 313, and a third solder resist. Layer 314 and fourth solder resist layer 315. The second substrate 311 has opposite upper side surfaces 311a and lower side surfaces 311b. In this embodiment, the second circuit carrier 31 is a four-layer circuit board, and the second substrate 311 has two layers of conductive patterns.

The second substrate 311 includes a first insulating layer 3111, a first conductive pattern layer 3112, a second insulating layer 3113, a second conductive pattern layer 3114, and a third insulating layer 3115. The first conductive pattern layer 3112 and the second conductive pattern layer 3114 are located on opposite surfaces of the second insulating layer 3113, and are electrically connected through the fifth conductive holes 317 disposed in the second insulating layer 3113. The first insulating layer 3111 covers the first conductive pattern layer 3112. The surface of the first insulating layer 3111 away from the second insulating layer 3113 is the upper side surface 311a of the second substrate 311. The third insulating layer 3115 covers the second conductive pattern layer 3114. The surface of the third insulating layer 3115 away from the second conductive pattern layer 3114 is the lower side surface 311b of the second substrate 311.

The third conductive pattern 312 is disposed on a surface of the first insulating layer 3111 away from the second insulating layer 3113 (ie, an upper side surface 311a of the second substrate 311), and is disposed on the first insulating layer The sixth conductive via 318 in the 3111 is electrically connected to the first conductive pattern layer 3112. The third conductive pattern 312 includes a plurality of fifth pads 3121, a plurality of sixth pads 3122, a plurality of seventh pads 3123, and a plurality of conductive lines 3124. Each of the fifth pads 3121 is located between the plurality of sixth pads 3122. That is, the plurality of sixth pads 3122 surround the plurality of fifth pads 3121. Each of the seventh pads 3123 is located between the plurality of fifth pads 3121. That is, the plurality of fifth pads 3121 surround the plurality of seventh pads 3123. The plurality of fifth pads 3121 are in one-to-one correspondence with the plurality of first conductive vias 103 to electrically conduct the first semiconductor wafer 22 and the second circuit carrier 31 through the plurality of first conductive vias 103. The plurality of sixth pads 3122 are in one-to-one correspondence with the plurality of second conductive vias 105 to electrically conduct the second semiconductor wafer 23 and the second circuit carrier 31 through the plurality of second conductive vias 105. The plurality of seventh pads 3123 and the third semiconductor wafer 33 are electrically connected by a plurality of solder bumps 331. The third semiconductor wafer 33 is mounted on the second circuit carrier 31 by a wire bonding technique, a surface mount technology, or a flip chip packaging technique. The third solder resist layer 314 covers the plurality of conductive lines 3124 of the at least a portion of the third conductive patterns 312 and the upper side surface 311a exposed from the third conductive patterns 312, and exposes the plurality of fifth The pad 3121, the plurality of sixth pads 3122, and the plurality of seventh pads 3123. The third solder resist layer 314 is used to cover the plurality of conductive lines 3124 in the third conductive pattern 312.

The fourth conductive pattern 313 is disposed on a surface of the third insulating layer 3115 away from the second insulating layer 3113 (ie, the lower surface 311b of the second substrate 311), and is disposed on the third insulation The seventh conductive via 319 in the layer 3115 is electrically connected to the second conductive pattern layer 3114. The fourth conductive pattern 313 includes a plurality of eighth pads 3131 and a plurality of conductive lines 3133. The fourth solder resist layer 315 covers the plurality of conductive lines 3133 of at least a portion of the fourth conductive pattern 313 and the lower side surface 311b exposed from the fourth conductive pattern 313, and exposes the plurality of Eight pads 3131. A plurality of solder ball protrusions 37 are disposed on the surface of the plurality of eighth pads 3131 exposed from the fourth solder resist layer 315 for electrically connecting the second circuit carrier 31 to other circuit boards or electronic components. .

The third semiconductor wafer 33 can be a memory wafer, a logic wafer, or a digital wafer. In the present embodiment, the third semiconductor wafer 33 is a logic wafer. The third semiconductor wafer 33 is bonded to the surface of the third solder resist layer 314 of the second circuit carrier 31 through the third insulating adhesive layer 38, and is covered by a flip chip packaging technology, a surface mount technology or a wire bonding technology. The seventh pads 3123 are electrically connected. In the embodiment, the third semiconductor wafer 33 is mounted on the second circuit carrier 31 by a flip chip packaging technology. The third semiconductor wafer 33 is electrically connected to the plurality of seventh pads 3123 through the plurality of solder bumps 331.

The second encapsulant 35 is disposed on the surface of the third solder resist layer 314 of the second circuit carrier 31 and covers the third semiconductor wafer 33 to protect the third semiconductor wafer 33 from damage. The second encapsulant 35 may be formed on the second circuit carrier 31 by printing or molding, and the cross-sectional area of the second encapsulant 35 is larger than the cross-sectional area of the third semiconductor wafer 33. Smaller than the cross-sectional area of the second circuit carrier 31 and less than or equal to the cross-sectional area of the receiving through-hole 101, so that the third semiconductor wafer 33 covered with the second encapsulant 35 can be accommodated in The receiving hole 101 is received. The second encapsulant 35 can be an epoxy resin or an epoxy molding compound.

The second package device 30 can be fabricated by: firstly, providing a double-sided circuit board including the second insulating layer 3113, the first conductive pattern layer 3112, and the second conductive pattern layer 3114, the first conductive pattern layer 3112 and the second conductive pattern layer 3114 are located on opposite surfaces of the second insulating layer 3113, and the first conductive pattern layer 3112 and the second conductive pattern layer 3114 are provided. The fifth conductive vias 317 in the second insulating layer 3113 are electrically connected to each other. Secondly, an upper single-sided copper-clad substrate is pressed onto the first conductive pattern layer 3112, and the upper single-sided copper-clad substrate comprises The first insulating layer 3111 is bonded to the upper copper foil of the first insulating layer 3111, and the first insulating layer 3111 is located between the first conductive pattern layer 3112 and the upper copper foil. Pressing a lower single-sided copper-clad substrate on the second conductive pattern layer 3114, the lower-side single-sided copper-clad substrate including the third insulating layer 3115 and the third insulating layer 3115 a lower side copper foil, and the third insulating layer 3115 is located at Between the second conductive pattern layer 3114 and the lower side copper foil; again, the upper side copper foil is selectively etched into the third conductive pattern 312, and the lower side copper foil is selectively etched to form the fourth conductive layer a pattern 313, and the third conductive pattern 312 is electrically connected to the first conductive pattern layer 3112 through a sixth conductive hole 318, and the fourth conductive pattern 313 passes through the seventh conductive hole 319 and the second conductive pattern The layer 3114 is electrically connected, such that an electrical connection between the third conductive pattern 312 and the fourth conductive pattern 313 is achieved; and then, at least a portion of the third conductive pattern 312 is printed, bonded, or sprayed. And forming a third solder resist layer 314 on the upper surface 311a of the first insulating layer 3111 exposed from the third conductive pattern 312, and a plurality of fifth pads 3121, a plurality of sixth pads 3122, and a plurality of Each of the seven pads 3123 is at least partially exposed from the third solder resist layer 314, and is exposed to and exposed from at least a portion of the fourth conductive pattern 313 by printing, laminating or spraying. The lower side surface 311 of the third insulating layer 3115 Forming the fourth solder resist layer 315 on b, and each of the plurality of eighth pads 3131 is at least partially exposed from the fourth solder resist layer 315, so that the second circuit load can be obtained. a board 31; then, the third semiconductor wafer 33 is electrically connected to the plurality of seventh pads 3123 by a wire bonding technique or a flip chip technique; finally, the second circuit carrier is printed or molded. A third solder resist layer 314 of 31 is formed away from the surface of the second substrate 311 to form a second encapsulant 35 covering the third semiconductor wafer 33, thereby obtaining the second package device 30.

It is understood by those skilled in the art that the first package device 20 and the second package device 30 may have other structures. For example, the first package device 20 may include only one first semiconductor wafer 22, that is, the second semiconductor wafer 23 is not included. In this case, the plurality of fourth pads 2133, the plurality of second pads 2123, the plurality of second conductive vias 105, the plurality of seventh pads 3123, and the plurality of sixth pads 3122 may correspondingly be omitted. . For example, the first semiconductor wafer 22 of the first package device 20 is disposed on the first solder resist layer 214 of the first circuit carrier 21 through an insulating layer, and is applied by wire bonding technology, surface mount technology or overlying The crystal package technology is mounted on the plurality of pads of the first circuit carrier 21 exposed from the first solder resist layer 214. In this case, the pads may pass through the first circuit carrier 21 The plurality of conductive lines are electrically connected to the plurality of first pads 2121. That is, in this case, the first semiconductor wafer 22 and the plurality of first pads 2121 are located on the same side of the first circuit carrier 21. For example, the first circuit carrier 21 of the first package device 20 may be a multi-layer circuit board, and the first semiconductor wafer 22 may be embedded in the multi-layer circuit board, in which case the first circuit carrier 21 is An embedded multi-layer circuit board with a chip embedded therein, and the first semiconductor wafer 22 embedded in the multi-layer circuit board can pass through a plurality of conductive lines and pads in the embedded multi-layer circuit board and a plurality of exposed portions A pad 2121 is electrically connected.

In the third step, referring to FIG. 9 , the first package device 20 and the second package device 30 are respectively disposed on two sides of the connection substrate 10 , and the third semiconductor wafer 33 is received in the receiving pass. In the hole 101, the plurality of first pads 2121 are in one-to-one correspondence with the solder pastes 109 at one end of the plurality of first conductive holes 103, and the plurality of fifth pads 3121 and the plurality of first conductive holes 103 are additionally The solder pastes 109 at one end are corresponding to each other and adjacent to each other, and the plurality of second pads 2123 are in one-to-one correspondence with the solder pastes 109 at one end of the plurality of second conductive vias 105, and the plurality of sixth pads 3122 and the plurality of second pads The solder pastes 109 on the other end of the conductive vias 105 are in one-to-one correspondence and adjacent to each other, thereby obtaining a stacked structure 40.

In the fourth step, referring to FIG. 10, the stack structure 40 is reflowed to melt and cure the solder paste 109 between the adjacent connection substrate 10 and the first package device 20 and the adjacent connection substrate 10. And a solder paste 109 between the second package device 30, thereby passing one end of the plurality of first conductive vias 103 of the connection substrate 10 and the plurality of first pads 2121 of the first package device 20 through a solder paste The other end of the plurality of first conductive vias 103 of the connection substrate 10 and the plurality of fifth pads 3121 of the second package device 30 are integrally soldered in one-to-one correspondence by solder paste. One end of the plurality of second conductive holes 105 of the connection substrate 10 and the plurality of second pads 2123 of the first package device 20 are integrally soldered in one-to-one correspondence by solder paste, and the connection substrate 10 is The other ends of the plurality of second conductive vias 105 are integrally soldered to the plurality of sixth pads 3122 of the second package device 30 in a one-to-one correspondence by solder paste. Thus, a stacked package structure 100 is obtained.

The stacked package structure 100 includes the connection substrate 10 and the first package device 20 and the second package device 30 on both sides of the connection substrate 10. The structures of the connection substrate 10, the first package device 20, and the second package device 30 are as described above. Specifically, the connection substrate 10 has a plurality of first conductive holes 103 and a plurality of second conductive holes 105. The plurality of second conductive holes 105 surround the plurality of first conductive holes 103. Each of the conductive holes 103, 105 penetrates the first surface 10a and the second surface 10b of the connection substrate 10, and solder paste 109 is printed on both ends of each of the conductive holes 103, 105. The first package device 20 includes a first circuit carrier 21 and a first semiconductor wafer 22 and a second semiconductor wafer 23 mounted on the first circuit carrier 21. The first circuit carrier 21 has a plurality of first pads 2121 and a plurality of second pads 2123. The plurality of first pads 2121 and the plurality of second pads 2123 are exposed on the same side of the first circuit carrier 21. The plurality of first pads 2121 are electrically connected to the first semiconductor wafer 22 and are in one-to-one correspondence with the plurality of first conductive holes 103. The plurality of second pads 2123 are electrically connected to the second semiconductor wafer 23 and are in one-to-one correspondence with the plurality of second conductive holes 105. Each of the first pads 2121 is soldered to one end of a corresponding one of the first conductive vias 103 by solder paste, and each of the second pads 2123 is soldered to one end of a second conductive via 105 corresponding thereto by a solder paste, thereby The first package device 20 is soldered to the side of the first surface 10a of the connection substrate 10. The second package device 30 includes a second circuit carrier 31 and a third semiconductor wafer 33 mounted on the second circuit carrier 31. The second circuit carrier 31 has a plurality of fifth pads 3121 and a plurality of sixth pads 3122. The plurality of fifth pads 3121 and the plurality of sixth pads 3122 are exposed on the same side of the second circuit carrier 31. The plurality of fifth pads 3121 are in one-to-one correspondence with the plurality of first conductive holes 103. The plurality of sixth pads 3122 are in one-to-one correspondence with the plurality of second conductive holes 105. Each of the fifth pads 3121 is soldered to the other end of one of the first conductive vias 103 corresponding thereto by solder paste. Each of the sixth pads 3122 is soldered to the other end of a second conductive via 105 corresponding thereto by solder paste, so that the second package device 30 is soldered to the side of the second surface 10b of the connection substrate 10.

In the stacked package structure 100, the first package device 20 and the second package device 30 are integrally connected by the connection substrate 10, and the connection substrate 10 and the first package device 20 and the connection substrate 10 The second package device 30 is connected to the solder paste 109 disposed on the conductive vias 103 and 105 in the connection substrate 10, and is not connected by solder balls, thereby improving the yield of the package structure 100 and reliability. In addition, when forming the conductive vias in the connection substrate 10, a through hole is formed on the insulating substrate 11 by a laser drilling process, and a laser drilling process can be used to form a via hole having a hole depth of less than 100 micrometers. Therefore, the through holes can be formed on the connecting substrate 10 having a thickness of less than or equal to 100 μm, thereby reducing the volume of the stacked package structure 100.

It is understood by those skilled in the art that the first encapsulant 24 can be further packaged with a package device away from the surface of the connection substrate 10. The second package device 30 can be repackaged away from the surface of the connection substrate 10. A packaged device to form a stacked package structure having three, four or more packaged devices.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

10. . . Connection substrate

10a. . . First surface

10b. . . Second surface

101. . . Receiving through hole

103. . . First conductive hole

105. . . Second conductive hole

106. . . Resin

107. . . First conductive cap

108. . . Second conductive cap

109. . . Solder paste

11. . . Insulating substrate

103a. . . First through hole

105a. . . Second through hole

20. . . First package device

twenty one. . . First circuit carrier

twenty two. . . First semiconductor wafer

twenty three. . . Second semiconductor wafer

twenty four. . . First encapsulant

211. . . First substrate

211a, 311b. . . Lower side surface

211b, 311a. . . Upper surface

212. . . First conductive pattern

213. . . Second conductive pattern

216. . . Third conductive hole

217. . . Fourth conductive hole

2121. . . First pad

2123. . . Second pad

2125, 2135, 3124, 3133. . . Conductive line

2131. . . Third pad

2133. . . Fourth pad

214. . . First solder mask

215. . . Second solder mask

221. . . First electrical connection pad

222. . . First wire

25. . . First insulating glue

26. . . Second insulating glue

231. . . Second electrical connection pad

232. . . Second wire

27. . . Spacer

30. . . Second package device

31. . . Second circuit carrier

33. . . Third semiconductor wafer

35. . . Second encapsulant

311. . . Second substrate

312. . . Third conductive pattern

313. . . Fourth conductive pattern

314. . . Third solder mask

315. . . Fourth solder mask

3111. . . First insulating layer

3112. . . First conductive pattern layer

3113. . . Second insulating layer

3114. . . Second conductive pattern layer

3115. . . Third insulating layer

317. . . Fifth conductive hole

318. . . Sixth conductive hole

3121. . . Fifth pad

3122. . . Sixth pad

3123. . . Seventh pad

331. . . Solder bump

319. . . Seventh conductive hole

3131. . . Eighth pad

37. . . Solder ball bump

38. . . Third insulating layer

40. . . Stack structure

100. . . Cascaded package structure

FIG. 1 is a schematic cross-sectional view of an insulating substrate provided by an embodiment of the present technical solution.

2 is a schematic cross-sectional view showing a through hole, a plurality of first through holes, and a plurality of second through holes formed in the insulating base material shown in FIG. 1.

3 is a cross-sectional view showing the hole walls of each of the plurality of first through holes and the plurality of second through holes shown in FIG. 2 to form a plurality of first conductive holes and a plurality of second conductive holes .

4 is a schematic cross-sectional view showing a state in which each of the plurality of first conductive vias and the plurality of second conductive vias shown in FIG. 3 is filled with a resin.

FIG. 5 is a schematic cross-sectional view showing the conductive caps formed at both ends of each of the conductive holes shown in FIG. 4.

Fig. 6 is a schematic cross-sectional view showing a connection substrate formed by printing a solder paste on each of the conductive caps shown in Fig. 5.

FIG. 7 is a schematic diagram of a first package device according to an embodiment of the present technical solution.

FIG. 8 is a schematic diagram of a second package device according to an embodiment of the present disclosure.

FIG. 9 is a cross-sectional view showing a stacked structure formed after the first package and the second package device shown in FIGS. 7 and 8 are respectively disposed on both sides of the connection substrate shown in FIG. 6.

FIG. 10 is a schematic cross-sectional view showing a laminated package structure obtained by performing a reflow process on the stacked structure shown in FIG.

10. . . Connection substrate

10a. . . First surface

10b. . . Second surface

101. . . Receiving through hole

103. . . First conductive hole

105. . . Second conductive hole

109. . . Solder paste

20. . . First package device

twenty one. . . First circuit carrier

twenty two. . . First semiconductor wafer

twenty three. . . Second semiconductor wafer

twenty four. . . First encapsulant

2121. . . First pad

2123. . . Second pad

30. . . Second package device

31. . . Second circuit carrier

3121. . . Fifth pad

3122. . . Sixth pad

100. . . Cascaded package structure

Claims (21)

A method for fabricating a package structure includes the steps of:
Providing a connection substrate having an opposite first surface and a second surface, wherein the connection substrate is provided with a plurality of first conductive holes, each of the first conductive holes penetrating the first surface and the second a surface, and solder paste is printed on both ends of each of the first conductive holes;
A first package device is disposed on a side of the first surface of the connection substrate, and a second package device is disposed on a side of the second surface of the connection substrate to form a stacked structure, wherein the first package device includes a circuit carrier board and a first semiconductor wafer mounted on the first circuit carrier, the first circuit carrier has a plurality of exposed first pads, and the plurality of first pads are One first conductive holes are in one-to-one correspondence, and each of the first pads is adjacent to a solder paste at one end of the corresponding first conductive hole, and the second package device includes a second circuit carrier and is mounted on the second a third semiconductor wafer on the circuit carrier, the second circuit carrier has a plurality of exposed fifth pads, and the plurality of fifth pads are also in one-to-one correspondence with the plurality of first conductive holes And each of the fifth pads is adjacent to the solder paste at the other end of the corresponding first conductive via; and the solder paste is cured at both ends of each of the first conductive vias, so that each of the first pads is soldered by the cured solder paste One end of a first conductive hole corresponding thereto, each fifth By curing the solder paste plate welded to the other end of a first conductive hole corresponding thereto, so that the first device and the second packaged device package are welded to opposite sides of the connection substrate to form a laminate package. The method of fabricating a package structure according to claim 1, wherein the method for forming the connection substrate comprises the steps of:
Providing an insulating substrate having the first surface and the second surface;
Forming a plurality of first through holes in the insulating substrate by using a laser drilling process;
Forming the plurality of first through holes into the plurality of first holes by depositing a layer of a conductive material on a hole wall of each of the first through holes or by filling a conductive paste in each of the first through holes a conductive hole; and a solder paste is printed on both ends of each of the first conductive holes by a printing process to obtain the connection substrate. The method of fabricating a package-on-package structure according to claim 2, wherein the plurality of first via holes are made into the plurality of layers by depositing a layer of a conductive material through a hole wall of each of the first through holes The first conductive via, after the plurality of first vias are formed into the plurality of first conductive vias, before the solder paste is printed on both ends of each of the first conductive vias by a printing process The method for forming a substrate further includes the steps of: filling a plug hole resin in each of the first conductive holes by a resin hole filling process; and depositing respectively on both ends of each of the first conductive holes filled with the plug resin by an electroplating process Forming a first conductive cap; when a solder paste is printed on both ends of each of the first conductive vias by a printing process, the solder paste is printed on the surface of the first conductive cap. The method of fabricating a package-on-package structure according to claim 3, wherein the plurality of first via holes are made into the plurality of holes by depositing a layer of a conductive material through a hole wall of each of the first through holes In the first conductive hole, the conductive material layer further extends from the first surface to form a first hole ring portion, and the conductive material layer further extends from the second surface to form a second hole ring portion, the first a first conductive cap at one end of the conductive hole is deposited on the surface of the plug hole resin and the surface of the first hole ring portion, and the first conductive cap at the other end of the first conductive hole is deposited on the surface of the plug hole resin and The surface of the second bore ring portion. The method for fabricating a package structure according to claim 2, wherein the insulating substrate is made of a thermosetting resin. The method of fabricating a package structure according to claim 1, wherein the first circuit carrier is a double-sided circuit board, and the method for forming the first package device comprises the steps of:
Providing a double-sided copper-clad substrate comprising a first substrate, an upper side copper foil and a lower side copper foil, the first substrate having an upper side surface and a lower side surface, the upper side copper foil being bonded to The upper side surface, the lower side copper foil is attached to the lower side surface;
Forming a plurality of third conductive holes in the double-sided copper-clad substrate;
Forming the lower side copper foil into a first conductive pattern via selective etching, the first conductive pattern including the plurality of first pads, the plurality of first pads and the plurality of third conductive Correspondingly, the upper side copper foil is formed into a second conductive pattern by selective etching, and the second conductive pattern includes a plurality of third pads corresponding to the plurality of first pads one by one, each of the first The third pad is electrically connected to a first pad through a third conductive via to form the first circuit carrier; and the first semiconductor is connected by wire bonding technology, surface mount technology or flip chip packaging technology The wafer is mounted on the first circuit carrier to form the first package device. The method of fabricating a package structure according to claim 6, wherein after the first semiconductor wafer is mounted on the first circuit carrier, a cover is formed on the first circuit carrier. The first encapsulant of the first semiconductor wafer is described to protect the first semiconductor wafer. The method of fabricating a package-on-package structure according to claim 6, wherein the lower side copper foil is formed into a first conductive pattern via selective etching, and the upper side copper foil is made into a second conductive via selective etching. After the pattern, a first solder resist layer is further disposed on a portion of the surface of the first conductive pattern and a lower side surface exposed from the first conductive pattern, the plurality of first pads being exposed from the first solder resist layer And providing a second solder resist layer on a portion of the surface of the second conductive pattern and the upper side surface exposed from the second conductive pattern, the plurality of third pads being exposed from the second solder resist layer. The method of fabricating a package structure according to claim 1, wherein the first semiconductor wafer and the plurality of first pads are located on opposite sides of the first circuit carrier; the connection substrate is further There is a receiving through hole penetrating through the first surface and the second surface, the plurality of first conductive holes surrounding the receiving through hole; the third semiconductor wafer and the plurality of fifth The pads are located on the same side of the second circuit carrier, and the plurality of fifth pads surround the third semiconductor wafer, and the second package device is disposed on a side of the second surface of the connection substrate to form In the stacking structure, the third semiconductor wafer is received in the receiving through hole. A method for fabricating a package structure includes the steps of:
Providing a connection substrate having an opposite first surface and a second surface, wherein the connection substrate is provided with a plurality of first conductive holes and a plurality of second conductive holes, each of the first conductive holes and each The second conductive holes are respectively penetrated through the first surface and the second surface, and solder paste is printed on each of the first conductive holes and each of the second conductive holes;
A first package device is disposed on a side of the first surface of the connection substrate, and a second package device is disposed on a side of the second surface of the connection substrate to form a stacked structure, wherein the first package device includes a circuit carrier board and a first semiconductor wafer and a second semiconductor wafer mounted on the first circuit carrier, the first circuit carrier has a plurality of first pads and a plurality of second pads, The first pad and the plurality of second pads are exposed on the same side of the first circuit carrier, the plurality of first pads are electrically connected to the first semiconductor chip, and the plurality of first conductive holes One-to-one correspondence, each of the first pads is adjacent to a solder paste at one end of the corresponding first conductive via, and the plurality of second pads are electrically connected to the second semiconductor wafer, and the plurality of Two conductive holes are corresponding to each other, each of the second pads is adjacent to a solder paste at one end of the corresponding second conductive hole, and the second package device includes a second circuit carrier and a second circuit carrier a third semiconductor wafer, the second circuit carrier has a plurality of a pad and a plurality of sixth pads, the plurality of fifth pads and the plurality of sixth pads being exposed on a same side of the second circuit carrier, the plurality of fifth pads and the plurality of The first conductive holes are in one-to-one correspondence, and each of the fifth pads is adjacent to the solder paste at the other end of the corresponding first conductive hole, and the plurality of sixth pads and the plurality of second conductive holes are Correspondingly, each of the sixth pads is adjacent to the solder paste at the other end of the second conductive via corresponding thereto; and the solder paste at both ends of each of the first conductive vias and the solder paste on both ends of each of the second conductive vias are cured, so that Each of the first pads is soldered to one end of a corresponding one of the first conductive vias by a cured solder paste, and each of the fifth pads is soldered to the other end of the corresponding one of the first conductive vias by the cured solder paste, and Having each of the second pads soldered to one end of a second conductive via corresponding thereto by a cured solder paste, each sixth pad being soldered to the other end of a corresponding second conductive via by a cured solder paste, Thereby, the first package device and the second package device are respectively soldered to the connection base Opposite sides, forming a laminate package. The method of fabricating a package package structure according to claim 10, wherein the first semiconductor wafer is located between the second semiconductor wafer and the first circuit carrier, the first semiconductor wafer and the plurality of The first pads are located on opposite sides of the first circuit carrier, the plurality of second pads surround the plurality of first pads; the connection substrate further defines a receiving through hole, the receiving through a hole penetrating the first surface and the second surface, the plurality of first conductive holes surrounding the receiving through hole, the plurality of second conductive holes surrounding the plurality of first conductive holes; the third semiconductor The wafer, the plurality of fifth pads, and the plurality of sixth pads are located on a same side of the second circuit carrier, and the plurality of fifth pads and the plurality of sixth pads are both surrounding a third semiconductor wafer, the plurality of sixth pads surrounding the plurality of fifth pads; and when the second package device is disposed on a side of the second surface of the connection substrate to constitute the stacked structure The third semiconductor wafer is housed in the receiving through hole. The method of fabricating a package structure according to claim 11, wherein the method for forming the connection substrate comprises the steps of:
Providing an insulating substrate, the insulating substrate comprising the first surface and the second surface;
Forming a plurality of first through holes and a plurality of second through holes in the insulating substrate by a laser drilling process, the plurality of second through holes surrounding the plurality of first through holes;
Depositing a layer of conductive material on the wall of each of the first through holes and the wall of each of the second through holes to form the plurality of first through holes into the plurality of first conductive holes, The second through holes are made into the plurality of second conductive holes;
Filling a plug hole resin into each of the first conductive holes and filling each of the second conductive holes with a resin hole filling process;
Depositing a first conductive cap on each of the two ends of the first conductive via filled with the plug resin, and depositing a second conductive cap on each of the two ends of the second conductive via filled with the plug resin ;
A solder paste is printed on each of the first conductive cap surfaces and each of the second conductive cap surfaces by a printing process to obtain the connecting substrate. The method of fabricating a package structure according to claim 12, wherein a cross-sectional area of the first conductive cap is larger than an area of the first through hole, and a cross-sectional area of the second conductive cap is larger than an area of the second through hole. A stacked package structure comprising:
Connecting the substrate, the connecting substrate has opposite first and second surfaces, and the connecting substrate is provided with a plurality of first conductive holes, each of the first conductive holes penetrating the first surface and the second surface And a solder paste is disposed on each of the first conductive holes;
a first package device, the first package device includes a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier, the first circuit carrier has a plurality of first pads, the plurality The first pads are in one-to-one correspondence with the plurality of first conductive holes, and each of the first pads is soldered to one end of a corresponding one of the first conductive holes by solder paste, so that the first package device is soldered to the connection substrate a second package device, the second package device includes a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier, the second circuit carrier has a plurality of a fifth pad, wherein the plurality of fifth pads are also in one-to-one correspondence with the plurality of first conductive holes, and each of the fifth pads is soldered to the other end of the corresponding one of the first conductive holes by solder paste, Thereby, the second package device is soldered to the side of the second surface of the connection substrate. The stacked package structure of claim 14, wherein each of the first conductive vias is filled with a plug resin, and a first conductive cap is deposited on each of the first conductive pillars. The first conductive cap covers the corresponding first conductive hole. The stacked package structure of claim 14, wherein the first package device further comprises a first encapsulant covering the first semiconductor wafer, a cross-sectional area of the first encapsulant and a first circuit carrier The cross-sectional area is the same, and the first semiconductor wafer and the plurality of first pads are located on opposite sides of the first circuit carrier. The layered package structure of claim 14, wherein the connection substrate is provided with a receiving through hole, the receiving through hole penetrating the first surface and the second surface, the plurality of first conductive holes surrounding The receiving hole is formed; the third semiconductor wafer and the plurality of fifth pads are located on the same side of the second circuit carrier, and the third semiconductor chip is received in the receiving through hole, the plurality of A fifth pad surrounds the third semiconductor wafer. The package structure of claim 17, wherein the second package device further comprises a second encapsulant covering the third semiconductor wafer, the second encapsulant having a cross-sectional area greater than that of the third semiconductor wafer The cross-sectional area is smaller than the cross-sectional area of the second circuit carrier and less than or equal to the cross-sectional area of the receiving through hole. A stacked package structure comprising:
Connecting the substrate, the connecting substrate has opposite first and second surfaces, and the connecting substrate is provided with a plurality of first conductive holes and a plurality of second conductive holes, each of the first conductive holes and each of the second The conductive holes are formed through the first surface and the second surface, and each of the first conductive holes and each of the second conductive holes are provided with a solder paste;
a first package device, the first package device includes a first circuit carrier and a first semiconductor wafer and a second semiconductor wafer mounted on the first circuit carrier, the first circuit carrier having a plurality of first pads a plurality of first pads and a plurality of second pads exposed on a same side of the first circuit carrier, the plurality of first pads and the first semiconductor wafer Electrically connected, and corresponding to the plurality of first conductive holes, the plurality of second pads are electrically connected to the second semiconductor wafer, and are in one-to-one correspondence with the plurality of second conductive holes, each The first pads are soldered to one end of a corresponding first conductive via by a solder paste, and each of the second pads is soldered to one end of a corresponding second conductive via by solder paste, thereby soldering the first package device On a side of the first surface of the connection substrate; and a second package device, the second package device includes a second circuit carrier and a third semiconductor wafer mounted on the second circuit carrier, the second circuit carrying The board has a plurality of fifth pads and a plurality of sixth pads, The fifth pad and the plurality of sixth pads are exposed on the same side of the second circuit carrier, and the plurality of fifth pads are in one-to-one correspondence with the plurality of first conductive holes, the plurality of The sixth pad is in one-to-one correspondence with the plurality of second conductive holes, and each of the fifth pads is soldered to the other end of the corresponding one of the first conductive holes by solder paste, and each of the sixth pads is soldered by solder paste And at the other end of a second conductive hole corresponding thereto, so that the second package device is soldered to the side of the second surface of the connection substrate. The stacked package structure of claim 19, wherein each of the first conductive vias is filled with a plug resin, and a first conductive cap is deposited on each of the first conductive pillars. The first conductive cap covers the corresponding first conductive hole. The layered package structure of claim 19, wherein a receiving through hole is formed in the connecting substrate, the receiving through hole penetrating the first surface and the second surface, and the plurality of first conductive holes surround The receiving hole is formed; the third semiconductor wafer and the plurality of fifth pads are located on the same side of the second circuit carrier, and the third semiconductor chip is received in the receiving through hole, the plurality of A fifth pad surrounds the third semiconductor wafer.