TWI839931B - Package structure embedded with sensor chip and manufacturing method thereof - Google Patents

Abstract

A package structure embedded with a sensor chip is provided, in which a sensor element is embedded in an encapsulation layer and has a light-emitting layer, and a circuit layer is arranged on the encapsulation layer and electrically connected to the sensor element to reduce the overall thickness of the package structure.

Description

Packaging structure and manufacturing method of embedded sensor chip

The present invention relates to a semiconductor packaging process, in particular to a packaging structure with an embedded sensor chip and its manufacturing method

With the booming development of the electronics industry, electronic products are gradually moving towards multi-function, high performance and miniaturization. The traditional image sensor package mainly places the sensor chip on a chip carrier, and uses wire bonding to electrically connect the sensor chip carrier, and then covers the sensor chip with a transparent member such as glass so that the image light can be captured by the sensor chip. In this way, the packaged image sensor package can be integrated into external devices such as printed circuit boards (PCBs) by system manufacturers for use in various electronic products such as digital cameras (DSC), digital video cameras (DV), optical mice, mobile phones, fingerprint readers, etc.

In the current semiconductor packaging of 3D sensing components, miniaturization or thinning is one of the main goals. FIG1 is a cross-sectional schematic diagram of a conventional semiconductor package. As shown in FIG1, the semiconductor package 1 is a vertical cavity surface emitting laser (VCSEL) type semiconductor chip 13 (which has a sensing area S and a metal layer 12 on the back of the chip) configured on a packaging substrate 11, and then a gold (Au) wire 14 is formed by wire bonding to electrically connect the electrode pad 130 of the semiconductor chip 13 and the packaging substrate 11. In order to obtain better electrical requirements, multiple wire bondings are required, resulting in increased costs. Among them, the back of the semiconductor chip 13 uses an extremely thick (thickness t greater than 1 micron) gold (Au) material as the metal layer 12 to enhance the heat dissipation effect. Afterwards, a glass cover 15 is mounted on the package substrate 11 through the support 10 to protect the semiconductor chip 13 and the wire 14 to prevent structural damage.

However, in the known semiconductor package 1, the package substrate 11 is used as a carrier of the semiconductor chip 13, and its thickness T is difficult to reduce, and the wire 14 needs to have a certain pull-up arc, so that the support member 10 needs to have a certain height h to prevent the glass cover 15 from colliding with the wire 14, so it is difficult to lower the position of the glass cover 15, so the height H of the overall structure of the semiconductor package 1 is difficult to reduce, and it is difficult to meet the thinning requirements.

Furthermore, the glass cover 15 needs to be placed on the package substrate 11 via the supporting members 10, which will also increase the height H of the semiconductor package 1, making it difficult to thin the semiconductor package 1.

Furthermore, the metal layer 12 for heat dissipation is made of gold, which not only increases the material cost of the semiconductor package 1, but also increases the height H of the overall structure of the semiconductor package 1, making it difficult for the semiconductor package 1 to meet the requirements of miniaturization or thinning.

Therefore, how to overcome the above-mentioned problems of knowledge and technology has become an urgent issue that the industry needs to overcome.

In view of the problems of the prior art, the present invention provides a package structure of an embedded sensing chip, comprising: a package layer having a first surface and a second surface opposite to each other; a sensing element embedded in the package layer and having a front surface and a back surface opposite to each other, wherein the front surface has a light-emitting layer and a plurality of electrode pads exposed on the first surface of the package layer, and the back surface has a metallization layer, and the metallization layer is a single metal layer, a single alloy layer, a plurality of metal layers, or a plurality of metal layers. A layer or multiple layers of alloy layers, which include titanium, nickel, silver, gold or a combination thereof, or an alloy thereof; a first circuit layer, which is combined with the second surface of the packaging layer, wherein a portion of the first circuit layer is combined with the back surface of the sensing element to carry the sensing element; a second circuit layer, which is disposed on the first surface of the packaging layer and electrically connected to the sensing element; and a plurality of conductive posts, which are buried in the packaging layer and electrically connect the first circuit layer and the second circuit layer.

The present invention also provides a method for manufacturing a package structure of an embedded sensing chip, comprising: forming a first circuit layer on a carrier; forming a plurality of conductive posts and configuring at least one sensing element on the first circuit layer, wherein the sensing element has a front side and a back side opposite to each other, and the front side has a light-emitting layer and a plurality of electrode pads, and the back side has a metallization layer, and the metallization layer is a single metal layer, a single alloy layer, a plurality of metal layers, or a plurality of alloy layers. , which includes titanium, nickel, silver, gold or a combination thereof, or an alloy thereof; forming a packaging layer on the carrier to cover the first circuit layer, the sensing element and the plurality of conductive pillars, and the packaging layer does not cover the light-emitting layer, the plurality of electrode pads and one end surface of the plurality of conductive pillars; forming a second circuit layer on the packaging layer so that the second circuit layer is electrically connected to the sensing element and the plurality of conductive pillars; and removing the carrier to expose the first circuit layer.

In the aforementioned embedded sensing chip packaging structure and its manufacturing method, the multiple metal layers on the back side of the sensing element include a stacked titanium layer, a nickel layer, a titanium layer and a silver layer.

The aforementioned embedded sensing chip packaging structure and its manufacturing method further include covering the light-transmitting layer on the light-emitting layer before placing the sensing element on the carrier, and exposing the light-transmitting layer on the packaging layer after forming the packaging layer.

In the aforementioned embedded sensing chip packaging structure and its manufacturing method, the second circuit layer extends into the packaging layer to form a conductive blind hole, so that the second circuit layer is electrically connected to the sensing element through the conductive blind hole.

In the aforementioned embedded sensing chip packaging structure and its manufacturing method, the sensing element is bonded to the first circuit layer via a bonding layer on its back side, and the bonding layer includes a conductive paste and/or a heat sink.

The aforementioned embedded sensor chip packaging structure and its manufacturing method further include forming an insulating protection layer on the packaging layer and the second circuit layer, and the insulating protection layer does not cover the light-emitting layer.

As can be seen from the above, the embedded sensing chip packaging structure and its manufacturing method of the present invention mainly embeds the sensing element in the packaging layer, and does not need to use the conventional packaging substrate. Therefore, compared with the conventional technology, the present invention can effectively meet the needs of miniaturization or thinning.

Furthermore, the present invention directly electrically connects the sensing element with the second circuit layer, so there is no need to electrically connect the sensing element and the second circuit layer by wire bonding. Therefore, compared with the prior art, the present invention can not only save material costs, but also does not need to consider the arc of wire bonding, thus achieving better uniformity and thinner thickness.

In addition, the present invention embeds the light-transmitting layer in the packaging layer by contacting and bonding the light-transmitting layer to the sensing element, so there is no need to mount the light-transmitting layer on the first surface of the packaging layer. Therefore, compared with the conventional technology, the present invention is easier to be thinned.

In addition, the present invention forms a metal layer on the back of the sensing element by electroplating copper, so there is no need to use extremely thick gold materials, which can not only reduce the material cost of the packaging structure, but also effectively reduce the thickness of the packaging structure.

1:Semiconductor packages

10: Support parts

11: Packaging substrate

12: Metal layer

13: Semiconductor chip

130:Electrode pad

14: Wire

15: Glass mask

2:Packaging structure

20: Sensing element

20a: Front

20b: Back

200:Electrode pad

21: Carrier

22: First circuit layer

22b,27a: Surface

221: Pad

222: Conductive traces

23: Binding layer

24: Metallization layer

25: Second circuit layer

250: Conductive blind vias

26: Insulation protective layer

260: Opening area

27: Translucent layer

28: Conductive column

28a: End face

29: Packaging layer

29a: First surface

29b: Second surface

290: Opening

3: Electronic devices

30: Conductive element

A: Luminescent layer

D, d, T, t, r: thickness

H,h: height

S: Sensing area

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package.

Figures 2A to 2H are cross-sectional schematic diagrams of the manufacturing method of the packaging structure of the present invention.

FIG3A is a cross-sectional schematic diagram of the subsequent process of FIG2G.

FIG3B is a cross-sectional schematic diagram of another embodiment of FIG3A.

The following is a specific embodiment to illustrate the implementation of the present invention. People familiar with this art can easily understand other advantages and effects of the present invention from the content disclosed in this manual. However, the specific embodiments contained in this article are not used to limit the present invention. The present invention can also be implemented or applied through other different implementation methods. The details contained in this article can also be given different changes or modifications based on different viewpoints and applications without deviating from the spirit of the present invention.

It should be noted that the features such as structure, proportion, size, etc. depicted in the drawings attached to this specification are only used to match the contents disclosed in the specification for understanding and reading by people familiar with this technology, and are not used to limit the restrictive conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention. At the same time, the terms such as "above", "first", "second", "third" and "one" used in this specification are only used to facilitate the clarity of the description, and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.

Figures 2A to 2H are schematic cross-sectional views of the manufacturing method of the embedded sensor chip packaging structure 2 of the present invention. In this embodiment, the manufacturing method of the present invention uses the full panel level packaging (PLP) specification to perform the packaging process to improve efficiency and increase output.

As shown in FIG. 2A , a first circuit layer 22 is formed on a carrier 21 , and the first circuit layer 22 includes at least one pad 221 and a plurality of conductive traces 222 .

In this embodiment, the carrier 21 can be a detachable copper foil substrate, metal plate or other plate material to facilitate the production of the first circuit layer 22. For example, a release layer (not shown) can be formed on the carrier 21 as required to combine the first circuit layer 22.

Furthermore, the first circuit layer 22 uses a redistribution layer (RDL) process to perform patterned copper electroplating operations.

As shown in FIG. 2B , at least one sensing element 20 having a light-transmitting layer 27 is disposed on the pad 221 of the first circuit layer 22 .

In this embodiment, the sensing element 20 has a front side 20a and a back side 20b opposite to each other, and the front side 20a is formed with a plurality of electrode pads 200 and at least one light-emitting layer A, so that the light-transmitting layer 27 is formed on the front side 20a to cover the light-emitting layer A, and the electrode pads 200 are exposed from the light-transmitting layer 27. For example, the plurality of electrode pads 200 and the light-emitting layer A can be manufactured together by electroplating copper.

Furthermore, the sensing element 20 is disposed on the pad 221 of the first circuit layer 22 via a bonding layer 23 with its back side 20b. Furthermore, the bonding layer 23 may include a conductive paste and/or a heat sink, such as copper paste, solder paste, silver paste or other suitable pastes, without particular limitation.

Furthermore, a metallization layer 24 is formed on the back surface 20b of the sensing element 20, and its thickness r is extremely thin, about less than 0.2 micrometers (μm), and the metallization layer 24 is a single metal layer, a single alloy layer, a plurality of metal layers, or a plurality of alloy layers. For example, the material forming the metallization layer 24 is gold (Au), titanium (Ti), nickel (Ni), silver (Ag) or a combination thereof, or an alloy thereof. Specifically, the plurality of metal layers on the back surface 20b of the sensing element 20 include a stacked titanium layer, a nickel layer, a titanium layer, and a silver layer, but are not limited to the above. It should be understood that the materials of the metallization layer 24 and the first circuit layer 22 may be the same or different.

In addition, the light-transmitting layer 27 allows light to penetrate, so the material forming the light-transmitting layer 27 is a light-transmitting material.

Therefore, by covering the light-transmitting layer 27 on the light-emitting layer A of the sensing element 20, the light-emitting layer A can be prevented from being damaged in various environments of different processes, thereby improving the yield of the product.

As shown in FIG. 2C , a plurality of conductive posts 28 are formed on the conductive traces 222 of the first circuit layer 22 so that the conductive posts 28 are electrically connected to the first circuit layer 22 .

In this embodiment, the conductive column 28 is manufactured simultaneously by patterned exposure and development. For example, copper is electroplated to form a column of the desired geometric shape, such as a square column, a round column, or a short column of other cross-sectional shapes.

As shown in FIG. 2D , a packaging layer 29 is formed on the carrier 21 so that the packaging layer 29 covers the first circuit layer 22 , the bonding layer 23 , the sensing element 20 and the conductive pillars 28 , and the packaging layer 29 does not cover the light-emitting layer A and one end surface 28a of the plurality of conductive pillars 28 .

In this embodiment, the packaging layer 29 is defined with a first surface 29a and a second surface 29b opposite to each other, so that the packaging layer 29 is bonded to the carrier 21 (or its release layer) with its second surface 29b.

Furthermore, the material forming the packaging layer 29 is an insulating material, which can be an organic dielectric material (such as a solder mask) or an inorganic dielectric material (such as an insulating oxide). For example, the types of organic dielectric materials may include ABF (Ajinomoto Build-up Film), photosensitive resin, polyimide (PI), Bismaleimide Triazine (BT), FR5 prepreg (PP), molding compound, epoxy molding compound (EMC), primer or other appropriate materials. The preferred material of the packaging layer 29 is PI, ABF or EMC, which is easy to process the circuit.

Furthermore, a part of the material of the packaging layer 29 is removed by a flattening process, such as grinding, so that the first surface 29a of the packaging layer 29 is flush with the end surface 28a of the conductive pillar 28, so that the end surface 28a of the conductive pillar 28 is exposed on the first surface 29a of the packaging layer 29.

In addition, after removing part of the material of the packaging layer 29, the first surface 29a of the packaging layer 29 can be aligned with the surface 27a of the light-transmitting layer 27, so that the surface 27a of the light-transmitting layer 27 is exposed on the first surface 29a of the packaging layer 29.

As shown in FIG. 2E , an opening 290 is formed on the packaging layer 29 by laser so that the electrode pad 200 of the sensing element 20 is exposed from the opening 290 , so that the packaging layer 29 does not cover the electrode pad 200 .

As shown in FIG. 2F , a second circuit layer 25 is formed on the first surface 29a of the packaging layer 29 so that the second circuit layer 25 is electrically connected to the conductive pillar 28, and the second circuit layer 25 extends into the opening 290 so that the second circuit layer 25 extends into the packaging layer 29 to form a conductive blind hole 250 so that the second circuit layer 25 is electrically connected to the electrode pad 200 of the sensing element 20 through the conductive blind hole 250.

In this embodiment, the second circuit layer 25 is a fan-out redistribution circuit layer (RDL), and the second circuit layer 25 is electrically connected to the first circuit layer 22 via the conductive pillar 28.

Therefore, the electrical conduction between the first and second circuit layers 22, 25 is achieved by electroplating copper pillars. After the package layer 29 is molded, the conductive pillars 28 are exposed by grinding to improve the problems of size limitation, voids in the holes, and poor electroplating uniformity in the conventional electroplating through-hole process.

As shown in FIG. 2G , an insulating protective layer 26 is formed on the first surface 29a of the packaging layer 29 and the second circuit layer 25 so that the light-transmitting layer 27 is exposed on the insulating protective layer 26 , and the insulating protective layer 26 does not cover the light-emitting layer A.

In this embodiment, the insulating protective layer 26 is a dielectric layer or a solder mask. For example, the material forming the insulating protective layer 26 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), etc., but not limited to the above materials; or a solder mask such as green paint, photosensitive ink, ABF or non-photosensitive dielectric material (such as EMC), but not limited to the above materials.

Furthermore, the insulating protective layer 26 can form an opening area 260 so that the light-transmitting layer 27 is exposed in the opening area 260.

As shown in FIG. 2H , the carrier 21 is removed to expose the second surface 29b of the packaging layer 29 and the first circuit layer 22 .

In this embodiment, the second surface 29b of the packaging layer 29 is flush with the surface 22b of the first circuit layer 22, so that the pad 221 and the plurality of conductive traces 222 are used as solder pads to combine the plurality of conductive elements 30, as shown in FIG. 3A. Therefore, in the subsequent manufacturing process, the packaging structure 2 can be connected to an electronic device 3 such as a circuit board through the conductive elements 30. For example, the conductive element 30 may include solder materials, such as solder balls, solder bumps, etc., but there is no particular limitation.

Furthermore, in another embodiment, the packaging structure 2 can remove the light-transmitting layer 27 as required, as shown in FIG. 3B .

It should be understood that the arrangement of the conductive element 30 in the above embodiment is applicable to a land grid array package (LGA) or a ball grid array package (BGA).

The manufacturing method of the present invention mainly embeds the sensing element 20 in the packaging layer 29 and removes the carrier 21 to facilitate thinning of the packaging structure 2. Therefore, compared with the conventional technology, the manufacturing method of the present invention does not need to adopt the configuration of the conventional packaging substrate, so that the packaging structure 2 can effectively meet the requirements of miniaturization or thinning.

Furthermore, the manufacturing method of the present invention uses the second circuit layer 25 to directly electrically connect the sensing element 20, so there is no need to electrically connect the sensing element 20 and the second circuit layer 25 by wire bonding during the manufacturing process. Therefore, compared with the conventional technology, the packaging structure 2 of the present invention does not need to use conventional gold wires during manufacturing, which not only saves material costs (because the electrode pad 200 and the second circuit layer 25 are both low-cost copper materials), but also does not need to consider the wire arc of the wire bonding, so it is easy to control the thickness d of the packaging layer 29, which is conducive to reducing the thickness D of the overall structure of the packaging structure 2, thereby achieving better uniformity and thinner thickness.

Furthermore, by contacting and bonding the light-transmitting layer 27 to the sensing element 20, the light-transmitting layer 27 is buried in the packaging layer 29, so there is no need to mount the light-transmitting layer 27 on the first surface 29a of the packaging layer 29. Therefore, compared with the prior art, the manufacturing method of the present invention can effectively reduce the thickness D of the packaging structure 2, making the packaging structure 2 easy to be thinned.

In addition, the metallization layer 24 is formed on the back side 20b (i.e., the back of the wafer) of the sensing element 20 by electroplating copper, so there is no need to use extremely thick gold materials, which not only reduces the material cost of the package structure 2, but also effectively reduces the thickness D of the package structure 2 due to its extremely thin thickness r (approximately reduced from greater than 1 micron to less than 0.2 micron), making the package structure 2 easier to meet the requirements of miniaturization or thinning. On the other hand, if the metallization layer 24 uses a composite metal material (such as Ti/Ni/Ti/Ag), the reliability performance between the back of the wafer and it can be improved.

The present invention provides a package structure 2 for an embedded sensing chip, comprising: a package layer 29, a sensing element 20, a first circuit layer 22, a second circuit layer 25, and a plurality of conductive pillars 28.

The packaging layer 29 has a first surface 29a and a second surface 29b opposite to each other.

The sensing element 20 is buried in the packaging layer 29 and has a front side 20a and a back side 20b opposite to each other, wherein the front side 20a has a light-emitting layer A and a plurality of electrode pads 200 exposed on the first surface 29a of the packaging layer 29, and the back side 20b has a metallization layer 24, and the metallization layer 24 is a single metal layer, a single alloy layer, a plurality of metal layers or a plurality of alloy layers, which includes titanium, nickel, silver, gold or a combination thereof, or an alloy thereof.

The first circuit layer 22 is combined with the second surface 29b of the packaging layer 29, wherein a portion of the first circuit layer 22 is combined with the back surface 20b of the sensing element 20 to support the sensing element 20.

The second circuit layer 25 is disposed on the first surface 29a of the packaging layer 29 and is electrically connected to the sensing element 20.

The conductive pillar 28 is buried in the packaging layer 29 and electrically connects the first circuit layer 22 and the second circuit layer 25.

In one embodiment, the plurality of metal layers of the metallization layer 24 of the back side 20b of the sensing element 20 include stacked titanium layers, nickel layers, titanium layers and silver layers.

In one embodiment, the packaging structure 2 further includes a light-transmitting layer 27 disposed on the light-emitting layer A.

In one embodiment, the second circuit layer 25 has a conductive blind hole 250 extending in the packaging layer 29, so that the second circuit layer 25 is electrically connected to the sensing element 20 through the conductive blind hole 250.

In one embodiment, the sensing element 20 is bonded to the first circuit layer 22 via a bonding layer 23 with its back surface 20b, and the bonding layer 23 includes a conductive paste and/or a heat sink.

In one embodiment, the packaging structure 2 further includes an insulating protection layer 26 formed on the first surface 29a of the packaging layer 29 and the second circuit layer 25, and the insulating protection layer 26 does not cover the light-emitting layer A.

In summary, the packaging structure and manufacturing method of the present invention mainly embeds the sensing element in the packaging layer, and does not need to use the conventional packaging substrate, so the present invention can effectively meet the needs of miniaturization or thinning.

Furthermore, the present invention directly electrically connects the sensing element with the second circuit layer, so there is no need to electrically connect the sensing element and the second circuit layer by wire bonding. Therefore, the present invention can not only save material costs, but also does not need to consider the arc of wire bonding, thus achieving better uniformity and thinner thickness.

In addition, the present invention embeds the light-transmitting layer in the packaging layer by contacting and bonding the light-transmitting layer to the sensing element, so there is no need to mount the light-transmitting layer on the first surface of the packaging layer, so the present invention is easier to be thinned.

In addition, the present invention forms a metal layer on the back of the sensing element by electroplating copper, so there is no need to use extremely thick gold materials, which can not only reduce the material cost of the packaging structure, but also effectively reduce the thickness of the packaging structure.

The above embodiments are used to illustrate the principle and effect of the present invention, but are not used to limit the present invention. Anyone familiar with this technology can modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application described below.

2:Packaging structure

20: Sensing element

22: First circuit layer

22b: Surface

23: Binding layer

24: Metallization layer

25: Second circuit layer

26: Insulation protective layer

27: Translucent layer

28: Conductive column

29: Packaging layer

29a: First surface

29b: Second surface

A: Luminescent layer

D,d: thickness

Claims (10)

A package structure for an embedded sensing chip includes: a packaging layer having a first surface and a second surface opposite to each other; a sensing element embedded in the packaging layer and having a front surface and a back surface opposite to each other, wherein the front surface has a light-emitting layer exposed on the first surface of the packaging layer, a light-transmitting layer and a plurality of electrode pads disposed on the light-emitting layer, and the back surface has a metallization layer, and the metallization layer is a single metal layer, a single alloy layer, a plurality of metal layers or a plurality of metal layers. A plurality of alloy layers, comprising titanium, nickel, silver, gold or a combination thereof, or an alloy thereof; a first circuit layer, which is combined with the second surface of the packaging layer, wherein a portion of the first circuit layer is combined with the back surface of the sensing element to carry the sensing element; a second circuit layer, which is disposed on the first surface of the packaging layer and electrically connected to the sensing element; and a plurality of conductive posts, which are buried in the packaging layer and electrically connect the first circuit layer and the second circuit layer. The package structure of the embedded sensing chip as described in claim 1, wherein the multiple metal layers on the back side of the sensing element include stacked titanium layers, nickel layers, titanium layers and silver layers. The package structure of the embedded sensing chip as described in claim 1, wherein the second circuit layer has a conductive blind hole extending in the package layer, so that the second circuit layer is electrically connected to the sensing element through the conductive blind hole. The package structure of the embedded sensing chip as described in claim 1, wherein the sensing element is bonded to the first circuit layer via a bonding layer on its back side, and the bonding layer includes a conductive paste and/or a heat sink. The packaging structure of the embedded sensing chip as described in claim 1 further includes an insulating protection layer formed on the packaging layer and the second circuit layer, and the insulating protection layer does not cover the light-emitting layer. A method for manufacturing a package structure of an embedded sensing chip includes: forming a first circuit layer on a carrier; forming a plurality of conductive posts and configuring at least one sensing element on the first circuit layer, wherein the sensing element has a front side and a back side opposite to each other, and the front side has a light-emitting layer and a plurality of electrode pads, and the back side has a metallization layer, and the metallization layer is a single metal layer, a single alloy layer, a plurality of metal layers, or a plurality of alloy layers, which contains titanium, nickel, silver, gold, or a combination thereof, or an alloy thereof, and wherein the sensing element is arranged Before placing the element on the carrier, a transparent layer is covered on the light-emitting layer, and after forming the packaging layer, the transparent layer is exposed on the packaging layer; a packaging layer is formed on the carrier to cover the first circuit layer, the sensing element and the plurality of conductive pillars, and the packaging layer does not cover the light-emitting layer, the plurality of electrode pads and one end surface of the plurality of conductive pillars; a second circuit layer is formed on the packaging layer to electrically connect the second circuit layer to the sensing element and the plurality of conductive pillars; and the carrier is removed to expose the first circuit layer. A method for manufacturing a package structure of an embedded sensing chip as described in claim 6, wherein the plurality of metal layers on the back side of the sensing element include a stacked titanium layer, a nickel layer, a titanium layer and a silver layer. A method for manufacturing a package structure of an embedded sensing chip as described in claim 6, wherein the second circuit layer extends into the package layer to form a conductive blind hole, so that the second circuit layer is electrically connected to the sensing element through the conductive blind hole. A method for manufacturing a package structure of an embedded sensing chip as described in claim 6, wherein the sensing element is bonded to the first circuit layer via a bonding layer on its back side, and the bonding layer includes a conductive paste and/or a heat sink. The method for manufacturing the package structure of the embedded sensing chip as described in claim 6 further includes forming an insulating protective layer on the package layer and the second circuit layer, and the insulating protective layer does not cover the light-emitting layer.

Images