TW200601516A - Stacked multi-package module - Google Patents

Stacked multi-package module

Info

Publication number
TW200601516A
TW200601516A TW093118580A TW93118580A TW200601516A TW 200601516 A TW200601516 A TW 200601516A TW 093118580 A TW093118580 A TW 093118580A TW 93118580 A TW93118580 A TW 93118580A TW 200601516 A TW200601516 A TW 200601516A
Authority
TW
Taiwan
Prior art keywords
connecting pads
semiconductor package
stacked multi
package module
spacer
Prior art date
Application number
TW093118580A
Other languages
Chinese (zh)
Inventor
Sheng-Tsung Liu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093118580A priority Critical patent/TW200601516A/en
Publication of TW200601516A publication Critical patent/TW200601516A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A stacked multi-package module includes a first semiconductor package, a spacer and a second semiconductor package. The spacer comprises a plurality of upper connecting pads, a plurality of lower connecting pads and a plurality electrical vias with a metal layer. The electrical vias connect the upper connecting pads and lower connecting pads. A plurality of solder materials are formed in the electrical vias and protrudes from the upper and lower connecting pads of the spacer. The solder materials connect the first semiconductor package and the second semiconductor package.
TW093118580A 2004-06-25 2004-06-25 Stacked multi-package module TW200601516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093118580A TW200601516A (en) 2004-06-25 2004-06-25 Stacked multi-package module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093118580A TW200601516A (en) 2004-06-25 2004-06-25 Stacked multi-package module

Publications (1)

Publication Number Publication Date
TW200601516A true TW200601516A (en) 2006-01-01

Family

ID=57806924

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093118580A TW200601516A (en) 2004-06-25 2004-06-25 Stacked multi-package module

Country Status (1)

Country Link
TW (1) TW200601516A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738094A (en) * 2012-05-25 2012-10-17 日月光半导体制造股份有限公司 Semiconductor packaging structure for stacking and manufacturing method thereof
CN103594386A (en) * 2012-08-17 2014-02-19 宏启胜精密电子(秦皇岛)有限公司 Laminated packaging composition and making method thereof
CN103681365A (en) * 2012-08-31 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 Package-on-package (POP) structure and manufacturing method for POP structure
TWI483321B (en) * 2012-09-19 2015-05-01 Zhen Ding Technology Co Ltd Package on package structure and method for manufacturing same
TWI614865B (en) * 2010-12-16 2018-02-11 英特爾公司 Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614865B (en) * 2010-12-16 2018-02-11 英特爾公司 Lower ic package structure for coupling with an upper ic package to form a package-on-package (pop) assembly and pop assembly including such a lower ic package structure
US10879219B2 (en) 2010-12-16 2020-12-29 Intel Corporation Lower IC package structure for coupling with an upper IC package to form a package-on-package (PoP) assembly and PoP assembly including such a lower IC package structure
CN102738094A (en) * 2012-05-25 2012-10-17 日月光半导体制造股份有限公司 Semiconductor packaging structure for stacking and manufacturing method thereof
CN103594386A (en) * 2012-08-17 2014-02-19 宏启胜精密电子(秦皇岛)有限公司 Laminated packaging composition and making method thereof
TWI461124B (en) * 2012-08-17 2014-11-11 Zhen Ding Technology Co Ltd Package on package structure and method for manufacturing same
CN103681365A (en) * 2012-08-31 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 Package-on-package (POP) structure and manufacturing method for POP structure
CN103681365B (en) * 2012-08-31 2016-08-10 宏启胜精密电子(秦皇岛)有限公司 Package-on-package structure and preparation method thereof
TWI483321B (en) * 2012-09-19 2015-05-01 Zhen Ding Technology Co Ltd Package on package structure and method for manufacturing same

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