TWI506758B - Package on package structure and method for manufacturing same - Google Patents

Description

Cascading package structure and manufacturing method thereof

The present invention relates to a semiconductor package technology, and more particularly to a package-on-package (POP) structure and a method of fabricating the same.

As the size of semiconductor devices continues to decrease, stacked package structures with upper packaged devices and lower packaged devices are also receiving increasing attention. The package structure is generally made by a laminate manufacturing method. In the conventional layer fabrication method, in order to achieve high-density integration and small-area mounting, a groove is usually disposed on the circuit carrier of the lower package device, and the wafer of the lower package device is mounted on the groove of the circuit carrier. Inside. However, since the wafer is small in volume, the groove has a certain depth, so that the packaging of the lower package device is difficult, and the package efficiency of the package package structure having the lower packager is also low.

The invention provides a laminated package structure with high packaging efficiency and a manufacturing method thereof.

A method of fabricating a package structure comprising the steps of: providing a first package device, the first package device comprising a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier, The first circuit carrier is provided with a receiving recess, the first circuit carrier further has a plurality of exposed first pads, and the plurality of first pads and the receiving recess are located on the first circuit The same side of the board, and multiple a first pad surrounds the receiving groove, and a surface of each of the first pads is formed with a conductive paste; a second package device is disposed on a side of the plurality of first pads of the first package device, thereby forming a stacked structure, the second package device includes a second circuit carrier and a second semiconductor wafer mounted on the second circuit carrier, the second circuit carrier having a plurality of exposed second a pad and a plurality of electrical connection pads, wherein the plurality of second pads are in one-to-one correspondence with the plurality of first pads, and each of the second pads is adjacent to the conductive paste on the first pad corresponding thereto The plurality of electrical connection pads and the plurality of second pads are located on the same side of the second circuit carrier, and the second semiconductor wafer is mounted on the plurality of electrical connection pads and is received in the Inside the receiving recess; and curing the conductive paste on each of the first pads such that each of the second pads is soldered to the first pad through the cured conductive paste, thereby soldering the second package Forming a first side of the plurality of first pads of the first circuit carrier Laminated packaging structure.

A stacked package structure includes a first package device and a second package device. The first package device includes a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier. The first circuit carrier is provided with a receiving recess. The first circuit carrier also has a plurality of exposed first pads. The plurality of first pads and the receiving recess are located on the same side of the first circuit carrier. A surface of each of the first pads is formed with a conductive paste. The second package device includes a second circuit carrier and a second semiconductor wafer mounted on the second circuit carrier. The second circuit carrier has a plurality of exposed second pads and a plurality of electrical connection pads. The plurality of second pads are in one-to-one correspondence with the plurality of first pads, and each of the second pads is connected to the first pad corresponding thereto by the conductive paste on the corresponding first pad . The plurality of electrical connection pads and the plurality of second pads are on the same side of the second circuit carrier. The second semiconductor wafer is mounted on the plurality of electrical connection pads And received in the receiving groove.

In the stacked package structure formed by the above method, since the second semiconductor wafer of the second package device is mounted on the exposed electrical connection pad and is received in the receiving recess of the first package device, the structure is not reduced. The difficulty of mounting the second semiconductor wafer improves the packaging efficiency of the package structure, and reduces the height of the package structure and reduces the volume of the package structure.

10‧‧‧Copper-clad substrate

11‧‧‧First copper foil layer

100, 311‧‧‧ basal layer

12‧‧‧Second copper foil layer

101‧‧‧Non-product area

102‧‧‧Product Area

110‧‧‧First conductive circuit layer

120‧‧‧Second conductive circuit layer

103a‧‧‧ receiving through hole

10a‧‧‧core circuit board

15, 15a‧‧‧ first film

13, 65‧‧‧ first pressed substrate

14, 66‧‧‧Second pressed substrate

131, 651‧‧‧ first bonding layer

133, 653‧‧‧ third copper foil layer

141, 661‧‧‧ second bonding layer

143, 663‧‧‧ fourth copper foil layer

130‧‧‧ Third conductive circuit layer

140‧‧‧fourth conductive layer

104, 105, 601, 603‧‧ ‧ through holes

135, 137, 655, 657‧‧‧ first pad

145, 147, 211, 221, 665, 667‧‧‧ electrical contact pads

149, 669‧‧‧ conductive lines

170, 670‧‧‧ first solder mask

180, 680‧‧‧second solder mask

151, 151a, 151b‧‧ ‧ film opening

103, 607‧‧‧ receiving groove

20, 60‧‧‧ first circuit carrier

21‧‧‧First semiconductor wafer

22‧‧‧ Third semiconductor wafer

213, 223‧‧‧bonding wire

23‧‧‧ Spacer

24‧‧‧Package colloid

25‧‧‧Electrical paste

200‧‧‧First packaged device

300‧‧‧Second packaged device

400‧‧‧Stack structure

31‧‧‧Second circuit carrier

33‧‧‧Second semiconductor wafer

35‧‧‧Bottom filler

312‧‧‧First conductive line pattern

313‧‧‧Second conductive line pattern

314‧‧‧ Third solder mask

315‧‧‧four solder mask

317‧‧‧ solder balls

311a‧‧‧ upper surface

311b‧‧‧lower surface

3122, 3123‧‧‧ second pad

3121‧‧‧Electrical connection pads

331‧‧‧ Conductive blind holes

500‧‧‧Layered package structure

63‧‧‧First copper foil

64‧‧‧Second copper foil

15b‧‧‧second film

630‧‧‧ Third conductive circuit layer

640‧‧‧fourth conductive layer

650‧‧‧ fifth conductive circuit layer

660‧‧‧ sixth conductive circuit layer

1 is a schematic cross-sectional view of a copper-clad substrate according to a first embodiment of the present invention. The copper-clad substrate includes a first copper foil layer, a base layer, and a second copper foil layer that are sequentially bonded.

2 is a schematic cross-sectional view showing the first copper foil layer shown in FIG. 1 as a first conductive wiring layer and the second copper foil layer as a second conductive wiring layer.

3 is a schematic cross-sectional view showing a core circuit substrate obtained by forming a through hole on the copper clad substrate shown in FIG. 2.

4 is a first film and a first pressing substrate which are sequentially pressed on the first conductive circuit layer side of the core circuit substrate shown in FIG. 3, and the second conductive circuit layer of the core circuit substrate is pressed one on the other side. A schematic cross-sectional view of the second press-bonded substrate, the first press-fit substrate has a third copper foil layer and a first adhesive layer, and the second press-bonded substrate has a fourth copper foil layer and a second adhesive layer.

5 is a schematic cross-sectional view showing the third copper foil layer shown in FIG. 4 as a third conductive wiring layer and the fourth copper foil layer as a fourth conductive wiring layer.

FIG. 6 is a schematic cross-sectional view of a first circuit carrier having a receiving recess obtained by removing material corresponding to the first adhesive layer of the receiving through hole.

FIG. 7 is a cross-sectional view showing the first semiconductor wafer and the second semiconductor wafer disposed on the side of the first circuit carrier shown in FIG. 6 away from the receiving recess.

FIG. 8 is a cross-sectional view showing the first package device obtained after the conductive paste is disposed on the receiving groove side of the first circuit carrier shown in FIG. 7.

FIG. 9 is a cross-sectional view showing a stacked structure obtained after stacking a second package device on the conductive paste side of the first package device shown in FIG.

FIG. 10 is a schematic cross-sectional view showing a laminated package structure obtained by performing a reflow process on the stacked structure shown in FIG.

FIG. 11 is a first embodiment of the present invention, wherein a first film and a first copper foil are pressed on the upper side of the core circuit substrate shown in FIG. 3, and a second film and a second copper foil are pressed on the lower side. Schematic diagram of the section.

Fig. 12 is a schematic cross-sectional view showing the first copper foil sheet shown in Fig. 11 as a third conductive wiring layer, and the second copper foil sheet as a fourth conductive wiring layer.

FIG. 13 is a cross-sectional view showing a first press-bonded substrate on the third conductive circuit layer shown in FIG. 12, and a second press-bonded substrate on the fourth conductive circuit layer. The first bonding layer and the third copper foil layer are laminated, and the second pressing substrate comprises a second bonding layer and a fourth copper foil layer.

Fig. 14 is a schematic cross-sectional view showing the third copper foil layer shown in Fig. 13 as a fifth conductive wiring layer and the fourth copper foil layer as a sixth conductive wiring layer.

15 is a schematic cross-sectional view showing a first circuit carrier having a receiving recess obtained after removing the material of the first adhesive layer corresponding to the receiving through hole shown in FIG. 14.

The laminated package structure and the manufacturing method thereof provided by the present technical solution will be further described in detail below with reference to the accompanying drawings and embodiments.

Referring to FIG. 1 to FIG. 10 , a method for fabricating a package package structure according to a first embodiment of the present technical solution includes the following steps:

In the first step, referring to FIG. 1, a copper clad substrate 10 is provided. In the present embodiment, the copper clad substrate 10 is a double-sided copper clad substrate, and includes a first copper foil layer 11 , a base layer 100 , and a second copper foil layer 12 which are sequentially bonded. The base layer 100 is an insulating layer made of an insulating material. In other embodiments, the copper clad substrate 10 may be a single-sided copper clad substrate, that is, the copper clad substrate 10 may include only the first copper foil layer 11 and the base layer 100.

The copper clad substrate 10 has a non-product area 101 and a product area 102 surrounding and surrounding the non-product area 101. The non-product area 101 is a waste area that will be removed after a series of processing, that is, the material of the copper-clad substrate at the non-product area 101 will be removed in a subsequent step. The product area 102 is an area that will form a circuit board product after a series of processing, that is, a material corresponding to the first copper foil layer 11 of the product area 102 and a second copper foil layer corresponding to the product area 102. The material of 12 will be formed into conductive traces and pads in subsequent steps. In the embodiment, the non-product area 101 is located at the center of the copper clad substrate 10 and has a rectangular shape.

In the second step, referring to FIG. 2, the first copper foil layer 11 and the second copper foil layer 12 are respectively formed into a first conductive circuit layer 110 and a second conductive circuit layer 120, the first conductive line. The layer 110 exposes a material corresponding to one side of the base layer 100 of the non-product region 101, and the second conductive wiring layer 120 exposes a material corresponding to the other side of the base layer 100 of the non-product region 101. The first conductive circuit layer 110 and the second conductive circuit layer 120 each have a plurality of conductive lines and a plurality of conductive contacts, and the first copper foil layer 11 and the second copper foil may be selectively chemically etched by an image transfer process. Formed by layer 12 It is also possible to selectively ablate the first copper foil layer 11 and the second copper foil layer 12 by laser.

In the present technical solution, before the first conductive circuit layer 110 and the second conductive circuit layer 120 are formed, the copper-clad substrate 10 at the product area 102 is drilled to form at least one through hole (not shown). And forming a conductive layer on the hole wall of the through hole by electroless plating and electroplating technology to make the through hole into a via hole, thereby electrically conducting the first conductive circuit layer 110 and the second conductive circuit layer 120.

In the third step, referring to FIG. 3, the material corresponding to the base layer 100 of the non-product area 101 is removed, so that a receiving through hole 103a is formed in the base layer 100. The receiving through hole 103 a sequentially penetrates the first conductive wiring layer 110 , the base layer 100 , and the second conductive wiring layer 120 . Thus, a core circuit substrate 10a having the receiving through hole 103a can be obtained. Preferably, in the present embodiment, the material corresponding to the base layer 100 of the non-product region 101 is removed by a laser cutting method.

In the fourth step, referring to FIG. 4, the first film 15 and the first pressed substrate 13 are pressed on the first conductive circuit layer 110 side of the core circuit substrate 10a, and the second conductive line on the core circuit substrate 10a. The second layer of the substrate 14 is pressed against the side of the layer 120. The first film 15 is a low-flow prepreg and has a film opening 151 corresponding to the receiving through hole 103a. The first press-bonding substrate 13 includes a first bonding layer 131 and a third copper foil layer 133 which are bonded together. The first bonding layer 131 is located between the first film 15 and the third copper foil layer 133. The second press-fit substrate 14 includes a second adhesive layer 141 and a fourth copper foil layer 143 that are bonded together. The second bonding layer 141 is located between the core circuit substrate 10a and the fourth copper foil layer 143. That is, the first film 15 and the first pressing substrate 13 are sequentially disposed on the surface of the first conductive circuit layer 110 such that the first bonding layer 131 is located between the first film 15 and the third copper foil layer 133; A second pressing substrate is placed on the surface of the second conductive circuit layer 120 14. The second bonding layer 141 is located between the core circuit substrate 10a and the fourth copper foil layer 143; and the first pressing substrate 13, the first film 15, and the core are pressed together by a press machine. The layer circuit board 10a and the second pressure board 14 are provided. It should be noted that since the first film 15 is a low-flow prepreg, the fluidity of the first film 15 is low at the time of pressing, so that the molten first bonding layer 131 and the molten first can be effectively prevented. The two bonding layers 141 are bonded together.

In the fifth step, referring to FIG. 5, the third copper foil layer 133 is formed into the third conductive wiring layer 130, and the fourth copper foil layer 143 is formed into the fourth conductive wiring layer 140. The third conductive wiring layer 130 exposes a material corresponding to the first adhesive layer 131 of the non-product region 101. The manufacturing method of the third conductive circuit layer 130 and the fourth conductive circuit layer 140 is similar to that of the first conductive circuit layer 110 and the second conductive circuit layer 120, and details are not described herein again.

In the present technical solution, before the third conductive wiring layer 130 and the fourth conductive wiring layer 140 are formed, the first pressing substrate 13 and the first film 15 at the product area 102 are drilled to form at least one only A first blind hole penetrating through the first pressing substrate 13 and the first film 15 is drilled in the second pressing substrate 14 to form at least one second blind hole penetrating only the second pressing substrate 14 at the first pressure. The substrate 13 , the core circuit board 10 a and the second press substrate 14 are drilled to form a plurality of through holes that sequentially penetrate the first press substrate 13 , the core circuit substrate 10 a and the second press substrate 14 and pass through The electroless plating and electroplating technology makes the first blind via hole into a first blind via hole (not shown), the second blind via hole as a second blind via hole (not shown), and the plurality of via holes are made into a plurality of via holes. 104, 105. The first blind via hole may electrically conduct the first conductive wiring layer 110 and the third conductive wiring layer 130. The second blind via hole can electrically conduct the second conductive wiring layer 120 and the fourth conductive wiring layer 140. Each of the via holes 104 is located between the plurality of via holes 105 and the receiving via holes 103a. That is, the plurality of via holes 104 surround the receiving via hole 103a, and the plurality of via holes 105 surrounds the plurality of vias 104. The plurality of via holes 104 , 105 may electrically conduct the third conductive wiring layer 130 and the fourth conductive wiring layer 140 .

The third conductive circuit layer 130 includes a plurality of first pads 135, a plurality of first pads 137, and a plurality of conductive lines (not shown). Each of the first pads 135 is located between the plurality of first pads 137 and a material corresponding to the first bonding layer 131 of the receiving vias 103a. That is, the plurality of first pads 135 surround the receiving vias 103a, and the plurality of first pads 137 surround the plurality of first pads 135. The plurality of first pads 135 are in one-to-one correspondence with the plurality of via holes 104 , and the plurality of first pads 137 are in one-to-one correspondence with the plurality of via holes 105 .

The fourth conductive circuit layer 140 includes a plurality of electrical contact pads 145 , a plurality of electrical contact pads 147 , and conductive traces 149 . Each of the electrical contact pads 145 is located between the plurality of electrical contact pads 147 and a material corresponding to the fourth conductive wiring layer 140 of the receiving vias 103a. That is, the plurality of electrical contact pads 145 surround the receiving vias 103a, and the plurality of electrical contact pads 147 surround the plurality of electrical contact pads 145. The plurality of electrical contact pads 145 are in one-to-one correspondence with the plurality of first pads 135, and each of the electrical contact pads 145 is electrically connected to the first pad 135 corresponding thereto through one via hole 104. The plurality of electrical contact pads 147 are in one-to-one correspondence with the plurality of first pads 137, and each of the electrical contact pads 147 is electrically connected to the first pad 137 corresponding thereto through a via hole 105.

In the technical solution, after the third conductive circuit layer 130 and the fourth conductive circuit layer 140 are formed, a first solder resist layer 170 is further disposed on the third conductive circuit layer 130, and is disposed on the fourth conductive circuit layer 140. The second solder resist layer 180. The first solder resist layer 170 covers the plurality of conductive lines of the third conductive wiring layer 130 and covers the surface of the first adhesive layer 131 located at the product region 102 exposed from the third conductive wiring layer 130 while exposing a plurality of The first pads 135, 137 and the surface of the first bonding layer 131 corresponding to the receiving via 103a. The second solder resist layer 180 covers the plurality of conductive lines of the fourth conductive circuit layer 140 149, and covering the surface of the second bonding layer 141 exposed from the fourth conductive wiring layer 140 while exposing a plurality of electrical contact pads 145, 147. The first solder resist layer 170 and the second solder resist layer 180 may be formed by printing or may be formed by lamination.

In the technical solution, after the first solder resist layer 170 and the second solder resist layer 180 are formed, a nickel gold layer is formed on the surface of each of the plurality of electrical contact pads 145, 147 (Fig. Not shown), in order to enhance the electrical connection between the plurality of electrical contact pads 145, 147 and the subsequently described first semiconductor wafer 21 and third semiconductor wafer 22. A plurality of nickel gold layers may be formed by processes such as electroless nickel plating, electroplating nickel gold, and electroless nickel plating.

In the sixth step, referring to FIG. 6, the material corresponding to the first adhesive layer 131 of the receiving through hole 103a is removed to form a receiving groove 103, and the receiving groove 103 is exposed corresponding to the receiving through hole. The material of the second bonding layer 141 of 103a. Thus, a first circuit carrier 20 having a receiving recess 103 is obtained.

The first circuit carrier 20 having the receiving recess 103 obtained according to the above steps, as shown in FIG. 6, includes a third conductive wiring layer 130, a first bonding layer 131, a first film 15, and a core layer which are sequentially pressed together. The circuit board 10a, the second bonding layer 141, and the fourth conductive wiring layer 140. The core layer circuit substrate 10a includes a second conductive wiring layer 120, a base layer 100, and a first conductive wiring layer 110 which are sequentially bonded. The first to fourth conductive circuit layers 110 to 140 are electrically conducted through the via holes 104, 105, the first blind via, and the second blind via. The receiving recess 103 extends only through the third conductive circuit layer 130, the first adhesive layer 131, the first film 15 and the core circuit substrate 10a, so that the surface of the second adhesive layer 141 corresponding to the receiving through hole 103a is exposed to the receiving surface. In the groove 103. The receiving groove 103 is configured to receive the flip chip described later, so that the flip chip does not occupy the external space. .

In the seventh step, referring to FIG. 7, the first semiconductor wafer 21 and the third semiconductor wafer 22 are mounted on the first circuit carrier 20 away from the receiving by a wire bonding technique, a surface mounting technology, or a flip chip packaging technology. The groove 103 is on one side such that the first semiconductor wafer 21 is located between the first circuit carrier 20 and the third semiconductor wafer 22. The first semiconductor wafer 21 may include a memory wafer, a logic wafer, or a digital wafer. In this embodiment, the first semiconductor wafer 21 is a logic wafer that is mounted on the first circuit carrier 20 by a wire bonding technique. The first semiconductor wafer 21 has a plurality of electrical contact pads 211 that are in one-to-one correspondence with the plurality of electrical contact pads 145. Each of the electrical contact pads 211 is electrically connected to a corresponding electrical contact pad 145 by a bonding wire 213 (eg, a gold wire). The third semiconductor wafer 22 can be a wafer such as a memory wafer, a logic wafer, or a digital wafer. In the embodiment, the third semiconductor wafer 22 is a memory wafer that is mounted on the first circuit carrier 20 by a wire bonding technique. The third semiconductor wafer 22 has a plurality of electrical contact pads 221 that are in one-to-one correspondence with the plurality of electrical contact pads 147. Each of the electrical contact pads 221 is electrically connected to a corresponding electrical contact pad 147 via a bonding wire 223 (eg, a gold wire). Preferably, in order to prevent signal interference between the first semiconductor wafer 21 and the third semiconductor wafer 22, a spacer 23 is further disposed between the first semiconductor wafer 21 and the third semiconductor wafer 22. It will be understood by those skilled in the art that the spacer 23 is not a necessary technical feature of the present technical solution. Even if the spacer 23 is omitted, the third semiconductor wafer 22 can be disposed on the first semiconductor wafer 21.

Next, the encapsulant 24 is disposed on the side of the first circuit carrier 20 away from the receiving recess 103 by a molding technique. The encapsulant 24 covers the first semiconductor wafer 21, the third semiconductor wafer 22, and the first semiconductor wafer 21 and a surface of the first circuit carrier 20 exposed by the third semiconductor wafer 22 to protect the first semiconductor wafer 21 and the third semiconductor wafer 22 from damage. The material of the encapsulant 24 is an epoxy molding compound. In this embodiment, the cross-sectional area of the encapsulant 24 is the same as the cross-sectional area of the first circuit carrier 20.

In an eighth step, referring to FIG. 8, a conductive paste 25 is formed on a surface of each of the plurality of first pads 135, 137, thereby forming a first package device 200. The material of the conductive paste 25 is generally mainly composed of tin and can be produced by a printing process.

In the ninth step, as shown in FIG. 9, a second package device 300 is disposed on one side of the plurality of conductive pastes 25 of the first package device 200, thereby forming a stacked structure 400. The second package device 300 includes a second circuit carrier 31, a second semiconductor wafer 33 mounted on the second circuit carrier 31, and a second circuit carrier 31 on the second semiconductor wafer 33. The bottom filler 35 is between. The second semiconductor wafer 33 is received in the receiving recess 103.

The second circuit carrier 31 may be a single-sided circuit board, a double-sided circuit board or a multi-layer circuit board formed with a conductive pattern, and includes a base layer 311, a first conductive line pattern 312, a second conductive line pattern 313, and a third protection The solder layer 314, the fourth solder resist layer 315, and the plurality of solder balls 317.

The base layer 311 is a multi-layer substrate including a plurality of layer resin layers and a plurality of layer conductive line patterns (not shown) alternately arranged. The base layer 311 has opposite upper side surfaces 311a and lower side surfaces 311b. The first conductive line pattern 312 is disposed on the upper side surface 311a. The second conductive line pattern 313 is disposed on the lower side surface 311b. The plurality of layers of the conductive line patterns of the base layer 311 and the plurality of layers of the conductive layer pattern of the base layer 311 and the first conductive line pattern 312 and the second conductive line pattern 313 respectively pass through the conductive holes (not shown) Show) electrical connection.

The third solder resist layer 314 covers a portion of the first conductive trace pattern 312 and an upper side surface 311a exposed from the first conductive trace pattern 312, such that a portion of the first conductive trace pattern 312 is removed from the third solder resist layer The 314 is exposed to form a plurality of electrical connection pads 3121 and a plurality of second pads 3122 and 3123. That is, the plurality of electrical connection pads 3121 and the plurality of second pads 3122, 3123 are all part of the first conductive line pattern 312. That is, the plurality of electrical connection pads 3121 and the plurality of second pads 3122, 3123 are exposed on the same side of the second circuit carrier 31 and are in the same plane. The plurality of electrical connection pads 3121 are arranged in an array, and the plurality of second pads 3122 are disposed around the plurality of electrical connection pads 3121 , and the plurality of second pads 3123 surround the plurality of second pads 3122 . That is, the plurality of second pads 3122 are disposed around the plurality of electrical connection pads 3121, and the plurality of second pads 3123 are disposed around the plurality of second pads 3122. The plurality of second pads 3122 are in one-to-one correspondence with the plurality of first pads 135, and each of the second pads 3122 is adjacent to the conductive paste 25 on the first pad 135 corresponding thereto to pass the plurality of first pads. The conductive paste 25 on the disk 135 electrically conducts the first semiconductor wafer 21 and the second circuit carrier 31. The plurality of second pads 3123 are in one-to-one correspondence with the plurality of first pads 137, and each of the second pads 3123 is adjacent to the conductive paste 25 on the first pad 137 corresponding thereto to pass the plurality of first pads. The conductive paste 25 on the disk 137 electrically conducts the third semiconductor wafer 22 and the second circuit carrier 31.

The fourth solder resist layer 315 covers a portion of the second conductive trace pattern 313 and a lower side surface 311b exposed from the second conductive trace pattern 313, so that a portion of the second conductive trace pattern 313 is removed from the fourth solder resist layer The 315 is exposed to form a plurality of second pads 3131. The plurality of second pads 3131 are arranged in an array. The plurality of electrical connection pads 3121 and the plurality of second pads 3122, 3123 pass through the first conductive line pattern 312 and the second conductive line pattern The conductive trace pattern and the conductive vias in the 313 and the underlying layer 311 are electrically connected to the plurality of second pads 3131.

The second semiconductor wafer 33 is packaged on the side of the third solder resist layer 314 of the second circuit carrier 31. In the present embodiment, the second semiconductor wafer 33 is mounted on the second circuit carrier 31 by a flip chip packaging technique. The second semiconductor wafer 33 has a plurality of electrical connection pads (not shown) corresponding to the plurality of electrical connection pads 3121. The electrical connection pads 3121 and the corresponding electrical connection pads pass through the conductive blind holes 331. Electrical connection. It can be understood that the conductive blind hole 331 can be a solder ball or a copper paste, or a metal conductive pillar and a solder ball can be combined with each other, or a copper paste and a copper conductive blind hole can be combined with each other.

A plurality of solder balls 317 are formed one by one on the plurality of second pads 3131.

The underfill 35 is disposed between the second semiconductor wafer 33 and the third solder resist layer 314 to firmly bond the second semiconductor wafer 33 with the first conductive trace pattern 312 to enhance the reliability of the second package device 300. The filling of the underfill 35 is performed by capillary action to penetrate the material of the liquid underfill 35 from the edge of the second semiconductor wafer 33 to the inner region between the second semiconductor wafer 33 and the third solder resist layer 314. The underfill 35 is typically made of an epoxy resin such as the underfill material Loctite 3536.

In the tenth step, referring to FIG. 10, the stack structure 400 is reflowed to melt and cure the conductive paste 25 between the adjacent first package device 200 and the second package device 300, thereby The plurality of first pads 135, 137 of the first package device 200 are respectively soldered integrally with the plurality of second pads 3122, 3123 of the second package device 300 in one-to-one correspondence by the conductive paste 25. Thus, a stacked package structure 500 is obtained.

The stacked package structure 500 includes the first package device 200 and the second package device 300 soldered together. The first package device 200 and the second package device 300 The structure is as described above Specifically, the first package device 200 includes a first circuit carrier 20 and a first semiconductor wafer 21 and a third semiconductor wafer 22 mounted on the first circuit carrier 20. The first circuit carrier 20 has a plurality of first pads 135 and a plurality of first pads 137. The plurality of first pads 135 and the plurality of first pads 137 are exposed on the same side of the first circuit carrier 20. A conductive paste 25 is formed on each of the plurality of first pads 135 and the plurality of first pads 137. The first circuit carrier 20 further has a receiving recess 103. The receiving groove 103 and the plurality of first pads 135 are located on the same side of the first circuit carrier 20 , and each of the first pads 135 is located in the receiving groove 103 and the plurality of first pads Between 137. That is, a plurality of first pads 135 surround the receiving recesses 103, and a plurality of first pads 137 surround the plurality of first pads 135. The receiving groove 103 is recessed from a side of the plurality of first pads 135 of the first circuit carrier 20 toward a side of the plurality of first pads 135 away from the first circuit carrier 20 . The second package device 300 includes a second circuit carrier 31 and a second semiconductor wafer 33 mounted on the second circuit carrier 31. The second circuit carrier 31 has a plurality of exposed electrical connection pads 3121, a plurality of second pads 3122, and a plurality of second pads 3123. The plurality of electrical connection pads 3121, the plurality of second pads 3122, and the plurality of second pads 3123 are exposed on the same side of the second circuit carrier 31. The plurality of second pads 3122 are in one-to-one correspondence with the plurality of first pads 135, and each of the second pads 3122 passes through the conductive paste 25 on the corresponding first pad 135 and the corresponding first pad. 135 welding as one. The plurality of second pads 3123 are in one-to-one correspondence with the plurality of first pads 137, and each of the second pads 3123 passes through the conductive paste 25 on the corresponding first pad 137 and the corresponding first pad. 137 welding as one. The second semiconductor wafer 33 is mounted on the plurality of electrical connection pads 3121 and received in the receiving recess 103 (ie, the receiving recess 103 surrounds the second semiconductor wafer 33).

In the stacked package structure 500, due to the second semiconductor crystal of the second package device 300 The sheet 33 is mounted on the exposed electrical connection pad 3121 and received in the receiving recess 103 of the first package device 200, thereby not only reducing the difficulty of constructing the second semiconductor wafer 33, but also improving the package structure. The package efficiency of 500 is reduced, and the height of the package structure 500 is reduced, and the volume of the package structure 500 is reduced. In addition, since the second semiconductor wafer 33 is mounted on the exposed electrical connection pad 3121, the second semiconductor wafer 33 is mounted on the second circuit carrier having the receiving groove compared to the prior art. The technical solution of the bottom of the receiving recess, the mounting method of the second semiconductor wafer 33 in the present technical solution also reduces the difficulty of providing the underfill 35 between the second semiconductor wafer 33 and the second circuit carrier 31. The reliability of the second package device 300 is improved, thereby improving the reliability of the package package structure 500 having the second package device 300.

Those skilled in the art can understand that the encapsulant 24 can further package a package device away from the surface of the first circuit carrier 20 to form a package structure having three, four or more package devices. .

Of course, those skilled in the art can also understand that in addition to fabricating a four-layer circuit board having one recess, the present technical solution can fabricate a multilayer circuit board of any number of layers. For example, the film and the copper foil are continuously added on both sides of the first circuit carrier 20 shown in Fig. 10, and then a multilayer circuit board having four or more layers having grooves is formed in accordance with the methods of the fifth and sixth steps. Alternatively, for example, the film and the copper foil are continuously added to the third conductive circuit layer 130 side of the first circuit carrier 20 shown in FIG. 10, and then formed into a groove according to the fifth and sixth steps. Four or more layers of multi-layer boards. Alternatively, for example, the film and the copper foil are continuously added to the fourth conductive wiring layer 140 side of the first circuit carrier 20 shown in FIG. 10, and then the copper foil is selectively etched to form a conductive line pattern, thereby forming Four or more layers of grooves Circuit board.

Referring to FIG. 11 to FIG. 15 , a method for fabricating a first circuit carrier provided by the second embodiment of the present technical solution includes the following steps:

In the first step, referring to Fig. 3, a core circuit substrate 10a having a receiving through hole 103a obtained in the third step of the first embodiment is provided.

In the second step, referring to FIG. 11, a first film 15a and a first copper foil 63 are sequentially disposed on the upper side of the core circuit substrate 10a (ie, the first conductive wiring layer 110 side), and simultaneously on the core circuit substrate 10a. A second film 15b and a second copper foil piece 64 are sequentially disposed on the lower side (ie, the side of the second conductive wiring layer 120). The first film 15a and the second film 15b are both low-flow prepregs, and each film has a film opening 151a, 151b corresponding to the receiving through hole 103a.

Next, the first copper foil sheet 63, the first film 15a, the core layer circuit substrate 10a, the second film 15b, and the second copper foil sheet 64 are press-bonded by a press machine at a time. It should be noted that since the first film 15a and the second film 15b are both low-flow prepregs, the first film 15a and the second film 15b have low fluidity during pressing, so that melting can be effectively prevented. The first film 15a is bonded to the molten second film 15b.

Referring to FIG. 12, the first copper foil piece 63 is formed into a third conductive circuit layer 630. The third conductive circuit layer 630 covers the receiving through hole 103a, and the second copper foil piece 64 is formed into a fourth conductive circuit layer. 640, the fourth conductive circuit layer 640 covers the receiving through hole 103a.

In the technical solution, before the third conductive circuit layer 630 and the fourth conductive circuit layer 640 are formed, the first copper foil 63 and the first film 15a at the product area 102 are drilled to form at least one a first blind via hole penetrating the first copper foil sheet 63 and the first film 15a, and forming a first blind via hole by electroless plating and electroplating technology (Fig. The first blind via hole can electrically conduct the first conductive circuit layer 110 and the third conductive circuit layer 630; and is further drilled in the second copper foil piece 64 and the second film 15b at the product area 102 to form a hole. At least one second blind hole penetrating only the second copper foil piece 64 and the second film 15b, the second blind hole is made into a second blind via hole (not shown), and the second blind via hole can be electrically connected to the second hole Conductive wiring layer 120 and fourth conductive wiring layer 640.

Referring to FIG. 13, a first pressing substrate 65 is press-fitted on the third conductive wiring layer 630 side of the core circuit substrate 10a, and a first electrode is bonded to the fourth conductive wiring layer 640 side of the core circuit substrate 10a. The second substrate 66 is pressed. The first press-fit substrate 65 includes a bonded first adhesive layer 651 and a third copper foil layer 653. The first bonding layer 651 is located between the third conductive wiring layer 630 and the third copper foil layer 653. The second pressing substrate 66 includes a second bonding layer 661 and a fourth copper foil layer 663 which are bonded together. The second bonding layer 661 is located between the fourth conductive circuit layer 640 and the fourth copper foil layer 663. That is, the first pressing substrate 65 is placed on the surface of the third conductive circuit layer 630 such that the first bonding layer 651 is located between the third conductive wiring layer 630 and the third copper foil layer 653; and the fourth conductive circuit layer a second pressing substrate 66 is placed on the surface of the 640 such that the second bonding layer 661 is located between the fourth conductive wiring layer 640 and the fourth copper foil layer 663; and the first pressing is pressed once by a press machine. The substrate 65, the core layer circuit substrate 10a, and the second pressure bonding substrate 66. It should be noted that, since the third conductive circuit layer 630 and the fourth conductive circuit layer 640 both cover the receiving through hole 103a, the third conductive circuit layer 630 and the fourth conductive line are formed during pressing. The layer 640 can effectively prevent the molten first bonding layer 651 and the molten second bonding layer 661 from being bonded together.

Referring to FIG. 14, the third copper foil layer 653 is formed into a fifth conductive wiring layer 650, and the fourth copper foil layer 663 is formed into a sixth conductive wiring layer 660. The fifth conductive wiring layer 650 is exposed to correspond to the The material of the first adhesive layer 651 that accommodates the through hole 103a. Fifth guide The manufacturing method of the electric circuit layer 650 and the sixth conductive circuit layer 660 is similar to the manufacturing method of the first conductive circuit layer 110 and the second conductive circuit layer 120, and details are not described herein again.

In the technical solution, before the fifth conductive circuit layer 650 and the sixth conductive circuit layer 660 are formed, the third copper foil layer 653 and the first bonding layer 651 at the product area 102 are drilled to form at least one. Only the third blind hole of the third copper foil layer 653 and the first adhesive layer 651 is penetrated, and the third blind via hole is formed into a third blind via hole (not shown) by electroless plating and electroplating technology, and the third blind guide is formed. The hole may electrically conduct the fifth conductive circuit layer 650 and the third conductive circuit layer 630; further drill holes in the fourth copper foil layer 663 and the second adhesive layer 661 at the product region 102 to form at least one through only the fourth copper a fourth blind via of the foil layer 663 and the second adhesive layer 661, the fourth blind via is formed as a fourth blind via (not shown), and the fourth blind via can electrically conduct the sixth conductive trace layer 660 and the fourth The conductive circuit layer 640 further defines a plurality of through holes penetrating through the first pressing substrate 65, the core layer circuit substrate 10a and the second pressing substrate 66 at the product region 102, and the plurality of through holes are formed into a plurality of via holes 601. 603. Each of the via holes 601 is located between the plurality of via holes 603 and the receiving via holes 103a. That is, the plurality of vias 601 surround the receiving vias 103a, and the plurality of vias 603 surround the plurality of vias 605. The plurality of via holes 601, 603 can electrically conduct the fifth conductive wiring layer 650 and the sixth conductive wiring layer 660.

The fifth conductive circuit layer 650 includes a plurality of first pads 655, a plurality of first pads 657, and a plurality of conductive lines (not shown). Each of the first pads 655 is located between the plurality of first pads 657 and a material corresponding to the first bonding layer 651 of the receiving vias 103a. That is, the plurality of first pads 655 surround the receiving vias 103a, and the plurality of first pads 657 surround the plurality of first pads 655. The plurality of first pads 655 are in one-to-one correspondence with the plurality of via holes 601, and the plurality of first pads 657 are in one-to-one correspondence with the plurality of via holes 603.

The sixth conductive circuit layer 660 includes a plurality of electrical contact pads 665 and a plurality of electrical contact pads. 667 and conductive line 669. Each of the electrical contact pads 665 is located between the plurality of electrical contact pads 667 and the material of the second bonding layer 661 corresponding to the receiving vias 103a. That is, a plurality of electrical contact pads 665 surround the receiving vias 103a, and a plurality of electrical contact pads 667 surround the plurality of electrical contact pads 665. The plurality of electrical contact pads 665 are in one-to-one correspondence with the plurality of first pads 655, and each of the electrical contact pads 665 is electrically connected to the first pad 655 corresponding thereto through one via hole 601. The plurality of electrical contact pads 667 are in one-to-one correspondence with the plurality of first pads 657, and each of the electrical contact pads 667 is electrically connected to the first pad 657 corresponding thereto through a via hole 603.

In the present technical solution, after the fifth conductive circuit layer 650 and the sixth conductive circuit layer 660 are formed, a first solder resist layer 670 is further disposed on the fifth conductive circuit layer 650, and is disposed on the sixth conductive circuit layer 660. The second solder mask layer 680. The first solder resist layer 670 covers the plurality of conductive traces of the fifth conductive trace layer 650 and covers the surface of the first adhesive layer 651 located at the product region 102 exposed from the fifth conductive trace layer 650 while exposing a plurality of The first pads 655, 657 and the surface of the first bonding layer 651 corresponding to the receiving vias 103a. The second solder resist layer 680 covers the plurality of conductive traces 669 of the sixth conductive trace layer 660 and covers the surface of the second adhesive layer 661 exposed from the sixth conductive trace layer 660 while exposing the plurality of electrical contact pads 665 667. The first solder resist layer 670 and the second solder resist layer 680 may be formed by printing or may be formed by lamination. In the technical solution, after the first solder resist layer 670 and the second solder resist layer 680 are formed, a nickel gold layer is formed on each of the plurality of electrical contact pads 665, 667 (not shown). In order to enhance the electrical connection between the electrical contact pads 665, 667 and the subsequently described first semiconductor wafer 21 and third semiconductor wafer 22. The nickel gold layer can be formed by a chemical nickel gold process, an electroplated nickel gold process, or a immersion nickel plating process.

In the sixth step, referring to FIG. 15, the material corresponding to the first bonding layer 651 of the receiving via 103a and the copper corresponding to the third conductive wiring layer 630 of the receiving via 103a are removed to form a receiving recess 607. . The receiving groove 607 exposes a fourth conductive circuit layer 640 corresponding to the receiving through hole 103a. Thus, a first circuit carrier 60 having a receiving recess 607 is obtained.

As shown in FIG. 8 , the first circuit carrier 20 having the receiving recess 607 according to the above steps includes a fifth conductive circuit layer 650, a first adhesive layer 651, and a third conductive circuit layer 630 which are sequentially pressed together. The first film 15a, the core layer circuit substrate 10a, the second film 15b, the fourth conductive wiring layer 640, the second bonding layer 661, and the sixth conductive wiring layer 660. The first conductive circuit layer 110, the second conductive circuit layer 120, the third conductive circuit layer 630, the fourth conductive circuit layer 640, the fifth conductive circuit layer 650, and the sixth conductive circuit layer 660 pass through vias 601, 603, The first to fourth blind vias are electrically conducted. The receiving groove 607 extends only through the fifth conductive circuit layer 650, the first adhesive layer 651, the third conductive circuit layer 630, the first film 15a, the core circuit substrate 10a and the second film 15b, so that the fourth conductive line The layer 640 is exposed in the receiving recess 607. The receiving recess 607 is configured to receive the flip chip described later, so that the flip chip does not occupy the external space.

It should be noted that a first method of the seventh step to the tenth step in the first embodiment may be used to construct the first semiconductor wafer 21 on the first circuit carrier 60 having the receiving recess 607. a third semiconductor wafer 22, and forming a conductive paste on a surface of each of the plurality of first pads 655, 657 by a printing process to obtain a first package device, and then the first package device and the second package The device 300 is stacked and reflowed to obtain a stacked package structure. The second semiconductor wafer 33 in the stacked package structure is surrounded by the receiving recess 607 of the first circuit carrier 60.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

135, 137‧‧‧ first pad

103‧‧‧ receiving groove

24‧‧‧Package colloid

25‧‧‧Electrical paste

20‧‧‧First circuit carrier

Claims (14)

A method of fabricating a package structure comprising the steps of: providing a first package device, the first package device comprising a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier, The first circuit carrier is provided with a receiving recess, the first circuit carrier further has a plurality of exposed first pads, and the plurality of first pads and the receiving recess are located on the first circuit The same side of the board, and a plurality of first pads surround the receiving recess, and a surface of each of the first pads is formed with a conductive paste; and is disposed on a plurality of first pads of the first package device a second package device to form a stacked structure, the second package device comprising a second circuit carrier and a second semiconductor wafer mounted on the second circuit carrier, the second circuit carrier Having a plurality of exposed second pads and a plurality of electrical connection pads, wherein the plurality of second pads are in one-to-one correspondence with the plurality of first pads, and each of the second pads is adjacent to the corresponding one a conductive paste on a pad, the plurality of electrical connections And the plurality of second pads are located on the same side of the second circuit carrier, the second semiconductor wafer is mounted on the plurality of electrical connection pads, and is received in the receiving recess; and curing Conductive pastes on the first pads such that each of the second pads is soldered integrally with the corresponding first pads through the cured conductive paste, thereby soldering the second packaged device to the first circuit carrier A plurality of first pad sides form a stacked package structure. The method of fabricating a package structure according to claim 1, wherein the first semiconductor wafer and the plurality of first pads are located on opposite sides of the first circuit carrier, the first package device The forming method includes the steps of: providing the first circuit carrier; and the first semiconductor by wire bonding technology, surface mount technology or flip chip packaging technology Forming a wafer on the side of the first circuit carrier away from the plurality of first pads; and forming the conductive paste on a surface of each first pad by a printing method to obtain the first package device . The method of fabricating a package structure according to claim 2, wherein the first circuit carrier is a circuit carrier having four conductive circuit layers, and the method for forming the first circuit carrier includes the steps of: providing a circuit carrier a copper-clad substrate comprising a first copper foil layer, a base layer and a second copper foil layer which are sequentially bonded, the copper-clad substrate having a non-product area and a surrounding and surrounding the non-product area a product area; the first copper foil layer and the second copper foil layer are respectively formed into a first conductive circuit layer and a second conductive circuit layer, wherein the first conductive circuit layer exposes a substrate corresponding to the non-product area a material on one side of the layer, the second conductive wiring layer exposing material corresponding to the other side of the base layer of the non-product area; removing material corresponding to the base layer of the non-product area to obtain a containment a core circuit substrate of the through hole, the core circuit substrate includes a first conductive circuit layer, a base layer and a second conductive circuit layer which are sequentially bonded, and the receiving through holes sequentially penetrate the first conductive circuit layer and the substrate Layer and second conductivity a circuit layer; a first film and a first pressing substrate are pressed on a side of the first conductive circuit layer of the core circuit substrate, and a second is pressed on a second conductive circuit layer side of the core circuit substrate Pressing the substrate, the first film is a low flow prepreg, and has a film opening corresponding to the receiving through hole, the first pressing substrate comprises a first bonding layer and a third copper layer The first bonding layer is located between the first film and the third copper foil layer, and the second pressing substrate comprises a second bonding layer and a fourth copper foil layer, the second bonding layer Located between the core circuit substrate and the fourth copper foil layer; forming the third copper foil layer and the fourth copper foil layer into a third conductive circuit layer and a fourth conductive line, respectively a road layer, the third copper foil layer exposing material of the first bonding layer in the non-product area; and removing material corresponding to the first bonding layer of the non-product area to obtain the first circuit Carrier board. The method of fabricating a package structure according to claim 2, wherein the first circuit carrier is a circuit carrier having six conductive circuit layers, and the method for forming the first circuit carrier includes the steps of: providing a a copper-clad substrate comprising a first copper foil layer, a base layer and a second copper foil layer which are sequentially bonded, the copper-clad substrate having a non-product area and a surrounding and surrounding the non-product area a product area; the first copper foil layer and the second copper foil layer are respectively formed into a first conductive circuit layer and a second conductive circuit layer, wherein the first conductive circuit layer exposes a substrate corresponding to the non-product area a material on one side of the layer, the second conductive wiring layer exposing material corresponding to the other side of the base layer of the non-product area; removing material corresponding to the base layer of the non-product area to obtain a containment a core circuit substrate of the through hole, the core circuit substrate includes a first conductive circuit layer, a base layer and a second conductive circuit layer which are sequentially bonded, and the receiving through holes sequentially penetrate the first conductive circuit layer and the substrate Layer and second conductivity a circuit layer; a first film and a first copper foil are pressed on a side of the first conductive circuit layer of the core circuit substrate, and a second is pressed on a second conductive circuit layer side of the core circuit substrate a film and a second copper foil, the first film and the second film are both low-flow prepregs, and each has a film opening corresponding to the receiving through hole, the first film is located at the first Between the copper foil and the core circuit substrate, the film opening of the first film is in communication with the receiving through hole, and the second film is located between the second copper foil and the core circuit substrate. And the film opening of the second film is in communication with the receiving through hole; Forming the first copper foil piece and the second copper foil piece into a third conductive circuit layer and a fourth conductive circuit layer, respectively, the third conductive circuit layer covering the receiving through hole adjacent to the first film a side, the fourth conductive circuit layer covers a side of the receiving through hole adjacent to the second film; and a first pressing substrate is pressed on a side of the third conductive circuit layer of the core circuit substrate One side of the fourth conductive circuit layer of the core circuit substrate is pressed against a second pressing substrate, and the first pressing substrate includes a first bonding layer and a third copper foil layer, the first bonding layer The layer is located between the third conductive circuit layer and the third copper foil layer, the second pressure substrate comprises a second bonding layer and a fourth copper foil layer, and the second bonding layer is located at the Between the fourth conductive circuit layer and the fourth copper foil layer; the third copper foil layer and the fourth copper foil layer are respectively formed into a fifth conductive circuit layer and a sixth conductive circuit layer, the fifth conductive line The layer exposes a material corresponding to the first adhesive layer of the receiving through hole; and the removing corresponds to the receiving Material of the first adhesive layer and the first through-holes of the copper foil, to obtain the first circuit board carrier. The method of fabricating a package structure according to claim 1, wherein the first semiconductor wafer and the plurality of first pads are respectively located on opposite sides of the first circuit carrier, the first circuit carrier The method further includes a plurality of via holes and a plurality of exposed electrical contact pads corresponding to the plurality of via holes, wherein the plurality of via holes are in one-to-one correspondence with the plurality of first pads, and the plurality of conductive contact pads are The first pads are respectively located on opposite sides of the first circuit carrier, and a plurality of electrical contact pads surround the first semiconductor wafer, and each of the electrical contact pads passes through a via and a corresponding first pad When the first semiconductor wafer is mounted on the first circuit carrier, the first semiconductor wafer is electrically connected to the first circuit carrier through a plurality of electrical contact pads. The method of fabricating a package structure according to claim 1, wherein the first package device further comprises an encapsulant covering the first semiconductor wafer, a cross-sectional area of the encapsulant and a first circuit carrier The first semiconductor wafer and the plurality of first solders have the same cross-sectional area The disks are located on opposite sides of the first circuit carrier. The method of fabricating a package structure according to claim 1, wherein the second package device further comprises an underfill disposed between the second semiconductor wafer and the second circuit carrier. A stacked package structure comprising: a first package device, the first package device comprising a first circuit carrier and a first semiconductor wafer mounted on the first circuit carrier, the first circuit carrier a receiving recess is defined, the first circuit carrier further has a plurality of exposed first pads, and the plurality of first pads and the receiving recess are located on the same side of the first circuit carrier. a surface of each of the first pads is formed with a conductive paste; and a second package device comprising a second circuit carrier and a second semiconductor wafer mounted on the second circuit carrier The second circuit carrier has a plurality of exposed second pads, the second circuit carrier has a plurality of exposed second pads and a plurality of electrical connection pads, the plurality of second The pad is in one-to-one correspondence with the plurality of first pads, and each of the second pads is adjacent to the conductive paste on the corresponding first pad, the plurality of electrical connection pads and the plurality of second pads Located on the same side of the second circuit carrier, the second semiconductor wafer is mounted on the same A plurality of conductive pads, and received in the receiving recess. The package structure of claim 8, wherein the first circuit carrier comprises a core circuit substrate, and the core circuit substrate comprises a first conductive circuit layer, a base layer and a second conductive line which are sequentially bonded The first circuit carrier further includes a first bonding layer and a third conductive circuit layer which are sequentially pressed on one side of the first conductive circuit layer of the core circuit substrate, and are sequentially pressed into the core circuit. a second adhesive layer and a fourth conductive circuit layer on a side of the second conductive circuit layer of the substrate, wherein the receiving groove extends only through the third conductive circuit layer, the first adhesive layer, and the first film of the core circuit substrate Exposing the second bonding layer to the receiving recess, the third conductive wiring layer including the plurality of first pads. The package structure of claim 9, wherein the first bonding layer and the core layer circuit A first film is further disposed between the substrates, the first film is a low flow film, and the receiving groove extends through the first film. The stacked package structure of claim 8, wherein the first semiconductor wafer and the plurality of first pads are respectively located on opposite sides of the first circuit carrier, and the first circuit carrier further has And a plurality of exposed electrical contact pads corresponding to the plurality of conductive vias, wherein the plurality of vias are in one-to-one correspondence with the plurality of first pads, and the plurality of electrical properties of the first circuit carrier The contact pad and the plurality of first pads are respectively located on opposite sides of the first circuit carrier, and the plurality of electrical contact pads of the first circuit carrier surround the first semiconductor wafer, each first The electrical contact pads of the circuit carrier are electrically connected to the corresponding first pads through a via hole. When the first semiconductor wafer is mounted on the first circuit carrier, the first semiconductor wafer passes the A plurality of electrical contact pads of the first circuit carrier are electrically connected to the first circuit carrier. The package structure of claim 8, wherein the first package device further comprises an encapsulant covering the first semiconductor wafer, a cross-sectional area of the encapsulant and a cross-sectional area of the first circuit carrier Similarly, the first semiconductor wafer and the plurality of first pads are located on opposite sides of the first circuit carrier. The package package structure of claim 8, wherein the second package device is further provided with a plurality of solder balls on a side away from the first package device. The package package structure of claim 8, wherein the second package device further comprises an underfill disposed between the second semiconductor wafer and the second circuit carrier.