201225248 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種矽穿 孔晶片封裝構造與方法。 【先前技術】 在習知的多晶片堆疊封裝構造中，矽穿孔（Through Silicon Via)係為較為先進之技術，複數個具有矽穿孔之 半導體晶片垂直往上堆疊在一基板上，並利用銲料材質 之微凸塊達到晶片與晶片之間以及晶片至基板之間的電 性連接。相較於打線接合（Wire bonding)、使用晶背的重 配置線路層與銲球之覆晶結合（Flip_chip b〇nding)、金凸 塊接合（Gold to Gold interc〇nnecti〇n，GGI)，較能符合高 密度晶片堆疊與微小尺寸封裝之要求。 然而’習知石夕穿孔之製作係先在晶片内製作高深寬比 的貫穿孔，接著，填入一導電材料於貫穿孔中以構成矽 穿孔，並設置微凸塊（micr〇 bump)於晶片上，以微凸塊 焊接上下晶片之矽穿孔，達到晶片與晶片之間的電性連 接。然矽穿孔晶片在垂直堆疊的方式中易產生銲點斷裂 與矽穿孔定位困難的問題’使多晶片堆疊技術增高且複 雜。 如第1圖所示，為美國專利編號US 7,151，009 B2, 揭不一種習知矽穿孔晶片封裝構造ι〇〇，複數個晶片 立體堆疊在一基板丨丨〇上。 日曰片120具有複數個貫穿$ 石夕穿孔1 2 1，石夕穿不|〗9 1 rio 丄 穿孔21内填充有導電之孔内金屬以| 201225248 直導通晶片120内部。複數個微凸塊1 30配置在每一晶 片120之矽穿孔121下方，並在晶片12〇中央位置貼上 固體膠141，作為晶片間隙的維持，再將晶#】2〇立體 堆疊並覆晶接合至基板110之連接墊113上，使該些微 凸塊130與下方晶片12〇之矽穿孔i2i内的孔内金屬電 性連接，以達成晶片12〇之間的電性導通。在晶片堆疊 之後，晶片120間之側緣再填入流動膠丨42以保護微凸 春塊130。後續並以複數個銲球16〇設置在基板丨之外 接表面上以對外連接。因此，目前矽穿孔之作用僅在於 晶片内部的縱向導通，而在晶片120之間設有兩種膠： 固體膠141與流動膠142為必要，以避免晶片間隙内產 生氣泡，而造成微凸塊丨3〇的銲點斷裂。 習知矽穿孔晶片1 2〇在作垂直向立體堆疊時上方晶 片之微凸塊130須對準下方晶片之矽穿孔121，有對位 不易的問題。此外，晶片12〇在運算時會產生熱能，產 # 生的熱應力會使晶片120變形、翹曲與晶片間隙改變， 進而將應力集中到晶片120間之電性接點處（即微凸塊 130處），亦會導致銲點斷裂。 【發明内容】 有鑒於此，本發明之主要目的係在於提供一種矽穿孔 晶片封裝構造與方法’解決習知矽穿孔晶片堆疊時矽穿 孔對位不易的問題，使多晶片堆疊技術更為低成本且簡 化。 本發明之次—目的係在於提供一種矽穿孔晶片封裝 4 201225248 構造與方法，複數個具有矽穿孔之晶片為侧立於基板 上，以連續跳接打線的銲線串連多個矽穿孔晶片之上電 極面，可節省銲線數量，並且不會有習知矽穿孔晶片之 間微凸塊因銲點斷裂的電性連接失敗等問題。 本發明之再一目的係在於提供一種矽穿孔晶片封裝 構造與方法，能活用矽穿孔，以提供側向電極之連接作 用，達到節省製程成本及時間之功效。201225248 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a structure and method for a via-hole package. [Prior Art] In the conventional multi-wafer stacked package structure, the through silicon via is a relatively advanced technology, and a plurality of semiconductor wafers having germanium perforations are vertically stacked on a substrate and made of a solder material. The microbumps reach an electrical connection between the wafer and the wafer and between the wafer and the substrate. Compared to wire bonding, reconfigurable circuit layer using a crystal back and flip chip bonding (Flip_chip b〇nding), gold bump bonding (Gold to Gold interc〇nnecti〇n, GGI) Can meet the requirements of high density wafer stacking and small size packaging. However, the fabrication of the conventional Shixi perforation is to first make a high aspect ratio through hole in the wafer, and then fill a conductive material in the through hole to form a crucible perforation, and set a microbump to the wafer. Upper, the micro-bumps are used to solder the vias of the upper and lower wafers to achieve electrical connection between the wafer and the wafer. Then, the problem that the perforated wafer is liable to cause solder joint breakage and puncture perforation positioning in a vertically stacked manner has made the multi-wafer stacking technique more complicated and complicated. As shown in Fig. 1, U.S. Patent No. 7,151,009 B2, which discloses a conventional perforated wafer package structure, in which a plurality of wafers are three-dimensionally stacked on a substrate. The sundial piece 120 has a plurality of penetrating through the #石夕孔1 2 1, Shi Xi wearing not | 〗 9 1 rio 丄 The perforation 21 is filled with a conductive hole in the metal to | 201225248 Straight conduction through the inside of the wafer 120. A plurality of microbumps 1 30 are disposed under the via holes 121 of each of the wafers 120, and a solid glue 141 is attached to the center of the wafer 12 as a wafer gap, and the crystals are stacked and flipped. Bonded to the connection pads 113 of the substrate 110, the micro bumps 130 are electrically connected to the metal in the vias in the vias i2i of the lower wafer 12 to achieve electrical conduction between the wafers 12 . After the wafer is stacked, the side edges between the wafers 120 are refilled with flowing capsules 42 to protect the micro-bumps 130. Subsequently, a plurality of solder balls 16 are disposed on the external surface of the substrate to be externally connected. Therefore, at present, the effect of the perforation is only in the longitudinal conduction of the inside of the wafer, and two kinds of glue are provided between the wafers 120: the solid glue 141 and the flow glue 142 are necessary to avoid bubbles in the gap of the wafer, thereby causing microbumps. The solder joint of 丨3〇 is broken. It is known that the micro-bumps 130 of the upper wafer must be aligned with the turns of the wafers 121 of the lower wafer when the wafers are vertically stacked, which is difficult to align. In addition, the wafer 12 产生 generates thermal energy during the operation, and the thermal stress generated by the wafer causes the wafer 120 to be deformed, warped, and the wafer gap is changed, thereby concentrating the stress at the electrical contact between the wafers 120 (ie, the microbumps). 130)) will also cause the solder joint to break. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a 矽-perforated wafer package structure and method 'solving the problem that the boring and punching alignment is not easy when the conventional erbium wafer stack is stacked, and the multi-wafer stacking technology is lower in cost. And simplified. The present invention is directed to providing a crucible-perforated chip package 4 201225248 construction and method, in which a plurality of wafers having crucible perforations are laterally stacked on a substrate, and a plurality of perforated wafers are serially connected by wire bonding. The upper electrode surface can save the number of bonding wires, and there is no problem that the microbumps between the perforated wafers fail due to the breakage of the solder joints. It is still another object of the present invention to provide a crucible-perforated wafer package construction and method that utilizes the perforation of the crucible to provide the connection of the lateral electrodes, thereby saving process cost and time.
本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示·_财穿孔晶片封裝構造主 要包含-基板、複數個晶片以及一銲線。該基板係具有 第接♦曰。每一晶片係設有—第一矽穿孔，該第一石夕 穿孔係具有一上電極面，係顯露於所屬晶片之一第一切 割侧面，該些晶片係侧立設置於該基板上，並使該些上 電極面為朝向遠離該基板之方向。該銲線係跨過該些晶 片之上方並以連續跳接打線的方式接合該些上電極面至 該第一接指。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的矽穿孔晶片封裳構造中，該銲線在該些晶片 之上方的線段係可為波浪狀。 一在前述的石夕穿孔晶片封裝構造中，該基板係π更具有 一第二接指，該銲線之兩端係分料接至該第〆接指與 該第二接指。 在前述的石夕穿孔晶片封裝構造中，該基板係,<更具有 201225248 複數個連接墊，每一晶片係更設有一第二矽穿孔，該第 二矽穿孔係具有一下電極面’係顯露於所屬晶片之一第 二切割側面’利用銲料焊接該些下電極面至該些連接塾。 在前述的矽穿孔晶片封裝構造中，可另包含有一封膠 體’係形成於該基板上，以密封該些晶片與該銲線。 本發明還揭示適用於前述的一種矽穿孔晶片封裝方 法，首先，提供一晶圓，包含複數個晶片，每一晶片係 設有一延伸到切割道之第一矽穿孔。接著，沿切割道切 籲割該晶圓以分離該些晶片，同時形成該晶片之一第一切 割侧面以及該第一矽穿孔顯露於該第一切割側面之一上 電極面。之後，側立設置該些晶片於一基板上，並使該 些上t極面為朝向遠離該基板之方向，該基板係具有一 第/接私。最後，形成一銲線，該銲線係跨過該些晶片 之上方並以連續跳接打線的方式接合該些上電極面至該 第一接指。 Φ 由以上技術方案可以看出，本發明之矽穿孔晶片封裝 構造與方法’具有以下優點與功效： 一、 可藉由將晶片側立設置於基板上再以連續跳接打線 的方式接合晶片之上電極面至基板之接指作為其中 之一技術手段，解決習知垂直堆疊之矽穿孔晶片在 堆疊時矽穿孔對位不易的問題，使多晶片堆疊技術 更為低成本且簡化。 二、 可藉由將晶片側立設置於基板上再以連續跳接打線 的方式接合晶片之上電極面至基板之接指作為其中【 201225248 t一技術手&’能以連續跳接打'線的銲線串連多個 矽穿孔晶片之上電極面’可節省銲線數量，並且不 - 會有習知矽穿孔晶片之間微凸塊因銲點斷裂的電性 連接失敗等問題。 三、可藉由將晶片側立設置於基板上再以連續跳接打線 的方式接纟晶片之上電極面至基板之接指作為其中 之一技術手段，能以一銲線串連多個矽穿孔晶片， 以節省製程成本及時間。 •【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是’該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基.本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例綠製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處理，以提供更 •清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例，一種矽穿孔晶片封裝 構造與方法舉例說明於第2圖之截面示意圖、第3圖晶 片之俯視圖以及第4A至4D圖於製程中元件之截面示意 圖。該矽穿孔晶片封裝構造200主要包含一基板21〇、 複數個晶片2 2 0以及一銲線2 3 0。 如第2圖所示，該基板21〇係具一上表面211以及一 下表面2丨2。該基板210係可為一印刷電路板、—導線[ 201225248 架、一電路薄膜或各種晶 乃戰板。該基板210係作為連 接晶片之電性傳遞介面， J^ 種咼密度兩面導通之多 層印刷電路板，内都报士、 $成有線路或/與鍍通孔（圖未繪 出）。該上表面211#可供S yMga ^ 你』供日日片设置與堆疊，該下表面212The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses that the perforated wafer package structure mainly comprises a substrate, a plurality of wafers, and a bonding wire. The substrate has a first connection. Each of the wafers is provided with a first cymbal perforation having an upper electrode surface exposed on a first cutting side of one of the associated wafers, the wafers being laterally disposed on the substrate, and The upper electrode faces are oriented in a direction away from the substrate. The bonding wire extends over the plurality of wafers and joins the upper electrode faces to the first fingers in a continuous jumper wire. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing perforated wafer sealing structure, the line of the bonding wire above the wafers may be wavy. In the foregoing shi-shi-punched chip package structure, the substrate π further has a second finger, and the two ends of the bonding wire are connected to the second finger and the second finger. In the foregoing shixi perforated chip package structure, the substrate system, <more has 201225248 plurality of connection pads, each of the wafer systems further has a second 矽 perforation, the second 矽 perforation has a lower electrode surface ′ The lower electrode faces are soldered to the connection ports on one of the second cutting sides of the associated wafer. In the foregoing 矽-perforated wafer package structure, a further adhesive layer may be further formed on the substrate to seal the wafers and the bonding wires. The present invention also discloses a method of encapsulating a perforated wafer for use in the foregoing. First, a wafer is provided comprising a plurality of wafers, each wafer having a first perforation extending to the scribe line. Next, the wafer is cut along the scribe line to separate the wafers while forming a first cut side of the wafer and the first turn pleats are exposed on one of the first cut sides. Thereafter, the wafers are laterally disposed on a substrate, and the upper t-pole faces are oriented away from the substrate, and the substrate has a first/small interface. Finally, a bond wire is formed which spans over the wafers and engages the upper electrode faces to the first fingers in a continuous jumper wire. Φ As can be seen from the above technical solution, the 矽-perforated chip package structure and method of the present invention has the following advantages and effects: 1. The wafer can be bonded to the substrate by standing on the substrate side by side jumper bonding. The connection of the upper electrode surface to the substrate is one of the technical means to solve the problem that the conventional vertically stacked tantalum perforated wafer is difficult to align the puncturing and aligning, which makes the multi-wafer stacking technology more cost-effective and simplified. 2. The wafer can be placed on the substrate side by side and then the electrode surface of the wafer can be bonded to the substrate by continuous jumper bonding. [201225248 t-Technology Hand & can be continuously jumped. The wire bonding wires of the wire are connected in series with the electrode faces of the plurality of perforated wafers to save the number of bonding wires, and there is no problem that the microbumps between the perforated wafers fail due to the breakage of the solder joints. 3. By placing the wafer sideways on the substrate and then connecting the electrode surface of the wafer to the substrate by continuous jumper wire bonding, as one of the technical means, a plurality of wires can be connected in series by a wire bond. Punch the wafer to save process cost and time. [Embodiment] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The method is implemented, so only the components and combinations related to the case are shown. The components shown in the figure are not in the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or It is a simplified process to provide a more clear description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a perforated wafer package construction and method is illustrated in a cross-sectional view in Fig. 2, a top view of the wafer in Fig. 3, and a cross-sectional view of the elements in the process of Figs. 4A through 4D. The 矽-perforated wafer package structure 200 mainly includes a substrate 21 〇, a plurality of wafers 2 2 0 , and a bonding wire 2 30 . As shown in Fig. 2, the substrate 21 has an upper surface 211 and a lower surface 2丨2. The substrate 210 can be a printed circuit board, a wire [201225248 frame, a circuit film or various crystal warfare boards. The substrate 210 is used as an electrical transmission interface for connecting the wafers, and the multi-layer printed circuit board with the two sides of the density is electrically connected, and the inside of the substrate is provided with a line or a plated through hole (not shown). The upper surface 211# is available for S yMga ^ for the Japanese day sheet setting and stacking, the lower surface 212
係可供對外表面接合。具體而言，該基板⑴之該上表 面2U係具有一第-接指213。該第-接指213係可由 :電金屬材質，如鋁、銅、鋁合金或與銅合金之中的任 者所製成’作為基板電路的輸出/輸入接點。該基板21〇 之該下表面2i2係形成有複數個外接墊（圖未繪出），以 供複數個銲球260的設置，該些銲球26〇係為金屬球， 特別是可迴焊接合之錫球，當封裝完成可藉由加熱該些 銲球260以表面接合至一外部印刷電路板（ρΗη^ circuit board, PCB)。 如第2圖所示，該些晶片22〇係以豎直結合形態設置 於該基板210之該上表面211，並與該基板21〇垂直， Φ 即為側立橫向的晶片設置。每一晶片2 2 0係設有一第一 石夕穿孔2 2 1。如第3圖所示，該些第一石夕穿孔2 2 1係可 没置於對應晶片2 2 0之侧邊，作為連接積體電路之對外 端點。具體而言，如第2與3圖所示，該第一矽穿孔221 係具有一上電極面222，該上電極面222係顯露於所屬 晶片220之一第一切割側面223。「切割側面」係為晶圓 切割時形成之晶片侧面’一般是與形成有積體電路的主 動表面為垂直。該些晶片220係側立設置於該基板2 i 〇 上’並使該些上電極面222為朝向遠離該基板2 1 〇之方[ 201225248 向。換言之，如第2圖所示’若該基板210在下方位置， 則該些晶片2 2 0設有該些第一梦穿孔2 2 1之一側係遠離 該基板210並朝上’該些晶片220未設有該些第一矽穿 孔22 1之另一相對侧係朝下並結合於該基板2 1 〇，形成 晶片侧立且電極面朝上之型態。 在本實施例中’如第2圖所示，該基板210係可更具 有複數個連接墊216，每一晶片220係可更設有一第二 $ 矽穿孔224，該第二矽穿孔224係具有一下電極面225 , 該下電極面225係顯露於所屬晶片220之一第二切割側 面226(如第3圖所示），利用銲料240焊接該些下電極面 225至該些連接墊216,即該些晶片220之上下兩切割側 面皆設有侧面裸露之電極面’而能與該基板210達成電 性連接。較佳地’如第2圖所示，該基板2 10係可更具 有複數個凹槽215，該些連接墊216係可設置於該些凹 槽215内。單一凹槽215之寬度係稍大於晶片22〇之單 鲁一第二碎穿孔224之厚度，以使該些晶片220可分別豎 直崁埋入該些凹槽215内，並以該些下電極面225接觸 該些連接墊216，再以銲料240焊接該些下電極面225 至該些連接塾216，而能穩固地使該些晶片22〇豎直在 該基板2 1 0上。 如第2圖所示，該銲線23 0係跨過該些晶片22〇之上 方並以連續跳接打線的方式接合該些上電極面222至該 第一接指213。「連續跳接打線」係為在一銲線的中間線 段形成有至少一下壓的銲點，但不截斷銲線，故能以— 201225248 銲線串連多個晶片的相同功能或訊號的電極。具體而 言’該基板210係可更具有一第二接指214，該第二接 指2 1 4係設置在該.基板2 1 0相對於該第一接指2丨3之另 一側。該知線2 3 0之兩端係分別焊接至該第一接指2 1 3 與s亥第一接指214。可利用打線機（wire bonder)以該第一 接指213為球接合端（ball bond)打線鍵合後往上移動， 跨過該些晶片220之上方並以連續跳接打線的方式接合 I 不同晶片220之該些第一矽穿孔221之該些上電極面 222，再以該第二接指214為尾鍵合端（或稱訂合式接合 端，stitch bond)將該銲線23 0之尾端鍵合在該第二接指 214上，使該些晶片220與該基板210之間形成電性連 接。不受限制地’亦可以該第二接指2 14為球接合端， 以該第一接指213為尾鍵合端進行打線。因此，該石夕穿 孔晶片封裝構造200不須在晶片間設置微凸塊，解決習 知垂直堆疊之矽穿孔晶片在堆疊時矽穿孔對位不易的問 • 題。此外’能以連續跳接打線的銲線230串連多個石夕穿 孔晶片220之上電極面222，用以省略在習知石夕穿孔晶 片之間的微凸塊’並可節省銲線數量，且不會有習知石夕 穿孔晶片之間微凸塊的電性連接失敗的問題。 詳細而言，在本實施例中，該銲線230在該些晶片 220之上方的線段係可為波浪狀，而波谷（tr〇ugh，即二 波峰crest間之最低點）皆接合至該些晶片22〇之上電極 面222，以提供一中間線段的伸縮空間。在另一變化實 施例中，該銲線23 0在該些晶片220之上方的線段亦可 10 201225248 為較為水平狀，而使該銲線230貼平並接觸於該些上電 極面222 ’以減少該銲線230之長度而減少材料成本。 在一更細部結構中，該矽穿孔晶片封裝構造2〇〇可另 包含有一封膠體25 0’該封膠體25 0係形成於該基板21〇 上，以密封該些晶片220與該銲線23 0 〇該封膠體25〇 可例如為環氧模封化合物（Epoxy M〇lding CQmpQund> EMC) ’以轉移成形方式（transfer m〇iding)覆蓋於該基板 210之該上表面211並包覆該些晶片22〇與該銲線23〇, 使其免受外力、溼氣或其他物質的破壞和腐蝕。 請參閱第4A至4D圖之截面示意圖，本發明進一步 說明該矽穿孔晶片封裴構造2〇〇之製造方法以彰顯本 案之功效。 頁无’如第 圓20包含複數個晶片（chiP)220,每一晶片220係設有 延伸到切割道（scri.be line)21之第一矽穿孔該些 一矽穿孔221内填充有導電之孔内金屬以垂直導通晶 220。該些孔内金屬之材質係可為導電材料，例如銲料 含銅導電膏、銀膠或導電油墨料，其係可利用壓模 形、填充灌注或電鍍笙士_^ , 凡电锻專方法形成。該些晶片22〇係可 同一晶圓20切割形成。在本實施例中，切割道21係 成在該第一石夕穿孔221 + * + h _ 之中央位置，即依切割道2丨位 切割後’可將該第—矽穿八 牙孔221为離為兩段皆且 墓 性質之開放端面，作， 八 乍為側向電極面，使該些晶片220 兩侧向白具有電連接特性。 201225248 接著，如第4 A與4 B圖所示，沿切割道21切割該晶 圓20以分離該些晶片220。如第3與4B圖所示，在此 切割步驟之後，同時形成該晶片220之該第一切割側面 223以及該第一矽穿孔221顯露於該第一切割側面223 之該上電極面222，並可同時形成該晶片220之該第二 切割側面2；26以及該第二矽穿孔224顯露於該第二切割 侧面2 2 6之該下電極面2 2 5。此切割步驟係可利用一切 割刀具（例如鑽石刀片）依照預先設定好之切割道，將該 晶圓20切割成複數個分離之晶片220。如第3圖所示， 令該些晶片220之兩側分別具有第一矽穿孔22丨之上電 極面222以及第二矽穿孔224之下電極面225 »在切割 之後，該上電極面222與/或該下電極面225可再電鍍上 鎳/金，以利電性接合。 之後’如第4C圖所示，側立設置該些晶片22〇於該 基板210上，並使該些上電極面222為朝向遠離該基板 210之方向’即是使該些上電極面222為朝上而下電極 面225為朝下並結合於該基板210。 之後’如第41)圖所示’形成上述之該銲線230，該 銲線230係跨過該些晶片22〇之上方並以連續跳接打線 的方式接合該些上電極面222至該第一接指213與該第 一接才曰2 1 4，能以一銲線串連多個矽穿孔晶片之矽穿孔 上電極面’以節省製程成本及時間。在本發明中，銲線 數里亦可為複數個，使一晶片220之每一石夕穿孔 221都能對應至—銲線230。通常該銲線230之材質可為 12 201225248 金（Au)，而具有良好延展性，另外，也可以使用銅線或 鋁線來代替。該銲線230之兩端打線接合點的形成方式 係可採用超音波接合、熱壓接合或熱超音波接合等方 式。在該銲線230之打線形成過程，每一打線接合點（包 3第接扣213、第二接指214以及上電極面222)皆可 利用毛細管（capillary)又稱瓷嘴或銲針（圖未繪出）以電 子點火（spark discharge)或氫焰燒方式使該銲線23〇具有 鲁焊接活性，首先一開始的打線接合點上燒結出一球體， 於第一點銲接之後拉線至適當長度，再利用超音波焊接 (ultrasonic welding)技術且不截斷線的方式令該銲線 230焊結於該些上電極面222，以增加接合強度。 依據本發明之第二具體實施例，另一種矽穿孔晶片封 裝構造說明於第5圖之截面示意圖。其中與第一實施例 相同的主要元件將以相同符號標示，並具備相同的基本 功效，不再予以贅述。該矽穿孔晶片封裝構造3〇〇主要 • 包含一基板210、複數個晶片220以及一銲線23〇。該些 晶片220間係可利用一絕緣性的黏晶膠3 7丨先垂直堆疊 之後’再利用黏晶膠3 7 2 —次侧立黏貼至該基板2 1 〇。 該些黏晶膠371、372係可選自於雙面PI膠帶、液態環 氧膠、預型片、B階黏膠（B-stage adhesive)或是晶片貼 附物質（Die Attach.Material, DAM)。 在本實施例中，該些晶片2 2 0係可具有僅單側之第一 石夕穿孔221 ’換g之，可不具有上述之第二石夕穿孔。該 些晶片220未具有電極之一側即利用該黏晶膠372貼附[ 13 201225248 固定於該基板210之該上表面21卜利用該銲線23〇跨 過該些晶片220之上方並以連續跳接打線的方式接合： 些上電極面222至該第—接指213 ,解決習知垂直堆疊 之矽穿孔晶片在堆疊時矽穿孔對位不易的問題。 以上所述，僅是本發明的較佳實施例而已並非對本 發明作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上’然而並非用以限定本發明，任何熟悉本項技 φ 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第1圖：一種習知矽穿孔晶片封裝構造之截面示意圖。 第2圖：依據本發明之第一具體實施例的一種矽穿孔晶 片封裝構造之截面示意圖。 第3圖：依據本發.明之第一具體實施例的矽穿孔晶片封 # 裝構造之晶片之俯視示意圖。 第4A至4D圖：依據本發明之第—具體實施例的矽穿孔 晶片封裝構造於製程中元件之截面示意圖。 第5圖：依據本發明之第二具體實施例的一種矽穿孔晶 片封裝構造之截面示意圖。 【主要元件符號說明】 1〇〇矽穿孔晶片封裝構造 110基板 113連接墊 1 2 0晶片 1 2 1矽穿孔 14 201225248 固體膠 142 流動膠 切割道 造 上表面 212 下表面 第二接指 215 凹槽 第一矽穿孔 222 上電極 下電極面 銲料 250 封膠體 130 微 凸 塊 141 160 銲 球 20 晶 圓 21 200 矽 穿 孔 晶 片 封 裝構 2 10 基板 211 213 第 —丨― 接 指 214 216 連 接 墊 220 晶 片 221 223 第 切 割 側 面· 224 第 二 矽 穿 孔 225 226 第 二 切 割 側 面 230 銲 線 240 260 銲 球 300 矽 穿 孔 晶 片 封 裝構 371 黏 晶 膠 372 造 黏晶膠 15It can be used to join the external surface. Specifically, the upper surface 2U of the substrate (1) has a first finger 213. The first finger 213 can be made of an electrical metal material such as aluminum, copper, aluminum alloy or any of copper alloys as an output/input junction of the substrate circuit. The lower surface 2i2 of the substrate 21 is formed with a plurality of external pads (not shown) for providing a plurality of solder balls 260, which are metal balls, in particular, reflowable. The solder balls can be surface bonded to an external printed circuit board (PCB) by heating the solder balls 260 when the package is completed. As shown in Fig. 2, the wafers 22 are disposed on the upper surface 211 of the substrate 210 in a vertically bonded manner, and are perpendicular to the substrate 21, and Φ is a wafer disposed laterally. Each of the wafers 220 is provided with a first diaper hole 2 2 1 . As shown in Fig. 3, the first diaper holes 2 2 1 may not be placed on the side of the corresponding wafer 220 as the external terminals of the integrated circuit. Specifically, as shown in Figures 2 and 3, the first turn-by-hole 221 has an upper electrode surface 222 that is exposed on one of the first cut sides 223 of the associated wafer 220. The "cut side" is the side of the wafer formed when the wafer is diced, which is generally perpendicular to the active surface on which the integrated circuit is formed. The wafers 220 are laterally disposed on the substrate 2 i ’ and the upper electrode surfaces 222 are oriented away from the substrate 2 1 [201225248]. In other words, as shown in FIG. 2, if the substrate 210 is in the lower position, the wafers 210 are provided with the first dream vias 2 1 1 side away from the substrate 210 and facing up the wafers The other opposite side of the first boring hole 22 1 is not disposed downward and is coupled to the substrate 2 1 〇 to form a pattern in which the wafer is laterally opposed and the electrode faces upward. In the present embodiment, as shown in FIG. 2, the substrate 210 can further have a plurality of connection pads 216, and each of the wafers 220 can further have a second 矽 矽 224, the second 矽 224 The lower electrode surface 225 is exposed on the second cutting side surface 226 of the wafer 220 (as shown in FIG. 3), and the lower electrode surface 225 is soldered to the connection pads 216 by solder 240, that is, The upper and lower cutting sides of the wafers 220 are provided with exposed side electrode faces ′ to be electrically connected to the substrate 210. Preferably, as shown in FIG. 2, the substrate 2 10 can have a plurality of recesses 215, and the connection pads 216 can be disposed in the recesses 215. The width of the single recess 215 is slightly larger than the thickness of the single rug-second puncturing 224 of the wafer 22, so that the wafers 220 can be vertically embedded in the recesses 215, respectively, and the lower electrodes are The surface 225 contacts the connection pads 216, and the lower electrode faces 225 are soldered to the connection pads 216 by solder 240, so that the wafers 22 are stably placed on the substrate 210. As shown in Fig. 2, the bonding wire 230 crosses the upper surface of the wafer 22 and is joined to the first electrode 213 by continuous jump wire bonding. "Continuous jumper wire" is a solder joint with at least a lower pressure formed in the middle line of a wire bond, but the wire is not cut off. Therefore, the same function or signal electrode of a plurality of wafers can be connected in series with the 201225248 wire bond. Specifically, the substrate 210 may further have a second finger 214 disposed on the other side of the substrate 210 with respect to the first finger 2丨3. The two ends of the line 2 30 are respectively soldered to the first finger 2 1 3 and the first finger 214. A wire bonder can be used to bond the first finger 213 to the ball bond and then move upward, across the wafers 220 and connect the wires in a continuous jumper. The upper electrode faces 222 of the first turns 221 of the wafer 220 are further terminated by the second bond 214 as a tail bond end (or a stitch bond). The end is bonded to the second finger 214 to form an electrical connection between the wafers 220 and the substrate 210. Alternatively, the second finger 2 14 may be a ball joint end, and the first finger 213 may be a tail bond end for wire bonding. Therefore, the diametrical wafer package structure 200 does not need to provide microbumps between the wafers, which solves the problem that the erbium perforated wafers in the vertically stacked stacks are difficult to align in the stacking. In addition, the soldering wire 230 capable of continuously striking the wires can be connected in series with the electrode faces 222 of the plurality of diaper-punched wafers 220 to omit the microbumps between the conventional shi-shi wavy wafers and save the number of bonding wires. There is no problem that the electrical connection of the microbumps between the perforated wafers fails. In detail, in this embodiment, the line of the bonding wire 230 above the wafers 220 may be wavy, and the troughs (the lowest points between the two crests crest) are bonded to the wires. The wafer 22 is above the electrode face 222 to provide a telescoping space for the intermediate segment. In another variation, the line of the bonding wire 230 above the wafers 220 may be relatively horizontal, and the bonding wire 230 is flattened and contacts the upper electrode faces 222'. The length of the bond wire 230 is reduced to reduce material costs. In a more detailed structure, the 矽-perforated chip package structure 2 can further include a glue 25 0 ′ formed on the substrate 21 , to seal the wafers 220 and the bonding wires 23 . The encapsulant 25 can be, for example, an epoxy molding compound (Epoxy M〇lding CQmpQund> EMC), covering the upper surface 211 of the substrate 210 by transfer molding and coating the upper surface 211 The wafer 22 is twisted with the bonding wire 23 to protect it from external force, moisture or other substances. Referring to the cross-sectional views of Figs. 4A to 4D, the present invention further illustrates the manufacturing method of the crucible perforated wafer sealing structure 2 to demonstrate the efficacy of the present invention. The page has no 'such as the first circle 20 including a plurality of wafers (chiP) 220, each of the wafers 220 is provided with a first perforation extending to a scri. be line 21, and the plurality of perforations 221 are filled with a conductive The metal in the hole conducts the crystal 220 vertically. The material of the metal in the hole may be a conductive material, such as a solder-containing copper conductive paste, a silver paste or a conductive ink material, which may be formed by using a stamper, a filling, or an electroplating gentleman. . The wafers 22 can be formed by cutting the same wafer 20. In this embodiment, the scribe line 21 is formed at a central position of the first diarrhea 221 + * + h _, that is, after the cutting of the scribe line 2, the first 矽 can be worn through the eight-hole 221 The open end face of the tomb nature of both segments is made, and the gossip is the lateral electrode face, so that the sides of the wafers 220 have electrical connection characteristics to white. 201225248 Next, as shown in Figs. 4A and 4B, the wafer 20 is cut along the scribe line 21 to separate the wafers 220. As shown in FIGS. 3 and 4B, after the cutting step, the first cut side surface 223 of the wafer 220 and the first turn surface 221 are exposed to the upper electrode surface 222 of the first cut side surface 223, and The second cut side 2; 26 of the wafer 220 can be simultaneously formed and the second turn 224 can be exposed to the lower electrode face 2 25 of the second cut side 2 2 6 . This cutting step utilizes all cutting tools (e.g., diamond blades) to cut the wafer 20 into a plurality of discrete wafers 220 in accordance with a pre-set cutting lane. As shown in FIG. 3, the two sides of the wafers 220 have a first turn-by-hole 22 丨 upper electrode face 222 and a second turn-by-hole 224 lower electrode face 225 » after cutting, the upper electrode face 222 / or the lower electrode surface 225 can be electroplated with nickel/gold for electrical bonding. Then, as shown in FIG. 4C, the wafers 22 are laterally disposed on the substrate 210, and the upper electrode faces 222 are oriented away from the substrate 210, that is, the upper electrode faces 222 are The upper and lower electrode faces 225 are directed downward and bonded to the substrate 210. Then, as shown in FIG. 41, the bonding wire 230 is formed, and the bonding wire 230 is stretched over the wafers 22 and joined to the upper electrode surface 222 by continuous jumper bonding to the first The first finger 213 and the first connector 241 can connect the upper electrode surface of the plurality of 矽-perforated wafers by a wire bond to save process cost and time. In the present invention, the number of bonding wires may be plural, so that each of the etched holes 221 of a wafer 220 can correspond to the bonding wire 230. Usually, the wire 230 can be made of 12 201225248 gold (Au), and has good ductility. Alternatively, copper wire or aluminum wire can be used instead. The manner in which the wire bonding points are formed at both ends of the bonding wire 230 may be ultrasonic bonding, thermocompression bonding or thermal ultrasonic bonding. In the wire forming process of the bonding wire 230, each wire bonding point (the third buckle 213, the second finger 214, and the upper electrode surface 222 of the package 3) can be used as a capillary or a soldering needle. It is not shown that the wire 23〇 has a Lu welding activity by spark discharge or hydrogen flame burning. First, a ball is sintered on the first wire bonding joint, and the wire is drawn to the appropriate after the first spot welding. The length is then welded to the upper electrode faces 222 by means of ultrasonic welding techniques without breaking the wires to increase the joint strength. In accordance with a second embodiment of the present invention, another crucible perforated wafer encapsulation configuration is illustrated in cross section in Figure 5. The same main elements as those in the first embodiment will be denoted by the same reference numerals and have the same basic functions and will not be described again. The 矽-perforated wafer package structure 3 〇〇 mainly includes a substrate 210, a plurality of wafers 220, and a bonding wire 23〇. The wafers 220 can be vertically stacked by using an insulating adhesive, and then the adhesive is applied to the substrate 2 1 侧. The adhesives 371, 372 can be selected from double-sided PI tape, liquid epoxy glue, pre-formed sheet, B-stage adhesive or wafer attachment material (Die Attach.Material, DAM) ). In this embodiment, the wafers 250 may have only one side of the first diaper 221 ′, which may not have the second diaper. The wafers 220 are not attached to one side of the electrodes, and are attached by the adhesive 372. [13 201225248 is fixed to the upper surface 21 of the substrate 210. The bonding wires 23 are used to straddle the wafers 220 and are continuous. The method of jumper bonding is performed: the upper electrode surface 222 to the first finger 213, which solves the problem that the conventional vertically stacked tantalum perforated wafer is difficult to be aligned in the stacking. The above is only a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed in the above preferred embodiments, however, it is not intended to limit the invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the present invention without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional crucible wafer package structure. Fig. 2 is a cross-sectional view showing a crucible-perforated wafer package structure in accordance with a first embodiment of the present invention. Fig. 3 is a top plan view showing a wafer of a 矽-perforated wafer package structure according to the first embodiment of the present invention. 4A to 4D are cross-sectional views showing the components of the crucible-perforated wafer package structure in the process according to the first embodiment of the present invention. Fig. 5 is a cross-sectional view showing a crucible-perforated wafer package structure in accordance with a second embodiment of the present invention. [Main component symbol description] 1"perforated chip package structure 110 substrate 113 connection pad 1 2 0 wafer 1 2 1 矽 perforation 14 201225248 solid glue 142 flow glue cutting surface upper surface 212 lower surface second finger 215 groove number One puncturing hole 222 Upper electrode lower electrode surface solder 250 Sealing body 130 Microbump 141 160 Solder ball 20 Wafer 21 200 矽Perforated chip package 2 10 Substrate 211 213 丨 丨 接 214 216 Connection pad 220 Wafer 221 223 First cutting side · 224 Second opening perforation 225 226 Second cutting side 230 Bonding wire 240 260 Solder ball 300 矽 Perforated wafer package 371 Adhesive glue 372 Adhesive glue 15