CN110299328B - Stack packaging device and packaging method thereof - Google Patents

Stack packaging device and packaging method thereof Download PDF

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Publication number
CN110299328B
CN110299328B CN201810233595.3A CN201810233595A CN110299328B CN 110299328 B CN110299328 B CN 110299328B CN 201810233595 A CN201810233595 A CN 201810233595A CN 110299328 B CN110299328 B CN 110299328B
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substrate
forming
pad
present application
welding
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CN110299328A (en
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常明
张晓东
黄京
刘国文
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2018/116159 priority patent/WO2019179145A1/en
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The application discloses a semiconductor device and a packaging method thereof. In the device, the welding conduction of the first substrate and the second substrate is realized through an interconnection structure which is arranged above the first welding pad of the second substrate and extends into the through hole of the first substrate. The through holes for forming the first substrate can be realized by a smaller-pitch process, such as an electroplating process, so that the interconnection structure formed in the through holes for realizing the welding of the first substrate and the second substrate can realize smaller-pitch connection, and the capacity requirement of the smaller-pitch process can be met. Therefore, the interconnection structure formed above the first bonding pad of the second substrate and extending into the through hole of the first substrate can realize electrical connection with smaller spacing, thereby being beneficial to improving the packaging density of the stacked package device.

Description

Stack packaging device and packaging method thereof
Technical Field
The present disclosure relates to the field of semiconductor device manufacturing technologies, and in particular, to a stacked package device and a package method thereof.
Background
As the size of electronic devices is reduced, high integration density may be achieved by stacking a plurality of chips in one semiconductor package or stacking a plurality of individual semiconductor packages. Recently, a Package On Package (POP) technology has been introduced for mobile electronic device applications and the like. The POP is a stacked package in which a logic package assembly and a memory package assembly are stacked. With the POP technique, different types of semiconductor chips can be included in one semiconductor device.
With the development of the POP technology towards the direction of high-density input/output pins, the distance between the pins is smaller and smaller, and the package thickness is thinner and thinner, so how to further increase the package density of the stacked package device and reduce the package cost becomes a big problem in the industry.
Disclosure of Invention
In view of the above, the present application provides a package on package device and a packaging method thereof, so as to further increase the packaging density of the package on package device and reduce the packaging cost.
In order to solve the technical problem, the following technical scheme is adopted in the application:
a first aspect of the present application provides a semiconductor device comprising:
a first substrate and a second substrate disposed over the first substrate;
the first and second substrates each include opposing first and second surfaces;
the first substrate is provided with a through hole penetrating through the first surface and the second surface of the first substrate, the first surface of the second substrate is provided with a first welding pad, and the through hole is opposite to the first welding pad;
the device further comprises an interconnection structure used for connecting the first substrate and the second substrate, wherein the interconnection structure is fixed on the first bonding pad and is extruded and filled in the through hole.
According to the semiconductor device provided by the first aspect of the present application, the connection conduction between the first substrate and the second substrate is realized through the interconnection structure which is fixed on the first bonding pad of the second substrate and is extruded and filled in the through hole of the first substrate. The through holes for forming the first substrate can be realized by a smaller-pitch process, such as an electroplating process, so that the interconnection structure formed in the through holes for realizing the connection of the first substrate and the second substrate can realize smaller-pitch connection, and the capacity requirement of the smaller-pitch process can be met. Therefore, the semiconductor device is fixed on the first bonding pad of the second substrate, and the interconnection structure extruded and filled in the through hole of the first substrate can realize the electrical connection of the first substrate and the second substrate with smaller distance and short distance, thereby being beneficial to improving the packaging density of the stacked packaging device. In addition, the packaging process flow of the stacked packaging device is simple, and the cost is low, so that the packaging cost of the stacked packaging device is reduced.
With reference to the first aspect of the present application, in a first possible implementation manner, a metal layer is formed on a surface of the through hole, and the metal layer is electrically connected to the electronic device on the first substrate.
With reference to the first aspect and the first possible implementation manner of the present application, in a second possible implementation manner, the device further includes a cavity structure disposed on the second surface of the first substrate, where the cavity structure includes a cavity structure wall disposed on the second surface of the first substrate and a cavity space surrounded by the cavity structure wall;
the first surface of the second substrate is further provided with a first chip, and the first chip is accommodated in the cavity space.
In this second possible implementation manner, the cavity structure disposed on the second surface of the first substrate may play a certain supporting role for the first substrate, so as to enhance the overall rigidity of the first substrate, and therefore, compared with a substrate without the cavity structure, the overall thickness of the first substrate may be relatively reduced, thereby achieving the effect of reducing the thickness of the device.
With reference to the first aspect of the present application and any one of the foregoing possible implementations, in a third possible implementation, a filling height of the interconnect structure in the via is at least 30% of a depth of the via.
In this third possible implementation, the soldering stability between the first substrate and the second substrate can be improved.
With reference to the first aspect of the present application and any one of the foregoing possible implementations, in a fourth possible implementation, the interconnection structure is a rivet structure. The realization mode can increase the bonding force between the first substrate and the second substrate and enhance the stability and reliability of the welding position of the first substrate and the second substrate.
With reference to the first aspect of the present application and any one of the foregoing possible implementations, in a fifth possible implementation, the interconnect structure is formed by a conductive adhesive material that can be formed by curing.
With reference to the fifth possible implementation manner of the first aspect of the present application, in a sixth possible implementation manner, the conductive adhesive material is a conductive adhesive. This implementation can simplify the packaging process.
With reference to the first aspect of the present application and any one of the foregoing possible implementation manners, in a seventh possible implementation manner, a solder mask layer is further disposed on the first surface of the second substrate, and the solder mask layer is located around the first pad. This implementation can prevent the cured conductive bonding material from overflowing the first pad.
With reference to the seventh possible implementation manner of the first aspect of the present application, in an eighth possible implementation manner, the solder mask layer is a solder mask layer defining structure or a non-solder mask layer defining structure.
With reference to the first aspect of the present application and any one of the foregoing possible implementation manners, in a ninth possible implementation manner, the device further includes a second pad disposed on the second surface of the second substrate, where the second pad is configured to be electrically connected to an external circuit.
With reference to the first aspect of the present application and any one of the foregoing possible implementations, in a tenth possible implementation, the device further includes:
a third substrate disposed over the first surface of the first substrate; the third substrate is electrically connected with the first substrate;
a second chip disposed over the third substrate, the second chip electrically connected to a surface of the third substrate.
A second aspect of the present application provides a method of packaging a semiconductor device, including:
providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively comprise a first surface and a second surface which are opposite, and a first welding pad is arranged on the first surface of the second substrate;
forming through holes which vertically penetrate through the first surface and the second surface of the first substrate at positions corresponding to the first welding pads;
assembling the first substrate and the second substrate together, and enabling the through holes to be arranged opposite to the first welding pads;
and forming an interconnection structure for connecting the first substrate and the second substrate above the first bonding pad, wherein the interconnection structure is fixed on the first bonding pad and is extruded and filled in the through hole.
The method provided by the second aspect of the present application can realize the connection conduction between the first substrate and the second substrate through the interconnection structure which is fixed on the first bonding pad of the second substrate and is extruded and filled in the through hole of the first substrate. The through holes for forming the first substrate can be realized by a smaller-pitch process, such as an electroplating process, so that the interconnection structure formed in the through holes for realizing the connection of the first substrate and the second substrate can realize smaller-pitch connection, and the capacity requirement of the smaller-pitch process can be met. Therefore, the method can realize the electrical connection of the first substrate and the second substrate at smaller distance and short distance by the interconnection structure which is fixed on the first bonding pad of the second substrate and is extruded and filled in the through hole of the first substrate, thereby being beneficial to improving the packaging density of the stacked packaging device. In addition, the packaging process flow of the stacked packaging device is simple, and the cost is low, so that the packaging cost of the stacked packaging device is reduced.
With reference to the second aspect of the present application, in a first possible implementation manner, after forming the via and before forming the interconnect structure, the method further includes:
and forming a metal layer on the surface of the through hole, wherein the metal layer is used for being electrically connected with the electronic device on the first substrate.
With reference to the second aspect of the present application and any one of the foregoing possible implementation manners of the second aspect, in a second possible implementation manner, before forming the through hole, the method further includes:
forming a cavity structure on the second surface of the first substrate, wherein the cavity structure comprises a cavity structure wall arranged on the second surface of the first substrate and a cavity space surrounded by the cavity structure wall; the cavity space is used for accommodating a first chip arranged on the first surface of the second substrate;
the through holes which vertically penetrate through the first surface and the second surface of the first substrate are formed at positions corresponding to the first welding pads, and the through holes are specifically as follows:
and forming through holes which vertically penetrate through the first surface and the second surface of the first substrate and the cavity structure wall at positions corresponding to the first welding pads.
In this second possible implementation manner, the cavity structure disposed on the second surface of the first substrate may play a certain supporting role for the first substrate, so as to enhance the overall rigidity of the first substrate, and therefore, compared with a substrate without the cavity structure, the overall thickness of the first substrate may be relatively reduced, thereby achieving the effect of reducing the thickness of the device.
With reference to the second aspect of the present application and any one of the foregoing possible implementation manners, in a third possible implementation manner, before assembling the first substrate and the second substrate together, the method further includes:
coating a conductive bonding material capable of being cured and molded on the first welding pad;
the forming of the interconnection structure for connecting the first substrate and the second substrate above the first pad specifically includes:
extruding the conductive bonding material which is coated on the first welding pad and can be solidified and molded while the first substrate and the second substrate are assembled, so that the conductive bonding material flows into the through hole;
and curing the conductive bonding material capable of being cured and molded, thereby forming an interconnection structure for connecting the first substrate and the second substrate.
With reference to the second aspect of the present application and any one of the foregoing possible implementation manners, in a fourth possible implementation manner, the assembling the first substrate and the second substrate together specifically includes:
and attaching and assembling the first substrate and the second substrate together by adopting a surface mounting process.
With reference to the second aspect of the present application and any one of the foregoing possible implementations, in a fifth possible implementation, the method further includes:
and forming a second welding pad on the second surface of the second substrate, wherein the second welding pad is used for being electrically connected with an external circuit.
With reference to the second aspect of the present application and any one of the foregoing possible implementations, in a sixth possible implementation, before the assembling, the method further includes:
forming a third substrate on the first surface of the first substrate; the third substrate is electrically connected with the first substrate;
forming a second chip over the third substrate, the second chip being electrically connected to a surface of the third substrate.
Compared with the prior art, the method has the following beneficial effects:
based on the above technical solutions, in the stacked package device provided in the embodiments of the present application, the interconnection structure fixed on the first pad of the second substrate and filled in the through hole of the first substrate by pressing achieves connection conduction between the first substrate and the second substrate. The through holes for forming the first substrate can be realized by a smaller-pitch process, such as an electroplating process, so that the interconnection structure formed in the through holes for realizing the connection of the first substrate and the second substrate can realize smaller-pitch connection, and the capacity requirement of the smaller-pitch process can be met. Therefore, the interconnection structure which is fixed on the first bonding pad of the second substrate and extruded and filled in the through hole of the first substrate can realize smaller distance and short-distance electrical connection between the first substrate and the second substrate, and therefore the packaging density of the stacked packaging device is improved.
In addition, in the embodiment of the application, the packaging process flow of the stacked packaged device is simple, and the cost is low, so that the packaging cost of the stacked packaged device is favorably reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a package on package device in the prior art;
fig. 2 is a schematic cross-sectional structure diagram of a package on package device provided by an embodiment of the present application;
fig. 3 is a schematic cross-sectional structure diagram of another package on package device provided in the embodiment of the present application;
fig. 4 is a flowchart illustrating a packaging method for a package on package device according to an embodiment of the present application;
fig. 5a 1-5E are schematic cross-sectional views illustrating a series of processes of a packaging method for a package on package device according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of a device formed by another packaging method for packaging a package-on-package device according to an embodiment of the present application.
Detailed Description
In the field of semiconductor device packaging, a cross-sectional structure of a stacked package device is shown in fig. 1. In fig. 1, the stack package device adopts a dual substrate bonding structure in which a system on chip (SOC chip) 11 is located between an upper substrate 12 and a lower substrate 13, so that a certain distance is ensured between the upper and lower substrates 12 and 13 and electrical connection between the upper and lower substrates 12 and 13 can be achieved when designing the device structure. In fig. 1, in order to electrically connect the upper and lower substrates 12 and 13, the upper and lower substrates 12 and 13 are soldered together using copper core balls 14.
At present, the minimum pitch achieved by the copper core ball process is 270 μm, which results in a low packing density of the stacked package structure. With the development of electronic device technology, a smaller pitch process is required to realize the soldering of the upper substrate and the lower substrate, so as to improve the packaging density of the stacked package device.
In addition, since the SOC chip 11 is disposed between the upper and lower substrates 12 and 13 and the SOC chip 11 is bonded to the lower substrate 13 by the flip chip process, a gap space is required between the upper and lower substrates 12 and 13 to accommodate the SOC chip 11 when the upper and lower substrates 12 and 13 are bonded together. If the upper and lower substrates 12 and 13 are bonded together using copper core balls that are too small in size without changing the size of the gap space, cold joint is likely to occur, resulting in poor bonding between the upper and lower substrates 12 and 13.
Therefore, the following drawbacks exist in the stacked package device shown in fig. 1:
firstly, the minimum distance for realizing the copper core ball process of the upper substrate and the lower substrate is larger, so that the packaging density of the stacked packaging structure is lower;
and secondly, the upper substrate and the lower substrate are connected by adopting the copper core balls, and if the size of the copper core balls is not properly selected, the defect of poor welding of the upper substrate and the lower substrate is easy to occur.
In order to overcome the defects of the package on package device shown in fig. 1, embodiments of the present application provide a new package on package device. In the stacked package device, the first substrate and the second substrate are soldered and conducted through the interconnection structure which is fixed on the first bonding pad of the second substrate and is extruded and filled in the through hole of the first substrate. The through holes for forming the first substrate can be realized by a smaller-pitch process, such as an electroplating process, so that the interconnection structure formed in the through holes for realizing the welding of the first substrate and the second substrate can realize smaller-pitch connection, and the capacity requirement of the smaller-pitch process can be met. Therefore, the electrical connection of the first substrate and the second substrate with smaller spacing can be realized by the interconnection structure which is extruded and filled in the through hole of the first substrate through being fixed on the first welding pad of the second substrate, so that the packaging density of the stacked packaging device is improved.
In addition, in the embodiment of the application, the packaging process flow of the stacked packaged device is simple, and the cost is low, so that the packaging cost of the stacked packaged device is favorably reduced.
In addition, in the package on package device provided by the embodiment of the present application, the interconnection structure for connecting the first substrate and the second substrate is directly formed on the first pad of the second substrate and is pressed and filled in the via hole of the first substrate, so that the interconnection structure does not have a cold joint defect in the cu-nb ball process. Therefore, compared with the scheme of utilizing the copper core ball process to realize the connection of the upper substrate and the lower substrate in the prior art, the interconnection structure can increase the bonding force between the first substrate and the second substrate and can enhance the stability and reliability of the welding spot.
The structure of the package on package device provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a package on package device provided in an embodiment of the present application includes the following structure:
a first substrate 21, a second substrate 22 and a cavity structure 23;
the first substrate 21 and the second substrate 22 both include a first surface and a second surface opposite to each other, and the first surface of the second substrate 22 is provided with a first chip 221 and a first pad 222; as an example, the first chip 221 may be a system-on-chip (SOC chip);
the cavity structure 23 includes a cavity structure wall 231 disposed on the second surface of the first substrate 21 and a cavity space 232 surrounded by the cavity structure wall 231;
the second substrate 22 is disposed under the cavity structure 23, and the first pads 222 are disposed under the cavity structure walls 231. Moreover, in order to reduce the overall device size of the stacked package device, the first chip 221 may be accommodated in the cavity space 232, and thus, in the embodiment of the present invention, the first chip 221 may be disposed opposite to the cavity space 232, and the size of the cavity space 232 may meet the requirement of accommodating the first chip 221.
The package on package device further includes a via 24 vertically penetrating the first surface and the second surface of the first substrate 21 and the cavity structure wall 231, the via 24 being disposed opposite to the first pad 222.
In addition, in order to realize the electrical connection between the first substrate 21 and the second substrate 22 and the adhesion of the two substrates, the stacked package device further includes an interconnect structure 25 fixed above the first pad 222 and extending to be press-filled into the through hole 24.
In addition, a metal layer 26 may be formed on the surface of the through hole 24, and the metal layer is used for electrically connecting with the electronic device on the first substrate 21. As an example, the metal layer may be a copper metal layer formed using an electroplating process.
It should be noted that, in the embodiment of the present application, the number of the first pads 222 may be multiple, and correspondingly, the number of the through holes 24 formed above the first pads 222 may also be multiple. More specifically, there is a one-to-one correspondence between the vias 24 and the first pads 222, such that one via 24 corresponds to one first pad 222. As such, a plurality of interconnect structures 25 may be included in the package on package device provided by the embodiments of the present application. In the present embodiment, the interconnect structure 25 may be formed in various ways.
As an example, the interconnect structure 25 may be formed of a conductive adhesive material that can be cured. As an example, the conductive adhesive material capable of being cured may be a conductive adhesive. As an example, the conductive paste may be at least one of a solder paste, a copper paste, and a silver paste. When the interconnect structure 25 is formed by using a conductive paste, the specific implementation thereof may be as follows: in the embodiment of the present application, after the cavity structure 23 is formed on the second surface of the first substrate 21, the first substrate 21 and the second substrate 22 may be connected together by using a surface mounting process. Before the two-substrate mounting, a conductive adhesive is coated on the first bonding pads 222 of the second substrate 22, then a certain pressure is applied during the two-substrate mounting, the conductive adhesive is pressed into the through holes 24 by the pressure drop, and then the conductive adhesive pressed into the through holes 24 is solidified into the interconnection structures 25 by reflow or baking.
When the embodiment of the present application adopts the above implementation manner to form the interconnect structure 25, the opening of the via 24 may be smaller than the size of the first pad 222, and therefore, the interconnect structure 25 may have a rivet structure with a large bottom area and a small top area. More specifically, an elongated portion of the interconnect structure 25 in the form of a rivet structure is located within the through-hole 24. The interconnection structure 25 having the rivet structure can increase the bonding force between the first substrate 21 and the second substrate 22, and enhance the reliability of the bonding position between the two. Moreover, in the embodiment of the present application, the height of the interconnect structure 25 extending into the through hole 24 is related to the amount of the conductive paste dispensed above the first pad 222, and the more the amount of the conductive paste, the higher the height extending into the through hole 24, the more stable and firm the soldering performance of the interconnect structure 25. As an alternative embodiment of the present application, in order to ensure the soldering stability between the first substrate 21 and the second substrate 22, the height of the interconnect structure 25 extending into the through hole 24 is at least 30% of the total depth of the through hole 24, and as a more specific alternative embodiment, the height of the interconnect structure 25 extending into the through hole 24 is the same as the total depth of the through hole 24. As another specific example, when the amount of the conductive paste is sufficiently large, the conductive paste may fill the entire through hole and overflow onto the first surface of the first substrate 21 by the pressing force, in which case the interconnect structure 25 may be formed to extend onto the first surface of the first substrate 21, and the interconnect structure 25 may further improve the soldering stability between the first substrate 21 and the second substrate 22.
As can be seen from the above, in the embodiment of the present application, the interconnection structure 25 is used to replace the copper core ball 14 shown in fig. 1 to realize the connection between the first substrate 21 and the second substrate 22, and the interconnection structure 25 does not have the insufficient solder joint defect of the copper core ball process. Therefore, the stacked package device in the embodiment of the application can solve the defect of poor welding of the two substrates in the existing stacked package device,
in addition, in the embodiment of the present application, the through holes 24 may be implemented by a smaller pitch process, such as an electroplating process, and therefore, the interconnection structures formed in the through holes for implementing the soldering between the first substrate and the second substrate may implement smaller pitch connection, which can meet the requirement of smaller pitch process capability. Therefore, the electrical connection with smaller spacing can be realized by the interconnecting joint which is fixed on the first bonding pad of the second substrate and is extruded and filled in the through hole of the first substrate, so that the packaging density of the stacked packaging device is improved. As an example, the manufacturing process parameters of the through hole 24 are as follows: the pitch was 230 μm, the pore size was 100 μm and the pore plate was 200 μm.
In addition, the connection of the first substrate 21 and the second substrate 22 is realized by the interconnection structure 25 formed in the through hole 24, and the risk of tin stringing does not exist.
In addition, in the embodiment of the present application, the cavity structures 23 disposed on the second surface of the first substrate 21 can support the first substrate 21 to a certain extent, so as to enhance the overall rigidity of the first substrate 21, and therefore, compared with a substrate without the cavity structures, the overall thickness of the first substrate 21 can be relatively reduced, thereby achieving the effect of reducing the thickness of the device. As an example, in the embodiment of the present application, the thickness of the first substrate 21 may be thinned by at least 60 μm compared to a substrate not provided with a cavity structure.
In addition, since the cavity structure 23 can enhance the overall rigidity of the first substrate 21, the processing of the package process of the stacked package device in the embodiment of the present application is convenient and easy, and the package yield is improved.
It should be noted that, as an extension of the embodiment of the present application, the stacked package device provided in the embodiment of the present application may not include the cavity structure 23 in the stacked package device shown in fig. 2. As such, in this embodiment, the effect of the cavity structure 23 is not obtained, but the embodiment can achieve electrical connection between the first substrate 21 and the second substrate 22 at a smaller distance and a short distance by the interconnection structure formed above the first pad 222 of the second substrate 22 and filled in the through hole 24 of the first substrate 21, thereby facilitating to increase the packaging density of the package on package device.
As a specific example of the present application, the first substrate 21 may be a copper-clad plate, and more specifically, the copper-clad plate may be a double-sided copper-clad plate, and in order to manufacture the fine line layer, ultra-thin copper foils having a certain thickness may be respectively disposed on the surfaces of the copper-clad plate, and as an example, the thickness of the ultra-thin copper foil may be 3 μm.
As another embodiment of the present application, the second Substrate 22 may be manufactured by using a 3-layer ETS (embedded Trace Substrate) process.
As another embodiment of the present application, the first pads 222 may be metal pads, metal solder balls, or other structures for realizing electrical connection. In the embodiment of the present application, the first pad 222 is illustrated as a metal pad.
In order to prevent the conductive adhesive material capable of being cured and molded from overflowing the first pad 222, as another specific embodiment of the present application, as shown in fig. 2, a solder resist layer 223 is disposed on the first surface of the second substrate 22, and the solder resist layer 223 is located around the first pad 222. More specifically, the Solder Mask may be a Solder Mask Defined (SMD) structure or a Non-Solder Mask Defined (NSMD) structure. And the opening of the solder mask layer of the SMD structure is smaller than the metal bonding pad. The circuit board designer defines the shape code, the position and the rated size of the welding disc; the actual size of the pad opening is controlled by the solder mask manufacturer. The solder mask is typically an imageable liquid photoresist.
The metal pads of the NSMD structure are smaller than the solder mask openings. On NSMD pads of a surface-wiring circuit board, a portion of the printed circuit wiring is wetted with solder.
As another embodiment of the present application, the second substrate 22 may further have a second pad 224 disposed on the second surface thereof for electrically connecting with an external circuit, and the second pad 224 may be a metal pad, a metal solder ball, or another electrical connection structure.
As another specific embodiment of the present application, as shown in fig. 3, the stacked package device provided in this embodiment may further include, on the basis of the structure shown in fig. 2:
a third substrate 31 disposed over the first surface of the first substrate 21;
a second chip 32 disposed above the third substrate 31, the second chip 32 being electrically connected to the surface of the third substrate 31, the third substrate 31 being electrically connected to the first substrate 21 through a third pad 33.
By way of example, the second chip 32 may be a Memory chip (Memory). The third pads 33 may be metal solder balls, metal pads, or other electrical connection structures.
In addition, in order to protect the internal components of the stacked package device, the stacked package device structure shown in fig. 3 may further include a molding compound 34 encapsulating the second chip 32 and the third substrate 31.
The above is a specific structure of the package on package device provided in the embodiments of the present application. Based on the specific structure of the package on package device, the embodiment of the application also provides a specific implementation manner of the packaging method of the package on package device.
Referring to fig. 4 to fig. 5D, a method for packaging a package on package device according to an embodiment of the present application includes the following steps:
s401: a first substrate 21 and a second substrate 22 are provided, the first substrate 21 and the second substrate 22 both include a first surface and a second surface opposite to each other, and a first chip 221 and a first pad 222 are disposed on the first surface of the second substrate 22.
As shown in fig. 5a1, the first substrate 21 is provided with blind holes 211 therein, and the second surface is provided with wires 212. The blind via 211 may enable electrical connection of the first surface and the second surface of the first substrate 21.
In the embodiment of the present application, the first substrate 21 may be a double-sided copper-clad plate, and in order to fabricate a fine circuit on the surface of the first substrate 21, ultra-thin copper foils with a certain thickness may be further disposed on two surfaces of the first substrate 21.
In the embodiment of the present application, a cross-sectional view of the structure of the second substrate 22 is shown in fig. 5a2, which may include a first surface and a second surface opposite to each other, and the first chip 221 and the first pad 222 are disposed on the first surface of the second substrate 22. In addition, a solder mask 223 may be disposed on the first surface of the second substrate 22, and the solder mask 223 is located around the first pad 222.
The second substrate 22 can be fabricated using a 3-layer ETS process. In the embodiment of the present application, after the 3-layer ETS process is performed, the first chip 221 and the first pad 222 are formed on the first surface of the second substrate 22.
As an example, in the embodiment of the present application, the first chip 221 may be formed on the first surface of the second substrate 22 using a flip-chip process. The specific process can be as follows:
the wafer formed with the plurality of first chips is ground to be thinned, and is cut into individual first chips, the first chips are bonded to the first surface of the second substrate 22 by using a die bonder, and underfill (underfill) is filled in bottoms of the first chips, so that the first chips 221 are formed on the first surface of the second substrate 22.
In the embodiment of the present application, the first chip 221 may be an SOC chip. In addition, the first pads 222 may be metal pads, metal solder balls, or other electrical connection structures.
S402: a cavity structure 23 is formed on the second surface of the first substrate 21, and the cavity structure 23 includes a cavity structure wall 231 disposed on the second surface of the first substrate 21 and a cavity space 232 surrounded by the cavity structure wall 231.
As an example, a layer of photosensitive dielectric material may be coated on the second surface of the first substrate 21, and then the cavity structure 23 may be formed on the second surface of the first substrate 21 through a photolithography and etching process.
In addition, as another example, a copper-clad plate or a semi-cured resin sheet (prep, PPG) may also be formed on the second surface of the first substrate 21, and then the cavity structure 23 may be formed by mechanically drilling and milling the copper-clad plate or the semi-cured resin sheet.
The cross-sectional structure of the step is shown in fig. 5B.
S403: a via hole 24 penetrating the first and second surfaces of the first substrate 21 and the cavity structure wall 231 up and down is formed at a position corresponding to the first pad 222.
Note that, in the embodiment of the present application, the position corresponding to the first pad 222 is a position vertically opposite to the first pad 222 when the first substrate and the second substrate are vertically opposite and parallel.
This step may be embodied as forming the through hole 24 penetrating the first surface and the second surface of the first substrate 21 and the cavity structure wall 231 up and down at the position corresponding to the first pad 222 by using a mechanical drilling process or a plated through hole process.
It should be noted that, in the embodiment of the present application, a metal layer 26 may also be formed on the surface of the through hole 24 to electrically connect with the electronic device on the first substrate 21.
The cross-sectional structure of the step is shown in fig. 5C.
S404: the conductive paste 51 is coated on the first pad 222.
In this step, the conductive adhesive 51 may be coated on the first bonding pad 222 that needs to be soldered and connected to the first substrate by a dispensing process.
In this step, the conductive paste may be at least one of a solder paste, a copper paste, and a silver paste. In order to secure soldering stability between the first substrate 21 and the second substrate 22, the amount of the conductive paste 51 applied is as large as possible.
The cross-sectional structure of the step is shown in fig. 5D.
S405: the first substrate 21 and the second substrate 22 formed with the cavity structure 23 are assembled together, and the first chip 221 is accommodated by the cavity space 232, the through hole 24 is disposed opposite to the first pad 222, and the conductive paste 51 coated on the first pad 222 is extruded and flowed into the through hole 24 by applying a certain pressure while assembling.
As an example, the first substrate 21 and the second substrate 22 formed with the cavity structure 23 may be attached and assembled together by using a surface Mounting process (Mounting).
While the first substrate 21 and the second substrate are attached together, a certain pressure is applied to extrude the conductive paste 51 coated on the first pads 222 into the through holes 24.
The cross-sectional structure of the step is shown in fig. 5E.
S406: the conductive paste 51 is cured such that the conductive paste 51 forms the interconnect structure 25 extending into the via 24 over the first pad 333.
The conductive paste 51 is cured using a reflow or baking process such that the conductive paste 51 forms the interconnect structure 25 extending into the via 24 over the first pad 333. The interconnection structure 25 is used to electrically connect the first substrate 21 and the second substrate 22 and bond the two substrates.
As an alternative embodiment of the present application, in order to ensure the soldering stability between the first substrate 21 and the second substrate 22, the height of the interconnect structure 25 extending into the through-hole 24 is at least 30% of the total depth of the through-hole 24.
The cross-sectional structure of the step is shown in fig. 5E.
It should be noted that, in the embodiment of the present application, S402 to S403 are processes on the first substrate 21, and S404 is a process on the second substrate 22, and since the first substrate 21 and the second substrate 22 are not assembled together yet, the execution sequence of S402 to S403 and S404 is not limited in the embodiment of the present application. Specifically, as shown in fig. 4, S402 to S403 may be executed first, and then S404 may be executed, or S404 may be executed first, and then S402 to S403 may be executed, or they may be executed simultaneously.
The foregoing is a specific implementation manner of the packaging method for a package on package device provided in the embodiments of the present application. In this embodiment, a conductive paste is used as an example of a material for forming the interconnect structure. In fact, in the embodiment of the present application, the material forming the interconnect structure is not limited to the conductive paste, but may be other conductive adhesive materials capable of being cured. Accordingly, when other conductive bonding materials capable of being cured to form the interconnect structure are used, the corresponding specific manner of forming the interconnect structure may vary accordingly.
For example, as an expanded embodiment of the present application, before the two substrates are assembled, the conductive adhesive is not coated on the first pad, but after the two substrates are assembled, a curable conductive adhesive material is introduced into the through hole 24, and then the curable conductive adhesive material is formed into the interconnect structure located above the first pad and extending into the through hole 24 through a corresponding process.
In addition, as another extended embodiment of the present application, when the conductive adhesive is used as the conductive adhesive material capable of being cured, before the two substrates are assembled, the conductive adhesive is not coated on the first bonding pad, but after the two substrates are assembled, the conductive adhesive is introduced into the through hole 24, and then the conductive adhesive is cured by corresponding reflow or baking, so that the conductive adhesive forms the interconnection structure located above the first bonding pad and extending into the through hole 24.
In addition, as an alternative embodiment of the present application, on the basis of the above embodiment, before S405, the method further includes the following steps:
forming a third substrate 31 on the first surface of the first substrate 21;
a second chip 32 is formed over the third substrate 31, the second chip 32 is electrically connected to the surface of the third substrate 31, and the third substrate 31 and the first substrate 21 are electrically connected through a third pad 33.
In addition, in order to protect the internal components of the package on package device, the packaging method may further include:
the second chip 32 and the third substrate 31 are molded with a molding compound, so as to form a molding compound 34 wrapping the second chip 32 and the third substrate 31.
The structure of the finally formed package-on-package device according to this embodiment is shown in fig. 6, and the corresponding simplified structure is shown in fig. 3.
The foregoing is a detailed description of the present application.

Claims (12)

1. A method of packaging a semiconductor device, comprising:
providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively comprise a first surface and a second surface which are opposite, and a first welding pad is arranged on the first surface of the second substrate;
forming through holes which vertically penetrate through the first surface and the second surface of the first substrate at positions corresponding to the first welding pads;
assembling the first substrate and the second substrate together, and enabling the through holes to be arranged opposite to the first welding pads;
and forming an interconnection structure for connecting the first substrate and the second substrate above the first bonding pad, wherein the interconnection structure is fixed on the first bonding pad and is extruded and filled in the through hole.
2. The method of claim 1, wherein after forming the via and before forming the interconnect structure, further comprising:
and forming a metal layer on the surface of the through hole, wherein the metal layer is used for being electrically connected with the electronic device on the first substrate.
3. The method of claim 1, further comprising, prior to forming the via:
forming a cavity structure on the second surface of the first substrate, wherein the cavity structure comprises a cavity structure wall arranged on the second surface of the first substrate and a cavity space surrounded by the cavity structure wall; the cavity space is used for accommodating a first chip arranged on the first surface of the second substrate;
the through holes which vertically penetrate through the first surface and the second surface of the first substrate are formed at positions corresponding to the first welding pads, and the through holes are specifically as follows:
and forming through holes which vertically penetrate through the first surface and the second surface of the first substrate and the cavity structure wall at positions corresponding to the first welding pads.
4. The method of claim 1, wherein a fill height of the interconnect structure within the via is at least 30% of a via depth.
5. The method of claim 1, wherein the interconnect structure is a rivet structure.
6. The method of any of claims 1-5, wherein prior to assembling the first substrate and the second substrate together, further comprising:
coating a conductive bonding material capable of being cured and molded on the first welding pad;
the forming of the interconnection structure for connecting the first substrate and the second substrate above the first pad specifically includes:
extruding the conductive bonding material which is coated on the first welding pad and can be solidified and molded while the first substrate and the second substrate are assembled, so that the conductive bonding material flows into the through hole;
and curing the conductive bonding material capable of being cured and molded, thereby forming an interconnection structure for connecting the first substrate and the second substrate.
7. The method of claim 6, wherein the conductive adhesive material is a conductive glue.
8. The method according to any one of claims 1 to 5, wherein a solder resist layer is further provided on the first surface of the second substrate, the solder resist layer being located around the first pad.
9. The method of claim 8, wherein the solder mask is a solder mask defining structure or a non-solder mask defining structure.
10. The method according to any one of claims 1 to 5, wherein assembling the first substrate and the second substrate together comprises:
and attaching and assembling the first substrate and the second substrate together by adopting a surface mounting process.
11. The method according to any one of claims 1-5, further comprising:
and forming a second welding pad on the second surface of the second substrate, wherein the second welding pad is used for being electrically connected with an external circuit.
12. The method of any of claims 1-5, further comprising, prior to assembling:
forming a third substrate on the first surface of the first substrate; the third substrate is electrically connected with the first substrate;
forming a second chip over the third substrate, the second chip being electrically connected to a surface of the third substrate.
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