CN104659021A - Three-dimensional wafer level fan-out PoP encapsulating structure and preparation method for encapsulating structure - Google Patents
Three-dimensional wafer level fan-out PoP encapsulating structure and preparation method for encapsulating structure Download PDFInfo
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- CN104659021A CN104659021A CN201410848910.5A CN201410848910A CN104659021A CN 104659021 A CN104659021 A CN 104659021A CN 201410848910 A CN201410848910 A CN 201410848910A CN 104659021 A CN104659021 A CN 104659021A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
The invention discloses a three-dimensional wafer level fan-out PoP encapsulating structure and a preparation method for the encapsulating structure. The three-dimensional wafer level fan-out PoP encapsulation is formed by stacking of one or more fan-out PoP encapsulating units; each fan-out PoP encapsulating unit comprises an IC chip, metallic convex point structures, a plastic encapsulated material, metal layers, dielectric material layers, re-wiring metallic wiring layers and welding balls; the method comprises the following steps: configuring a metal base material round disc; preparing the metallic convex point structure on the upper surface of the round disc; flipping the chip patch and conducting plastic encapsulating; forming a through hole in the plastic encapsulated material; preparing the metallic convex point structure in the through hole; preparing the re-wiring metallic wiring layers; configuring and removing the round disc; etching the lower surface of the round disc to form the re-wiring metallic wiring layers; conducting stacking reflow welding; removing the round disc; forming the three-dimensional round disc level fan-out PoP encapsulation through ball planting and reflow welding. According to the invention, the problems of packaging density, cost and reliability existing in the conventional PoP encapsulating technologies are solved.
Description
Technical field
The present invention relates to microelectronic packaging technology and three-dimensional integration technology field, particularly one three-dimensional wafer level fan-out PoP encapsulation technology and manufacture method thereof.
Background technology
Along with Electronic Packaging product is to the development of high density, multi-functional, low-power consumption, miniaturization, the system in package (System in Package, SiP) of three-dimensional integration technology is adopted to achieve the development of advancing by leaps and bounds.Silicon through hole (Through Silicon Via, TSV) technical scheme, the highest owing to having stacking density, overall dimension is minimum, and the features such as significant increase chip speed and reduction power consumption are the optimal cases realizing three-dimensional integration technology.But, problems such as the manufacture difficulty that current TSV technology faces, process costs and finished product yield, reliability and outstanding.The three-dimensional integration technology of existing maturation is mainly stacked package (Package on Package, PoP), and wherein upper and lower packaging body is generally the encapsulating structure adopting tellite.Because tellite has certain thickness, and cost is higher, and the height causing whole PoP to encapsulate and cost are difficult to effectively be reduced, and is difficult to the requirement meeting high density and low cost.The difference due to upper and lower package body structure of existing PoP encapsulation, causes warpage of packaging assembly in process for making to be difficult to be effectively controlled, has a strong impact on solder-ball interconnections reliability of structure.The manufacturing process of existing PoP encapsulation, owing to adopting traditional non-wafer level packaging manufacturing mode, causes that efficiency is low and cost is high, is unfavorable for the popularization that PoP encapsulates.
Therefore, still need new encapsulating structure and manufacturing technology, to solve the problem existing for prior art.
Summary of the invention
The present invention is directed to three-dimensional PoP encapsulation technology and propose a kind of encapsulating structure and manufacture method, to solve packaging density, cost and the integrity problem existing for existing PoP encapsulation technology.
To achieve these goals, the present invention adopts following technical proposals:
A kind of three-dimensional wafer level fan-out PoP encapsulating structure, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes the first metal salient point structure, IC chip, salient point, the first capsulation material, the second metal salient point structure, first wiring metal routing layer, the first metal layer, the first dielectric materials layer, second wiring metal routing layer, the second dielectric materials layer, the second metal level more again, described IC chip is with salient point, salient point is connected in the first metal salient point structure, the the first metal salient point anatomical connectivity be not connected with salient point has the second metal salient point structure, first capsulation material encloses the first metal salient point structure, IC chip, salient point and the second metal salient point structure, IC chip and the second metal salient point structure with first again wiring metal routing layer be connected, first again wiring metal routing layer is manufactured with the first metal layer, first dielectric materials layer encirclement first wiring metal routing layer again, and be coated in IC chip, second metal salient point structure and the first capsulation material same side, the second dielectric materials layer is coated with in the first metal salient point structure and another side of the first capsulation material, second dielectric materials layer encirclement second wiring metal routing layer again, second again wiring metal routing layer be connected with the first metal salient point structure, second again wiring metal routing layer is manufactured with the first metal layer,
Second metal level of two packaging bodies staggered relatively is connected by the first soldered ball, and on the first metal layer of a packaging body, connect the second soldered ball, forms a fan-out PoP encapsulation unit;
Second soldered ball of described fan-out PoP encapsulation unit is connected with the first metal layer of a fan-out PoP encapsulation unit staggered relatively again, described do not plant ball portion the first metal layer, a pair second metal levels of the first soldered ball and connection thereof, the second soldered ball and connection thereof a pair the first metal layer be surrounded by the second capsulation material, form a three-dimensional wafer level fan-out PoP encapsulating structure.
Utilize this structure, first packaging body is due to without board structure, and directly realize with external environment condition by wiring metal routing layer more interconnected, therefore overall package body thickness can significantly be reduced, and manufacturing cost is also reduced; Further, the moulding compound through hole TMV of low cost has the function of the same interconnected conducting of upper and lower structure of TSV, therefore can replace TSV structure and realize pitch interconnect port, thus make between upper and lower packaging body, and be largely increased with the I/O interconnecting channels quantity of external structure and density, improve the density of encapsulation; In addition, fan-out (Fan-Out) characteristic of three-dimensional wafer level fan-out PoP encapsulating structure significantly can increase the I/O interconnecting channels quantity of PoP encapsulation.Finally, because fan-out PoP encapsulation units all in three-dimensional wafer level fan-out PoP encapsulating structure is identical, and all carry out stacking Reflow Soldering by face-to-face mode, therefore three-dimensional wafer level fan-out PoP encapsulation has high symmetry, thus greatly can improve the warpage of encapsulation.
Moulding compound through hole is adopted to realize between upper and lower packaging body, and integrated interconnected with the three-dimensional of external structure.
First metal salient point structure can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten.
Second metal salient point structure can be but be not limited to metal material or the braze materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten.
First again wiring metal routing layer and second again wiring metal routing layer can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten.
First dielectric materials layer and the second dielectric materials layer can be but be not limited to the insulating material such as thermosetting capsulation material, plug socket resin, ink and welding resistance green oil.
The upper surface of the back side of IC chip, the upper surface of the first capsulation material and the second metal salient point structure at grade.
Three-dimensional wafer level fan-out PoP encapsulation, by the stacking formation of at least one fan-out PoP encapsulation unit, realizes interconnected by the second soldered ball between adjacent fan-out PoP encapsulation unit.
In first capsulation material, through hole adopts laser or mechanical tapping, or adopts special plastic package die directly to be formed during plastic package process.
The salient point of IC chip can be but be not limited to copper pillar bump.
A manufacture method for three-dimensional wafer level fan-out PoP encapsulating structure, is characterized in that, carry out according to following steps:
Step 1: prepare the first carrier disk, is configured on the first carrier disk by the first adhesive material by metal base disk;
Step 2: adopt etching or electro-plating method to make the first metal salient point structure at the upper surface of metal base disk;
Step 3: the IC flip-chip attachment with salient point is configured in the first metal salient point structure;
Step 4: adopt high-temperature heating injection moulding process, the coated sealing of the first capsulation material is had IC chip and the first metal salient point structure of salient point, and expose the back side of IC chip, carry out baking Post RDBMS after plastic packaging;
Step 5: adopt laser or mechanical tapping method to make through hole in the first capsulation material, expose the upper surface of the first metal salient point structure;
Step 6: adopt plating or liquid metal fill method to form the second metal salient point structure in the through hole made, the first metal salient point structure and the second metal salient point structure form moulding compound through hole jointly;
Step 7: at the back side of IC chip, the upper surface of the second metal salient point structure and the upper surface of the first capsulation material apply the first dielectric materials layer, adopt plating or chemical plating method making first wiring metal routing layer again, first again wiring metal routing layer make the first metal layer, adopts the first dielectric materials layer coating parcel first wiring metal routing layer again;
Step 8: above-mentioned steps 7 is made the structural allocation of formation on Second support disk by the 3rd adhesive material;
Step 9: remove the first carrier disk and the first adhesive material by methods such as machinery, etching or exposures;
Step 10: adopt the engraving method lower surface to metal base disk identical with step 2 to etch, formation second wiring metal routing layer again, second again wiring metal routing layer make the second metal level, adopts the second dielectric materials layer coating parcel second wiring metal routing layer again;
Step 11: carry out planting ball technique on the second metal level, and carry out reflow soldering process, obtain the first soldered ball be arranged in array;
Step 12: structure above-mentioned steps 11 being made formation carries out face-to-face stacking reflow soldering process, and the first soldered ball becomes the interconnect architecture of upper and lower structure;
Step 13: remove Second support disk and the 3rd adhesive material by methods such as machinery, etching or exposures;
Step 14: carry out on the first metal layer planting ball and reflow soldering process, obtain the second soldered ball be arranged in array, forms fan-out PoP encapsulation unit;
Step 15: at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit;
Step 16: adopt high-temperature heating injection moulding process, the second capsulation material is carried out coated sealing, carries out baking Post RDBMS technique after plastic packaging, form three-dimensional wafer level fan-out PoP and encapsulate;
Step 17: the product array adopting blade cuts method separation three-dimension wafer level fan-out PoP encapsulation, forms single 3 D wafer level fan-out PoP encapsulation.
In described step 5, in the first capsulation material, through hole adopts special plastic package die directly to be formed.
Accompanying drawing explanation
Fig. 1 is the schematic diagram configuring metal base disk on the first carrier disk;
Fig. 2 is the schematic diagram making the first metal salient point structure on metal base disk;
Fig. 3 is the schematic diagram configuring IC chip on metal base disk;
Fig. 4 is sealed in coated to IC chip, salient point and metal salient point structure in the first capsulation material, and exposes the schematic diagram at the back side of IC chip;
Fig. 5 is the schematic diagram making through hole on the first capsulation material;
Fig. 6 is the schematic diagram making the second metal salient point structure in through-holes;
Fig. 7 is making first wiring metal routing layer again, and first again wiring metal routing layer make the first metal layer, adopts the schematic diagram of the first dielectric materials layer coating parcel first wiring metal routing layer again;
Fig. 8 is the schematic diagram of configuration Second support disk;
Fig. 9 is the schematic diagram of removal first carrier disk;
Figure 10 adopts the lower surface of engraving method to metal base disk to etch, formation second wiring metal routing layer again, second again wiring metal routing layer make the second metal level, adopts the schematic diagram of the second dielectric materials layer coating parcel second wiring metal routing layer again;
Figure 11 carries out planting ball and reflow soldering process on the second metal level, obtains the schematic diagram of the first welded ball array;
Figure 12 is the schematic diagram carrying out face-to-face stacking reflow soldering process;
Figure 13 is the schematic diagram removing Second support disk;
Figure 14 carries out planting ball and reflow soldering process on the first metal layer, obtains the second welded ball array, forms the schematic diagram of fan-out PoP encapsulation unit;
Figure 15 is the schematic diagram at least one fan-out PoP encapsulation unit being carried out stacking Reflow Soldering;
Figure 16 is the schematic diagram that three-dimensional wafer level fan-out PoP encapsulates an embodiment.
In figure, 100 be the first carrier disk, 100a be that the first adhesive material, 200 is Second support disk, 200a is the 3rd adhesive material, 1 be IC chip for metal base disk, 2 is the first metal salient point structure, 3,4 for salient point, 5 be the first capsulation material, 6 to be the second metal salient point structure, 7 be first again wiring metal routing layer, 8 for the first metal layer, 9, to be the first dielectric materials layer, 10 be that second wiring metal routing layer, 11 is the second dielectric materials layer, 12 be again the second metal level, 13 be the first soldered ball, 14 be the second soldered ball, 15 is the second capsulation material.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As shown in figure 16, a kind of three-dimensional wafer level fan-out PoP encapsulating structure, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes the first metal salient point structure 2, IC chip 3, salient point 4, first capsulation material 5, second metal salient point structure 6, first wiring metal routing layer 7, the first metal layer 8, first dielectric materials layer 9, second wiring metal routing layer 10, second dielectric materials layer 11, second metal level 12 more again, described IC chip 3 is with salient point 4, salient point 4 is connected in the first metal salient point structure 2, the the first metal salient point structure 2 be not connected with salient point 4 is connected with the second metal salient point structure 6, first capsulation material 5 encloses the first metal salient point structure 2, IC chip 3, salient point 4 and the second metal salient point structure 6, IC chip 3 and the second metal salient point structure 6 with first again wiring metal routing layer 7 be connected, first again wiring metal routing layer 7 is manufactured with the first metal layer 8, first dielectric materials layer 9 surrounds the first wiring metal routing layer 7 again, and be coated in IC chip 3, second metal salient point structure 6 and the first capsulation material 5 same side, the second dielectric materials layer 11 is coated with in the first metal salient point structure 2 and first another side of capsulation material 5, second dielectric materials layer 11 surrounds the second wiring metal routing layer 10 again, second again wiring metal routing layer 10 be connected with the first metal salient point structure 2, second again wiring metal routing layer 10 is manufactured with the first metal layer 12,
First soldered ball 13 connects the second metal level 12 of two packaging bodies staggered relatively, and connects the second soldered ball 14 on the first metal layer 8 of a packaging body, forms a fan-out PoP encapsulation unit;
Second soldered ball 14 of described fan-out PoP encapsulation unit is connected with the first metal layer 8 of a fan-out PoP encapsulation unit staggered relatively again, a pair the first metal layer 8 of described the first metal layer 8, first soldered ball 13 and a pair second metal level 12, second soldered balls 14 connected and connection thereof of not planting ball portion is surrounded by the second capsulation material 15, forms a three-dimensional wafer level fan-out PoP encapsulating structure.
First metal salient point structure 2 and the second metal salient point structure 6 can be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material or braze material composition.
First again wiring metal routing layer 7 and second again wiring metal routing layer 10 can be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material.
First dielectric materials layer 9 and the second dielectric materials layer 11 can be but be not limited to the insulating material such as thermosetting capsulation material, plug socket resin, ink and welding resistance green oil.
The upper surface of the back side of IC chip 3, the upper surface of the first capsulation material 5 and the second metal salient point structure 6 at grade.
The salient point 4 of IC chip 3 can be but be not limited to copper pillar bump.
Below by for the three-dimensional wafer level fan-out PoP encapsulating structure of embodiment in the present invention, describe the manufacturing process of three-dimensional wafer level fan-out PoP encapsulating structure in detail with Fig. 1 to Figure 16.
Step 1: prepare the first carrier disk, is configured on the first carrier disk by the first adhesive material by metal base disk, as shown in Figure 1.
Please refer to Fig. 1, preparing the first carrier disk 100, first carrier disk 100 can be metal, wafer, glass, macromolecule organic material etc.By the first adhesive material 100a, metal base disk 1 is configured on the first carrier disk 100.In the present invention, metal base disk 1 can be the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, and prioritizing selection copper or Cu alloy material, the first adhesive material 100a can be but be not limited to the material such as adhesive tape, macromolecule resin.The size of metal base disk 1 is not more than the size of the first carrier disk 100.
Step 2: make the first metal salient point structure at metal base disk upper surface, as shown in Figure 2.
Please refer to Fig. 2, make the first metal salient point structure 2 at the upper surface of metal base disk 1.In the present invention, the first metal salient point structure 2 adopts etching or electro-plating method to make.In engraving method, apply at the upper surface of metal base disk 1 or paste light sensation wet film or dry film, figure is made by exposure imaging method, there is the light sensation wet film of figure or dry film as resist layer, select the etching solution of only etching metal base material disk 1 to etch its upper surface, form the first metal salient point structure 2.In electro-plating method, apply at the upper surface of metal base disk 1 or paste and there is certain thickness light sensation wet film or dry film, figure is made by exposure imaging method, adopt electro-plating method to make formation first metal salient point structure 2, the thickness of light sensation wet film or dry film will exceed the height dimension of the first made metal salient point structure 2.In the present invention, the first metal salient point structure 2 can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten.
Step 3: the IC flip-chip attachment with salient point is configured in the first metal salient point structure, as shown in Figure 3.
Please refer to Fig. 3, adopt upside-down mounting patch device the IC chip 3 upside-down mounting attachment with salient point 4 to be configured in the first metal salient point structure 2, and carry out reflux technique and realize electrical interconnection.In the present invention, the salient point 4 on IC chip 3 can be but be not limited to copper pillar bump.
Step 4: adopt injection moulding process to have the IC chip of salient point and the first metal salient point structure is coated is sealed in the first capsulation material, and expose the back side of IC chip, carry out baking Post RDBMS after plastic packaging, as shown in Figure 4.
Please refer to Fig. 4, adopt high-temperature heating injection moulding process, the coated sealing of environment-friendly type first capsulation material 5 of low water absorption, low stress had IC chip 3 and the first metal salient point structure 2 of salient point 4, and exposing the back side of IC chip 3, the back side of IC chip 3 and the surface of the first capsulation material 5 are at grade.In the present invention, the first capsulation material 5 is the materials such as thermosetting polymer.Baking Post RDBMS technique is carried out after plastic packaging.
Step 5: make through hole on the first capsulation material, exposes the upper surface of the first metal salient point structure, as shown in Figure 5.
Please refer to Fig. 5, adopt laser or mechanical tapping method to make through hole in the first capsulation material 5, or adopt special plastic package die directly to form through hole in step 4, expose the upper surface of the first metal salient point structure 2.
Step 6: make the second metal salient point structure in through-holes, as shown in Figure 6.
Please refer to Fig. 6, make the second metal salient point structure 6 in through-holes, plating or liquid metal fill method is adopted to form the second metal salient point structure 6 in the through hole made, second metal salient point structure 6 can be the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten, or braze material forms, but is not limited to these materials.In the present invention, the second metal salient point structure 6 also can adopt the printing process of braze cream to make formation.First metal salient point structure 2 and the second metal salient point structure 6 be composition moulding compound through hole TMV jointly.
Step 7: making first wiring metal routing layer again, first again wiring metal routing layer make the first metal layer, adopts the first dielectric materials layer coating parcel first wiring metal routing layer again, as shown in Figure 7.
Please refer to Fig. 7, at the back side of IC chip 3, the upper surface of the second metal salient point structure 6 and the upper surface of the first capsulation material 5 apply the first dielectric materials layer 9, on the first dielectric materials layer 9, figure is formed by exposure, developing method, adopt plating or chemical plating method making first wiring metal routing layer 7 again, first again wiring metal routing layer 7 make the first metal layer 8, adopts the first dielectric materials layer 9 to apply parcel first wiring metal routing layer 7 again.In the present invention, first again wiring metal routing layer 7 can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten, the first metal layer 8 can be but be not limited to be the metallic multilayer structures combinations such as copper, nickel, gold, titanium, tin, and the first dielectric materials layer 9 can be but be not limited to the insulating material such as thermosetting capsulation material, plug socket resin, ink and welding resistance green oil.
Step 8: configuration Second support disk, as shown in Figure 8.
Please refer to Fig. 8, by the 3rd adhesive material 200a, above-mentioned steps 7 is made the structural allocation of formation on Second support disk 200.In the present invention, Second support disk 200 can be metal, wafer, glass, macromolecule organic material etc., and the 3rd adhesive material 200a can be but be not limited to the material such as adhesive tape, macromolecule resin.
Step 9: remove the first carrier disk, as shown in Figure 9.
Please refer to Fig. 9, remove the first carrier disk 100 and the first adhesive material 100a by methods such as machinery, etching or exposures.
Step 10: adopt the lower surface of engraving method to metal base disk to etch, formation second wiring metal routing layer again, second again wiring metal routing layer make the second metal level, adopts the second dielectric materials layer coating parcel second wiring metal routing layer again, as shown in Figure 10.
Please refer to Figure 10, the engraving method lower surface to metal base disk 1 identical with step 2 is adopted to etch, formation second wiring metal routing layer 10 again, second again wiring metal routing layer 10 make the second metal level 12, adopts the second dielectric materials layer 11 to apply parcel second wiring metal routing layer 10 again.In the present invention, the second metal level 12 is but is not limited to be the metallic multilayer structures combinations such as copper, nickel, gold, titanium, tin.
Step 11: carry out planting ball and reflow soldering process on the second metal level, obtain the first welded ball array, as shown in figure 11.
Please refer to Figure 11, the second metal level 12 carries out planting ball technique, and carries out reflow soldering process, obtain the first soldered ball 13 be arranged in array.
Step 12: structure above-mentioned steps 11 formed carries out face-to-face stacking reflow soldering process, as shown in figure 12.
Please refer to Figure 12, structure above-mentioned steps 11 being made formation carries out face-to-face stacking reflow soldering process, and the first soldered ball 13 becomes the interconnect architecture of upper and lower structure.
Step 13: remove Second support disk, as shown in figure 13.
Please refer to Figure 13, remove Second support disk 200 and the 3rd adhesive material 200a by methods such as machinery, etching or exposures.
Step 14: carry out on the first metal layer planting ball and reflow soldering process, obtain the second welded ball array, forms fan-out PoP encapsulation unit, as shown in figure 14.
Please refer to Figure 14, the first metal layer 8 carries out plant ball and reflow soldering process, obtain the second soldered ball 14 be arranged in array, form fan-out PoP encapsulation unit.
Step 15: at least one fan-out PoP encapsulation unit carries out stacking Reflow Soldering, as shown in figure 15.
Please refer to Figure 15, at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball 14 becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit.
Step 16: carry out plastic package process, forms three-dimensional wafer level fan-out PoP and encapsulates, as shown in figure 16.
Please refer to Figure 16, adopt high-temperature heating injection moulding process, environment-friendly type second capsulation material 15 of low water absorption, low stress is carried out coated sealing, after plastic packaging, carries out baking Post RDBMS technique, form three-dimensional wafer level fan-out PoP and encapsulate.
Step 17: cutting forms single three-dimensional wafer level fan-out PoP and encapsulates.As shown in figure 16, this figure is single POP packaging part after cutting.
Adopt the product array of blade cuts method separation three-dimension wafer level fan-out PoP encapsulation, form single 3 D wafer level fan-out PoP encapsulation.
The active face of IC chip refers to the side with integrated circuit, is generally positioned at the surface of chip, not shown.
Moulding compound through hole English is TMV (Through Mold Via).
For effectively illustrating and describing object of the present invention to the description of embodiments of the invention; and be not used to limit the present invention; belonging to any, those skilled in the art is to be understood that: within the spirit and principles in the present invention all; any amendment of doing, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a three-dimensional wafer level fan-out PoP encapsulating structure, is characterized in that, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes the first metal salient point structure (2), IC chip (3), salient point (4), the first capsulation material (5), the second metal salient point structure (6), first wiring metal routing layer (7), the first metal layer (8), the first dielectric materials layer (9), second wiring metal routing layer (10), the second dielectric materials layer (11), the second metal level (12) more again, described IC chip (3) is with salient point (4), salient point (4) is connected in the first metal salient point structure (2), the the first metal salient point structure (2) be not connected with salient point (4) is connected with the second metal salient point structure (6), first capsulation material (5) encloses the first metal salient point structure (2), IC chip (3), salient point (4) and the second metal salient point structure (6), IC chip (3) and the second metal salient point structure (6) with first again wiring metal routing layer (7) be connected, first again wiring metal routing layer (7) is manufactured with the first metal layer (8), first dielectric materials layer (9) encirclement first wiring metal routing layer (7) again, and be coated in IC chip (3), second metal salient point structure (6) and the first capsulation material (5) same side, the second dielectric materials layer (11) is coated with in the first metal salient point structure (2) and the first capsulation material (5) another side, second dielectric materials layer (11) encirclement second wiring metal routing layer (10) again, second again wiring metal routing layer (10) be connected with the first metal salient point structure (2), second again wiring metal routing layer (10) is manufactured with the first metal layer (12),
Second metal level (12) of two packaging bodies staggered relatively connects the first soldered ball (13), and at upper connection second soldered ball (14) of the first metal layer (8) of a packaging body, form a fan-out PoP encapsulation unit;
Second soldered ball (14) of described fan-out PoP encapsulation unit is connected with the first metal layer (8) of a fan-out PoP encapsulation unit staggered relatively again, described the first metal layer (8), the first soldered ball (13) and a pair second metal levels (12) connected thereof, the second soldered ball (14) and a pair the first metal layer (8) of connecting thereof of not planting ball portion is surrounded by the second capsulation material (15), forms a three-dimensional wafer level fan-out PoP encapsulating structure.
2. a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, the first metal salient point structure (2) and the second metal salient point structure (6) are but are not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material or braze material composition.
3. a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, first again wiring metal routing layer (7) and second again wiring metal routing layer (10) be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy or tungsten metal material.
4. a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, the first dielectric materials layer (9) and the second dielectric materials layer (11) are but are not limited to thermosetting capsulation material, plug socket resin, ink or welding resistance green oil insulating material.
5. a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, the upper surface of the back side of IC chip (3), the upper surface of the first capsulation material (5) and the second metal salient point structure (6) at grade.
6. a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, the salient point (4) of IC chip (3) is but is not limited to copper pillar bump.
7. a manufacture method for three-dimensional wafer level fan-out PoP encapsulating structure, is characterized in that, carry out according to following steps:
Step 1: prepare the first carrier disk (100), is configured on the first carrier disk (100) by the first adhesive material (100a) by metal base disk (1);
Step 2: adopt etching or electro-plating method to make the first metal salient point structure (2) at the upper surface of metal base disk (1);
Step 3: IC chip (3) the upside-down mounting attachment with salient point (4) is configured in the first metal salient point structure (2);
Step 4: adopt high-temperature heating injection moulding process, first capsulation material (5) coated sealing had IC chip (3) and the first metal salient point structure (2) of salient point (4), and expose the back side of IC chip (3), carry out baking Post RDBMS after plastic packaging;
Step 5: adopt laser or mechanical tapping method to make through hole in the first capsulation material (5), expose the upper surface of the first metal salient point structure (2);
Step 6: adopt plating or liquid metal fill method to form the second metal salient point structure (6) in the through hole made, the first metal salient point structure (2) and the second metal salient point structure (6) be composition moulding compound through hole jointly;
Step 7: at the back side of IC chip (3), the upper surface of the second metal salient point structure (6) and the upper surface of the first capsulation material (5) apply the first dielectric materials layer (9), adopt plating or chemical plating method making first wiring metal routing layer (7) again, first again wiring metal routing layer (7) make the first metal layer (8), adopts the first dielectric materials layer (9) to apply parcel first wiring metal routing layer (7) again;
Step 8: above-mentioned steps 7 is made the structural allocation of formation on Second support disk (200) by the 3rd adhesive material (200a);
Step 9: remove the first carrier disk (100) and the first adhesive material (100a) by machinery, etching or exposure method;
Step 10: adopt the engraving method lower surface to metal base disk 1 identical with step 2 to etch, formation second wiring metal routing layer (10) again, making second metal level (12) on second again wiring metal routing layer (10), adopts the second dielectric materials layer (11) to apply parcel second wiring metal routing layer (10) again;
Step 11: carry out planting ball technique on the second metal level (12), and carry out reflow soldering process, obtains the first soldered ball (13) be arranged in array;
Step 12: structure above-mentioned steps 11 being made formation carries out face-to-face stacking reflow soldering process, and the first soldered ball (13) becomes the interconnect architecture of upper and lower structure;
Step 13: remove Second support disk (200) and the 3rd adhesive material (200a) by machinery, etching or exposure method;
Step 14: carry out planting ball and reflow soldering process on the first metal layer (8), obtains the second soldered ball (14) be arranged in array, and forms fan-out PoP encapsulation unit;
Step 15: at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball (14) becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit;
Step 16: adopt high-temperature heating injection moulding process, the second capsulation material (15) is carried out coated sealing, carries out baking Post RDBMS technique after plastic packaging, form three-dimensional wafer level fan-out PoP and encapsulate;
Step 17: the product array adopting blade cuts method separation three-dimension wafer level fan-out PoP encapsulation, forms single 3 D wafer level fan-out PoP encapsulation.
8. the manufacture method of a kind of three-dimensional wafer level fan-out PoP encapsulating structure according to claim 7, it is characterized in that, in described step 5, in the first capsulation material, through hole adopts special plastic package die directly to be formed.
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