CN104505382A - Wafer-level fan-out PoP encapsulation structure and making method thereof - Google Patents
Wafer-level fan-out PoP encapsulation structure and making method thereof Download PDFInfo
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- CN104505382A CN104505382A CN201410843472.3A CN201410843472A CN104505382A CN 104505382 A CN104505382 A CN 104505382A CN 201410843472 A CN201410843472 A CN 201410843472A CN 104505382 A CN104505382 A CN 104505382A
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Abstract
The invention discloses a wafer-level fan-out PoP encapsulation structure and a making method thereof. The wafer-level fan-out PoP encapsulation structure is formed by stacking at least one fan-out PoP encapsulation units, each two adjacent fan-out PoP encapsulation units are connected through a second welding ball and coated and sealed by adopting a second plastic sealing material, each fan-out PoP encapsulation unit comprises an IC chip, a first plastic sealing material, a second binding material, a metal salient point structure, a first metal layer, a second metal layer, a first rewiring metal routing layer, a first dielectric material layer, a second rewiring metal routing layer, a second dielectric material layer, a first welding ball and the second welding ball, a bonding pad of each IC chip is connected with the corresponding first rewiring metal routing layer, each metal salient point structure forms a molded plastic through hole, and three-dimensional integrated interconnection between an upper encapsulating body as well as a lower encapsulating body in each fan-out PoP encapsulation unit and an external structure is realized through the corresponding molded plastic through hole. The making method mainly includes arranging a metal substrate wafer on a first carrier wafer; making the metal salient point structure on the surface of the metal substrate wafer; feeding the chip; plastically sealing, making the first rewiring metal routing layer; arranging a second carrier wafer, removing the first carrier wafer, etching the lower surface of the metal substrate wafer to form the second rewiring metal routing layer; performing stacking and reflow soldering; removing the second carrier wafer; forming the fan-out PoP encapsulation unit after ball placing and reflow soldering processes; performing stacking and reflow soldering on the fan-out PoP encapsulation units; and forming the wafer-level fan-out PoP encapsulation structure after plastic sealing. By the wafer-level fan-out PoP encapsulation structure and the making method, the problems of encapsulating density, cost and reliability of existing PoP encapsulation technology are solved.
Description
Technical field
The present invention relates to microelectronic packaging technology and three-dimensional integration technology field, particularly one three-dimensional wafer level fan-out PoP encapsulation technology and manufacture method thereof.
Background technology
Along with Electronic Packaging product is to the development of high density, multi-functional, low-power consumption, miniaturization, the system in package (System in Package, SiP) of three-dimensional integration technology is adopted to achieve the development of advancing by leaps and bounds.Silicon through hole (Through Silicon Via, TSV) technical scheme, the highest owing to having stacking density, overall dimension is minimum, and the features such as significant increase chip speed and reduction power consumption are the optimal cases realizing three-dimensional integration technology.But, problems such as the manufacture difficulty that current TSV technology faces, process costs and finished product yield, reliability and outstanding.The three-dimensional integration technology of existing maturation is mainly stacked package (Package on Package, PoP), and wherein upper and lower packaging body is generally the encapsulating structure adopting tellite.Because tellite has certain thickness, and cost is higher, and the height causing whole PoP to encapsulate and cost are difficult to effectively be reduced, and is difficult to the requirement meeting high density and low cost.The difference due to upper and lower package body structure of existing PoP encapsulation, causes warpage of packaging assembly in process for making to be difficult to be effectively controlled, has a strong impact on solder-ball interconnections reliability of structure.The manufacturing process of existing PoP encapsulation, owing to adopting traditional non-wafer level packaging manufacturing mode, causes that efficiency is low and cost is high, is unfavorable for the popularization that PoP encapsulates.
Therefore, still need new encapsulating structure and manufacturing technology, to solve the problem existing for prior art.
Summary of the invention
The present invention is directed to three-dimensional PoP encapsulation technology and propose a kind of encapsulating structure and manufacture method, to solve packaging density, cost and the integrity problem existing for existing PoP encapsulation technology.
To achieve these goals, the present invention adopts following technical proposals:
A kind of wafer level fan-out PoP encapsulating structure, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes metal salient point structure, IC chip, bonding welding pad, the second adhesive material, and the first capsulation material, first is wiring metal routing layer, the first metal layer, the first dielectric materials layer, second wiring metal routing layer, the second dielectric materials layer, the second metal level more again; Described IC chip is with bonding welding pad, second adhesive material is pasted on the surface of IC chip, first capsulation material surrounds metal salient point structure and IC chip, the bonding welding pad of IC chip with first again wiring metal routing layer be connected, first again wiring metal routing layer is manufactured with the first metal layer, first dielectric materials layer encirclement first wiring metal routing layer again, and be coated in IC chip, metal salient point structure and the first capsulation material same side; Be coated with the second dielectric materials layer in IC chip, metal salient point structure and another side of the first capsulation material, the second dielectric materials layer surrounds the second wiring metal routing layer again, and second again wiring metal routing layer is manufactured with the first metal layer;
Second metal level of two packaging bodies staggered relatively is connected by the first soldered ball, and on the first metal layer of a packaging body, connect the second soldered ball, forms a fan-out PoP encapsulation unit;
Second soldered ball is connected with the first metal layer of a fan-out PoP encapsulation unit staggered relatively again, described do not plant ball portion the first metal layer, a pair second metal levels of the first soldered ball and connection thereof, the second soldered ball and connection thereof a pair the first metal layer be surrounded by the second capsulation material, form a wafer level fan-out PoP encapsulating structure.
Metal salient point structure can be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material.
First again wiring metal routing layer and second again wiring metal routing layer can be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material.
The upper surface of the active face of IC chip, the upper surface of metal salient point structure and the first capsulation material at grade.
Utilize this structure, first packaging body is due to without board structure, and directly realize with external environment condition by wiring metal routing layer more interconnected, therefore overall package body thickness can significantly be reduced, and manufacturing cost is also reduced; Further, the moulding compound through hole TMV of low cost has the function of the same interconnected conducting of upper and lower structure of TSV, therefore can replace TSV structure and realize pitch interconnect port, thus make between upper and lower packaging body, and be largely increased with the I/O interconnecting channels quantity of external structure and density, improve the density of encapsulation; In addition, fan-out (Fan-Out) characteristic of wafer level fan-out PoP encapsulating structure significantly can increase the I/O interconnecting channels quantity of PoP encapsulation.Finally, because fan-out PoP encapsulation units all in wafer level fan-out PoP encapsulating structure is identical, and all carry out stacking Reflow Soldering by face-to-face mode, therefore wafer level fan-out PoP encapsulation has high symmetry, thus greatly can improve the warpage of encapsulation.
A manufacture method for wafer level fan-out PoP encapsulating structure, specifically carry out according to following steps:
Step 1: prepare the first carrier disk, is configured on the first carrier disk by the first adhesive material by metal base disk;
Step 2: make metal salient point structure by etching or electro-plating method at the upper surface of metal base disk;
Step 3: by the second adhesive material by IC chip configuration on metal base disk, IC chip is with bonding welding pad;
Step 4: adopt high-temperature heating injection moulding process, by the environment-friendly type first capsulation material coated sealing IC chip of low water absorption, low stress and metal salient point structure, and expose the active face of IC chip and the upper surface of metal salient point structure, carry out baking Post RDBMS technique after plastic packaging;
Step 5: apply the first dielectric materials layer at the upper surface of the active face of IC chip, the upper surface of metal salient point structure and the first capsulation material, on the first dielectric materials layer, figure is formed by exposure, developing method, adopt plating or chemical plating method making first wiring metal routing layer again, first again wiring metal routing layer make the first metal layer, adopt the first dielectric materials layer coating parcel first wiring metal routing layer again, wiring metal routing layer is interconnected again for the bonding welding pad of IC chip and first;
Step 6: the stickup of Second support disk is configured on the first metal layer and the first dielectric materials layer by the 3rd adhesive material;
Step 7: remove the first carrier disk and the first adhesive material by machinery, etching or exposure method;
Step 8: adopt the lower surface of engraving method to metal base disk to etch, formation second wiring metal routing layer again, second again wiring metal routing layer make the second metal level, adopts the second dielectric materials layer coating parcel second wiring metal routing layer again;
Step 9: carry out planting ball technique on the second metal level, and carry out reflow soldering process, obtain the first soldered ball be arranged in array;
Step 10: above-mentioned steps is made the structure formed and carries out face-to-face stacking reflow soldering process, the first soldered ball becomes the interconnect architecture of upper and lower structure;
Step 11: remove Second support disk and the 3rd adhesive material by machinery, etching or exposure method;
Step 12: carry out on the first metal layer planting ball and reflow soldering process, obtain the second soldered ball be arranged in array, forms fan-out PoP encapsulation unit;
Step 13: at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit;
Step 14: adopt high-temperature heating injection moulding process, the second capsulation material is carried out coated sealing, carries out baking Post RDBMS technique after plastic packaging, forms wafer level fan-out PoP encapsulation;
Step 15: cutting forms single wafer level fan-out PoP and encapsulates.
Accompanying drawing explanation
Fig. 1 is the schematic diagram configuring metal base disk on the first carrier disk;
Fig. 2 is the schematic diagram making metal salient point structure on metal base disk;
Fig. 3 is the schematic diagram configuring IC chip on metal base disk;
Fig. 4 is by IC chip and metal salient point structure is coated is sealed in the first capsulation material, and exposes the schematic diagram of the active face of IC chip and the upper surface of metal salient point structure;
Fig. 5 is making first wiring metal routing layer again, and first again wiring metal routing layer make the first metal layer, adopts the schematic diagram of the first dielectric materials layer coating parcel first wiring metal routing layer again;
Fig. 6 is the schematic diagram of configuration Second support disk;
Fig. 7 is the schematic diagram of removal first carrier disk;
Fig. 8 adopts the lower surface of engraving method to metal base disk to etch, formation second wiring metal routing layer again, second again wiring metal routing layer make the second metal level, adopts the schematic diagram of the second dielectric materials layer coating parcel second wiring metal routing layer again;
Fig. 9 carries out planting ball and reflow soldering process on the second metal level, obtains the schematic diagram of the first welded ball array;
Figure 10 is the schematic diagram carrying out face-to-face stacking reflow soldering process;
Figure 11 is the schematic diagram removing Second support disk;
Figure 12 carries out planting ball and reflow soldering process on the first metal layer, obtains the second welded ball array, forms the schematic diagram of fan-out PoP encapsulation unit;
Figure 13 is the schematic diagram at least one fan-out PoP encapsulation unit being carried out stacking Reflow Soldering;
Figure 14 is the schematic diagram that wafer level fan-out PoP encapsulates an embodiment.
In figure, 100 be the first carrier disk, 100a be that the first adhesive material, 200 is Second support disk, 200a is the 3rd adhesive material, 1 be metal base disk, 2 be metal salient point structure, 3 be IC chip, 4 for bonding welding pad, 5 be the second adhesive material, 6 is the first capsulation material, 7 be first again wiring metal routing layer, 8 for the first metal layer, 9, to be the first dielectric materials layer, 10 be that second wiring metal routing layer, 11 is the second dielectric materials layer, 12 be again the second metal level, 13 be the first soldered ball, 14 be the second soldered ball, 15 is the second capsulation material.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As shown in figure 14, a kind of wafer level fan-out PoP encapsulating structure, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes metal salient point structure 2, IC chip 3, bonding welding pad 4, second adhesive material 5, first capsulation material 6, first wiring metal routing layer 7, the first metal layer 8, first dielectric materials layer 9, second wiring metal routing layer 10, second dielectric materials layer 11, second metal level 12 more again; Described IC chip 3 is with bonding welding pad 4, second adhesive material 5 is pasted on the surface of IC chip 3, first capsulation material 6 surrounds metal salient point structure 2 and IC chip 3, the bonding welding pad 4 of IC chip 3 with first again wiring metal routing layer 7 be connected, first again wiring metal routing layer 7 is manufactured with the first metal layer 8, first dielectric materials layer 9 surrounds the first wiring metal routing layer 7 again, and is coated in IC chip 3, metal salient point structure 2 and the first capsulation material 6 same side; Be coated with in IC chip 3, metal salient point structure 2 and first another side of capsulation material 6 second dielectric materials layer 11, second dielectric materials layer 11 surround second again wiring metal routing layer 10, second again wiring metal routing layer 10 is manufactured with the first metal layer 12;
First soldered ball 13 connects the second metal level 12 of two packaging bodies staggered relatively, and connects the second soldered ball 14 on the first metal layer 8 of a packaging body, forms a fan-out PoP encapsulation unit;
Second soldered ball 14 is connected with the first metal layer 8 of a fan-out PoP encapsulation unit staggered relatively again, a pair the first metal layer 8 of described the first metal layer 8, first soldered ball 13 and a pair second metal level 12, second soldered balls 14 connected and connection thereof of not planting ball portion is surrounded by the second capsulation material 15, forms a wafer level fan-out PoP encapsulating structure.
The bonding welding pad 4 of IC chip 3 and first wiring metal routing layer 7 is interconnected again.Metal salient point structure 2 forms moulding compound through hole.Moulding compound through hole realizes between the upper and lower packaging body in fan-out PoP encapsulation unit, and integrated interconnected with the three-dimensional of external structure.
Below by for the wafer level fan-out PoP encapsulating structure of embodiment in the present invention, describe the manufacturing process of wafer level fan-out PoP encapsulating structure in detail with Fig. 1 to Figure 14.
A manufacture method for wafer level fan-out PoP encapsulating structure, specifically carry out according to following steps:
Step 1: prepare the first carrier disk 100, is configured on the first carrier disk 100 by the first adhesive material 100a by metal base disk 1, as shown in Figure 1.
First carrier disk 100 can be metal, wafer, glass, macromolecule organic material etc.Metal base disk 1 can be the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, and prioritizing selection copper or Cu alloy material, the first adhesive material 100a can be but be not limited to the material such as adhesive tape, macromolecule resin.The size of metal base disk 1 is not more than the size of the first carrier disk 100.
Step 2: make metal salient point structure 2 at the upper surface of metal base disk 1, as shown in Figure 2.
In the present invention, metal salient point structure 2 adopts etching or electro-plating method to make.In engraving method, apply at the upper surface of metal base disk 1 or paste light sensation wet film or dry film, figure is made by exposure imaging method, there is the light sensation wet film of figure or dry film as resist layer, select the etching solution of only etching metal base material disk 1 to etch its upper surface, form metal salient point structure 2.In electro-plating method, apply at the upper surface of metal base disk 1 or paste and there is certain thickness light sensation wet film or dry film, figure is made by exposure imaging method, adopt electro-plating method to make and form metal salient point structure 2, the thickness of light sensation wet film or dry film will exceed the height dimension of made metal salient point structure 2.In the present invention, metal salient point structure 2 can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten.
Step 3: IC chip 3 is configured on metal base disk 1 by the second adhesive material 5, IC chip 3 with bonding welding pad 4, as shown in Figure 3.
In the present invention, the second adhesive material 5 can be bonding die adhesive tape, the material such as epoxy resin containing Argent grain.After configuration IC chip 3, high-temperature baking technique need be carried out to the second adhesive material 5.
Step 4: adopt high-temperature heating injection moulding process, by the environment-friendly type first capsulation material 6 coated sealing IC chip 3 of low water absorption, low stress and metal salient point structure 2, and expose the active face of IC chip 3 and the upper surface of metal salient point structure 2, baking Post RDBMS technique is carried out, as shown in Figure 4 after plastic packaging.
First capsulation material 6 is the material such as thermosetting polymer of low water absorption, low stress, environment-friendly type.The upper surface of the active face of IC chip 3, the upper surface of metal salient point structure 2 and the first capsulation material 6 at grade.
Step 5: apply the first dielectric layer 9 at the upper surface of the active face of IC chip 3, the upper surface of metal salient point structure 2 and the first capsulation material 6, on the first dielectric materials layer 9, figure is formed by exposure, developing method, adopt plating or chemical plating method making first wiring metal routing layer 7 again, first again wiring metal routing layer 7 make the first metal layer 8, adopts the first dielectric materials layer 9 to apply parcel first wiring metal routing layer 7 again.The bonding welding pad 4 of IC chip 3 and first wiring metal routing layer 7 is interconnected again, as shown in Figure 5.
In the present invention, first again wiring metal routing layer 7 can be but be not limited to the metal materials such as copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten, the first metal layer 8 can be but be not limited to be the metallic multilayer structures combinations such as copper, nickel, gold, titanium, tin, and the first dielectric materials layer 9 can be but be not limited to the insulating material such as thermosetting capsulation material, plug socket resin, ink and welding resistance green oil.
Step 6: by the 3rd adhesive material 200a, Second support disk 200 stickup is configured on the first metal layer 8 and the first dielectric materials layer 9, as shown in Figure 6.
By the 3rd adhesive material 200a, above-mentioned steps 5 is made the structural allocation of formation on Second support disk 200.In the present invention, Second support disk 200 can be metal, wafer, glass, macromolecule organic material etc., and the 3rd adhesive material 200a can be but be not limited to the material such as adhesive tape, macromolecule resin.
Step 7: remove the first carrier disk 100 and the first adhesive material 100a by machinery, etching or exposure method, as shown in Figure 7.
Step 8: adopt the lower surface of engraving method to metal base disk 1 to etch, formation second wiring metal routing layer 10 again, second again wiring metal routing layer 10 make the second metal level 12, the second dielectric materials layer 11 is adopted to apply parcel second wiring metal routing layer 10 again, as shown in Figure 8.
In the present invention, the second metal level 12 is but is not limited to be the metallic multilayer structures combinations such as copper, nickel, gold, titanium, tin.
Step 9: carry out planting ball technique on the second metal level 12, and carry out reflow soldering process, obtains the first soldered ball 13 be arranged in array, as shown in Figure 9.
Step 10: structure above-mentioned steps 9 being made formation carries out face-to-face stacking reflow soldering process, and the first soldered ball 13 becomes the interconnect architecture of upper and lower structure, as shown in Figure 10.
Step 11: remove Second support disk 200 and the 3rd adhesive material 200a by machinery, etching or exposure method, as shown in figure 11.
Step 12: carry out planting ball and reflow soldering process on the first metal layer 8, obtains the second soldered ball 14 be arranged in array, and forms fan-out PoP encapsulation unit, as shown in figure 12.
Step 13: at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball 14 becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit, as shown in figure 13.
Step 14: adopt high-temperature heating injection moulding process, the second capsulation material 15 is carried out coated sealing, carries out baking Post RDBMS technique after plastic packaging, forms wafer level fan-out PoP encapsulation, as shown in figure 14.
Step 15: cutting forms single wafer level fan-out PoP and encapsulates.As shown in figure 14, this figure is single POP packaging part after cutting.
The active face of IC chip 3 refers to the side with integrated circuit, is generally positioned at the surface of chip, not shown.
Moulding compound through hole English is TMV (Through Mold Via).
Adopt blade cuts method to be separated the product array of wafer level fan-out PoP encapsulation, form single wafer level fan-out PoP and encapsulate.
For effectively illustrating and describing object of the present invention to the description of embodiments of the invention; and be not used to limit the present invention; belonging to any, those skilled in the art is to be understood that: within the spirit and principles in the present invention all; any amendment of doing, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a wafer level fan-out PoP encapsulating structure, is characterized in that, by the stacking formation of at least one fan-out PoP encapsulation unit; A fan-out PoP encapsulation unit is made up of the packaging body of two same structures;
A described packaging body includes metal salient point structure (2), IC chip (3), bonding welding pad (4), the second adhesive material (5), and the first capsulation material (6), first is wiring metal routing layer (7), the first metal layer (8), the first dielectric materials layer (9), second wiring metal routing layer (10), the second dielectric materials layer (11), the second metal level (12) more again, described IC chip (3) is with bonding welding pad (4), second adhesive material (5) is pasted on the surface of IC chip (3), first capsulation material (6) surrounds metal salient point structure (2) and IC chip (3), the bonding welding pad (4) of IC chip (3) with first again wiring metal routing layer (7) be connected, first again wiring metal routing layer (7) is manufactured with the first metal layer (8), first dielectric materials layer (9) encirclement first wiring metal routing layer (7) again, and be coated in IC chip (3), metal salient point structure (2) and the first capsulation material (6) same side, the second dielectric materials layer (11) is coated with in IC chip (3), metal salient point structure (2) and the first capsulation material (6) another side, second dielectric materials layer (11) surrounds the second wiring metal routing layer (10) again, and second again wiring metal routing layer (10) is manufactured with the first metal layer (12),
Second metal level (12) of two packaging bodies staggered relatively is connected by the first soldered ball (13), and at upper connection second soldered ball (14) of the first metal layer (8) of a packaging body, form a fan-out PoP encapsulation unit;
Second soldered ball (14) is connected with the first metal layer (8) of a fan-out PoP encapsulation unit staggered relatively again, described the first metal layer (8), the first soldered ball (13) and a pair second metal levels (12) connected thereof, the second soldered ball (14) and a pair the first metal layer (8) of connecting thereof of not planting ball portion is surrounded by the second capsulation material (15), forms a wafer level fan-out PoP encapsulating structure.
2. a kind of wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, metal salient point structure (2) is but is not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material.
3. a kind of wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, first again wiring metal routing layer (7) and second again wiring metal routing layer (10) be but be not limited to copper, copper alloy, iron, ferroalloy, nickel, nickel alloy, tungsten metal material.
4. a kind of wafer level fan-out PoP encapsulating structure according to claim 1, it is characterized in that, the upper surface of the active face of IC chip (3), the upper surface of metal salient point structure (2) and the first capsulation material (6) at grade.
5. a manufacture method for wafer level fan-out PoP encapsulating structure, is characterized in that, specifically carries out according to following steps:
Step 1: prepare the first carrier disk (100), is configured on the first carrier disk (100) by the first adhesive material (100a) by metal base disk (1);
Step 2: make metal salient point structure (2) by etching or electro-plating method at the upper surface of metal base disk (1);
Step 3: be configured on metal base disk (1) by the second adhesive material (5) by IC chip (3), IC chip (3) is with bonding welding pad (4);
Step 4: adopt high-temperature heating injection moulding process, by environment-friendly type first capsulation material (6) coated sealing IC chip (3) of low water absorption, low stress and metal salient point structure (2), and expose the active face of IC chip (3) and the upper surface of metal salient point structure (2), carry out baking Post RDBMS technique after plastic packaging;
Step 5: the upper surface of the active face in IC chip (3), metal salient point structure (2) and the upper surface of the first capsulation material (6) apply the first dielectric materials layer (9), on the first dielectric materials layer (9), figure is formed by exposure, developing method, adopt plating or chemical plating method making first wiring metal routing layer (7) again, first again wiring metal routing layer (7) make the first metal layer (8), adopts the first dielectric materials layer (9) to apply parcel first wiring metal routing layer (7) again; The bonding welding pad (4) of IC chip (3) is with first wiring metal routing layer (7) is interconnected again;
Step 6: Second support disk (200) stickup is configured on the first metal layer (8) and the first dielectric materials layer (9) by the 3rd adhesive material (200a);
Step 7: remove the first carrier disk (100) and the first adhesive material (100a) by machinery, etching or exposure method;
Step 8: adopt the lower surface of engraving method to metal base disk (1) to etch, formation second wiring metal routing layer (10) again, making second metal level (12) on second again wiring metal routing layer (10), adopts the second dielectric materials layer (11) to apply parcel second wiring metal routing layer (10) again;
Step 9: carry out planting ball technique on the second metal level (12), and carry out reflow soldering process, obtains the first soldered ball (13) be arranged in array;
Step 10: structure above-mentioned steps 9 being made formation carries out face-to-face stacking reflow soldering process, and the first soldered ball (13) becomes the interconnect architecture of upper and lower structure;
Step 11: remove Second support disk (200) and the 3rd adhesive material (200a) by machinery, etching or exposure method;
Step 12: carry out planting ball and reflow soldering process on the first metal layer (8), obtains the second soldered ball (14) be arranged in array, and forms fan-out PoP encapsulation unit;
Step 13: at least one fan-out PoP encapsulation unit is carried out stacking Reflow Soldering, the second soldered ball (14) becomes the interconnect architecture of upper and lower adjacent fan-out PoP encapsulation unit;
Step 14: adopt high-temperature heating injection moulding process, the second capsulation material (15) is carried out coated sealing, carries out baking Post RDBMS technique after plastic packaging, forms wafer level fan-out PoP encapsulation;
Step 15: cutting forms single wafer level fan-out PoP and encapsulates.
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