CN106449560A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN106449560A CN106449560A CN201610934324.1A CN201610934324A CN106449560A CN 106449560 A CN106449560 A CN 106449560A CN 201610934324 A CN201610934324 A CN 201610934324A CN 106449560 A CN106449560 A CN 106449560A
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- chip
- pattern layer
- metal pattern
- packaging structure
- envelope bed
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 148
- 229910052751 metal Inorganic materials 0.000 claims abstract description 148
- 239000000463 material Substances 0.000 claims description 93
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims 1
- 239000005022 packaging material Substances 0.000 abstract 4
- 238000000034 method Methods 0.000 description 11
- 238000009825 accumulation Methods 0.000 description 5
- 238000003825 pressing Methods 0.000 description 4
- 239000004033 plastic Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000005253 cladding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000001149 thermolysis Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging structure. The chip packaging structure includes a first metal pattern layer, a chip, a second metal pattern layer and a packaging material layer, wherein the chip includes a first side surface with connecting salient points and a second side surface without connecting salient points; the chip is arranged on the first metal pattern layer; the second side surface contacts the first metal pattern layer; the second metal pattern layer is arranged on the chip; at least partial area of the second metal pattern layer contacts the connecting salient points; the packaging material layer is clad with the first metal pattern layer, the chip and the second metal pattern layer; the first metal pattern layer is exposed from one side of the packaging material layer; and the second metal pattern layer is exposed from the other side of the packaging material layer. The chip packaging structure can timely dissipate the heat of the chip so as to maintain the performance of the chip.
Description
Technical field
The present invention relates to chip encapsulation technology field, more particularly to a kind of chip-packaging structure.
Background technology
With the continuous development of integrated circuit technique, electronic product is increasingly to miniaturization, intelligent and high reliability
Direction is developed, and integrated antenna package directly affects integrated circuit, electronic module or even overall performance, in IC wafer
Size progressively reduces, integrated level improve constantly in the case of, electronics industry redeems to integrated antenna package and proposes more and more higher
Requirement.
Current fan-out (fanout) technique, chip is embedded in resin material, and the heat for producing when chip operation is because dissipating
Heat is bad and accumulate, so as to cause chip overheating, performance reduction.
Content of the invention
The present invention provides a kind of chip package process, can solve the problem that the poor heat radiation that prior art is present causes chip performance
The problem of reduction.
For solving above-mentioned technical problem, one aspect of the present invention is：A kind of chip-packaging structure is provided, should
Chip-packaging structure includes the first metal pattern layer, chip, the second metal pattern layer and the envelope bed of material, and wherein, chip includes to be provided with
The first side of connecting salient points and the second side for being not provided with connecting salient points, the chip is arranged on first metal pattern layer
On, and the second side contacted with first metal pattern layer；Second metal pattern layer is arranged on the chip, institute
At least part of region for stating the second metal pattern layer is contacted with the connecting salient points；Bed of material cladding described first is sealed described in the envelope bed of material
Metal pattern layer, the chip and second metal pattern layer, and the side of the envelope bed of material exposes first metal
Patterned layer, the opposite side of the envelope bed of material exposes second metal pattern layer.
Wherein, the chip periphery is provided with limiting component, to limit the position of the chip.
Wherein, the limiting component includes multiple spacing cylinders, and the plurality of spacing cylinder is embedded in inside the envelope bed of material
And a loading space is surrounded, the chip is arranged in the loading space.
Wherein, the limited post body is formed in first metal pattern layer, one end of the spacing cylinder with described
First metal pattern layer is contacted.
Wherein, first metal pattern layer includes mutually disjunct base portion and radiating part, and the base portion is arranged on described
The periphery of radiating part；The limited post body is formed on the base portion；The chip is arranged on the radiating part, and described
Two side faces are contacted with the radiating part.
Wherein, described spacing cylinder is metal cartridge, at least part of region of second metal pattern layer and the limit
Another end in contact of position cylinder.
Wherein, the base portion includes multiple mutually disjunct wiring area, on each described wiring area at least provided with
One spacing cylinder.
Wherein, the radiating part is in netted.
Wherein, the envelope bed of material includes the first envelope bed of material and the second envelope bed of material, first metal pattern layer and the core
Piece is embedded in the first envelope bed of material, and second metal pattern layer is embedded in the second envelope bed of material.
Wherein, the envelope bed of material is resin bed.
The invention has the beneficial effects as follows：Be different from the situation of prior art, the present invention pass through the first metal pattern layer and
Second metal pattern layer is exposed out in the both sides of the envelope bed of material respectively, also, the second side of chip and the first metal pattern layer
Contact, thus, even if chip is embedded in the envelope bed of material, the heat for producing during chip operation can be distributed in time from the first metal pattern layer
Go out, without causing the accumulation of heat, it is to avoid chip overheating and cause performance reduce.
Description of the drawings
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, below will be to making needed for embodiment description
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the top view of chip-packaging structure provided in an embodiment of the present invention；
Fig. 2 is the side view of a-quadrant in Fig. 1；
Fig. 3 is the vertical view of the first metal pattern layer and limiting component in chip-packaging structure provided in an embodiment of the present invention
Figure；
Fig. 4 is the side view in one region of chip-packaging structure that another embodiment of the present invention is provided；
Fig. 5 is the schematic flow sheet of chip package process provided in an embodiment of the present invention；
Fig. 6 is the schematic flow sheet of the chip package process that another embodiment of the present invention is provided；
Fig. 7 is top view during step S21 in Fig. 6；
Fig. 8 is the side view of a-quadrant in Fig. 7；
Fig. 9 is top view during step S22 in Fig. 6；
Figure 10 is the side view of a-quadrant in Fig. 9；
Figure 11 is top view during step S23 in Fig. 6；
Figure 12 is the side view of a-quadrant in Figure 11；
Figure 13 is the top view before the first envelope material prefabricated film pressing of step S24 in Fig. 6；
Figure 14 is the side view of a-quadrant in Figure 13；
Figure 15 is the top view after the first envelope material prefabricated film pressing of step S24 in Fig. 6；
Figure 16 is the side view of a-quadrant in Figure 15；
Figure 17 is the top view that in Fig. 6, step S24 forms after the first envelope bed of material；
Figure 18 is the side view of a-quadrant in Figure 17；
Figure 19 is top view during step S25 in Fig. 6；
Figure 20 is the side view of a-quadrant in Figure 19；
Figure 21 is the top view that in Fig. 6, step S26 presses after the second envelope material prefabricated film；
Figure 22 is the side view of a-quadrant in Figure 21；
Figure 23 is the top view that in Fig. 6, step S26 forms after the second envelope bed of material；
Figure 24 is the side view of a-quadrant in Figure 23.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is all other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Refer to Fig. 1 and Fig. 2, Fig. 1 be chip-packaging structure provided in an embodiment of the present invention top view.Fig. 2 is in Fig. 1
The side view of a-quadrant.
The chip-packaging structure of the present invention at least includes the first metal pattern layer 10, chip 20, the second metal pattern layer 30
And the envelope bed of material 40, wherein, chip 20 is arranged in the first metal pattern layer 10, and is contacted with the first metal pattern layer 10, the
Two metal pattern layer 30 are arranged on chip 20, and the envelope bed of material 40 coats the first metal pattern layer 10, chip 20 and the second metal
Patterned layer 30.
Specifically, chip 20 includes the first side 22 for being provided with connecting salient points 21 and the second side for being not provided with connecting salient points 21
Face 23, chip 20 is arranged in the first metal pattern layer 10, and the second side 23 of chip 20 is connect with the first metal pattern layer 10
Touch, so that the heat that chip 20 is produced can be derived from the first metal pattern layer 10.
Second metal pattern layer 30 is arranged on chip 20, at least part of region of the second metal pattern layer 30 be connected
Salient point 21 is contacted, to be turned on chip 20 with external circuit by the second metal pattern layer 30.
The envelope bed of material 40 coats the first metal pattern layer 10, chip 20 and the second metal pattern layer 30, and seals the one of the bed of material 40
Side exposes the first metal pattern layer 10, and the opposite side for sealing the bed of material 40 exposes the second metal pattern layer 30.The envelope bed of material 40 1
Aspect can play insulating effect, so that chip 20 is more securely fixed in the first metal pattern layer 40, effectively can keep away
Exempt from the situation generation that chip 20 comes off.
Prior art is different from, the present invention passes through the first metal pattern layer 10 and the second metal pattern layer 30 respectively in envelope
The both sides of the bed of material 40 are exposed out, also, the second side 23 of chip 20 is contacted with the first metal pattern layer 10, thus, even if
Chip 20 is embedded in the envelope bed of material 40, and the heat that chip 20 is produced when working can be distributed in time from the first metal pattern layer 10,
Without causing the accumulation of heat, it is to avoid chip 20 overheated and cause performance reduce.
Limiting component is provided with 20 periphery of chip, so that the position of chip 20 is limited, when so as to prevent plastic packaging, envelope is expected solid
Harmomegathus during change causes chip 20 to offset.
Specifically, in the present embodiment, limiting component includes multiple spacing cylinders 50, and multiple spacing cylinders 50 are embedded in envelope
The bed of material 40 is internal and surrounds a loading space 60, and chip 20 is arranged in loading space 60.For example, the chip 20 of the present embodiment
For square, spacing cylinder 50 form fence and surround one square, chip 20 is loaded in the square loading space 60.When
So, in some other embodiment, chip 20 can be other shapes, and the fence that spacing cylinder 50 is formed then is surrounded and chip 20
Approximate shape.
It is to be appreciated that in some other embodiment, limiting component can also be other structures, for example, limiting component
For the L-shaped part being arranged at four angles of chip, or the baffle plate being arranged on 20 four edges of chip etc., as long as chip 20 can be limited
Position, prevent chip 20 offset.
Spacing cylinder 50 is formed in the first metal pattern layer 10, one end of spacing cylinder 50 and the first metal pattern layer 10
Contact, so as to the basis using the first metal pattern layer 10 as spacing cylinder 50, forms frame structure, can increase adhesion, carry
The steadiness of high spacing cylinder 50.
It is the first metal pattern layer and limiting section in chip-packaging structure provided in an embodiment of the present invention to refer to Fig. 3, Fig. 3
The top view of part.First metal pattern layer 10 includes mutually disjunct base portion 11 and radiating part 12, and base portion 11 is arranged on radiating part
12 periphery.Specifically, spacing cylinder 50 is formed on base portion 11, and chip 20 is then arranged on radiating part 12, and second side
23 are contacted with radiating part 12.Wherein, radiating part 12 is in netted, and for example, the radiating part 12 of the present embodiment is a square net, should
The shapes and sizes of square net are close with the shapes and sizes of the second side 23 of chip, and the second side 23 of chip 20 is direct
Contact with the radiating part 12, as radiating part 12 is metal material, thus the heat of chip 20 fully can be derived by radiating part 12.
Spacing cylinder 50 is metal cartridge, and at least part of region of the second metal pattern layer 30 is another with spacing cylinder 50
End in contact.Therefore, the two ends of spacing cylinder 50 connect the first metal pattern layer 10 and the second metal pattern layer 30, the second gold medal respectively
Metal patterns layer 30 is connected with the connecting salient points 21 of chip 20, such that it is able to set up connecting salient points 21 with spacing cylinder 20 and first
Connection between metal level 10.So that the first metal layer 10 also can be as baseline, so that the first side 22 of chip 20 and
Two side faces 23 all can be connected with external circuit.
For example, the second metal pattern layer 30 in the present embodiment includes terminal pad 31 and the cross structure of multiple circles
32, in a part of region of the second metal pattern layer 30, the such as region of the centre of the present embodiment, each terminal pad 31 is corresponded to respectively
One connecting salient points 21, and be connected with the connecting salient points 21, the terminal pad 31 in remaining region is then located at the periphery of zone line, outward
In the terminal pad 31 in week, part terminal pad 31 is had to be connected with the part terminal pad 31 of zone line by cross structure 32.Additionally, even
Connect bridge 32 and zone line can also be arranged on, and connection is set up between different company connecting salient points 21.Terminal pad 31 and company
The shape of bridge 32 and quantity are connect according to actual needs arranging.It is to be appreciated that in further embodiments, the second metal pattern
Layer 30 can also have other patterns.
Mutually it is not attached between base portion in first metal pattern layer 10 and 11 radiating parts 12, so that base portion 11 is used as base
Line and connect with external circuit, play conducting effect, and 12 thermolysis of radiating part.
Base portion 11 includes multiple mutually disjunct wiring area, such as the wiring area 13a in Fig. 3,13b, 13c, 13d,
13e and 13f, at least provided with a spacing cylinder 50 on each wiring area, to set up between the wiring area and chip 20
Connection.For example in Fig. 3, wiring area 13a is provided with 5 spacing cylinders 50, is respectively equipped with 1 on wiring area 13b, 13c, 13d
Individual spacing cylinder 50,13e are provided with 4 spacing cylinders 50, arrange in the quantity of concrete wiring area and each wiring area
The quantity of spacing cylinder 50 arrange according to the actual requirements.
The envelope bed of material 40 includes the first envelope bed of material 41 and the second envelope bed of material 42, the first metal pattern layer 10, chip 20 and spacing
Part is embedded in the first envelope bed of material 41, and the second metal pattern layer 30 is embedded in the second envelope bed of material 42.
Specifically, the first envelope bed of material 41 of the present embodiment coats the first metal pattern layer 10, chip 20 and spacing cylinder 50,
So that the position of chip 20, the first metal pattern layer 10 and spacing cylinder 50 is fixed.
The second envelope bed of material 42 coats the second metal pattern layer 30 so that the second metal pattern layer 30 can be more solidly fixed to
On the first envelope bed of material 41.
Specifically, the envelope bed of material 40 is resin bed, such as epoxy resin, and the sealing property of epoxy resin is preferable, and plastic packaging is easy.
To sum up, in the chip-packaging structure of the present invention, the heat that chip 20 is produced can be in time from the first metal pattern layer 10
Distribute, it is to avoid the accumulation of heat, maintain the performance of chip 20.
As shown in figure 4, Fig. 4 is the side view in one region of chip-packaging structure that another embodiment of the present invention is provided.This
Embodiment is with the difference of above-described embodiment, and the chip-packaging structure of the present embodiment is the chip package of two above-described embodiments
At the stacking of structure, also, the second metal pattern layer 30 position corresponding with spacing cylinder 50 of the chip-packaging structure of bottom,
And entered by soldered ball 70 at the 50 corresponding position of more than 10 spacing cylinder of the first metal pattern layer of the chip-packaging structure of top layer
Row connection, to realize the conducting between two chips.
It is to be appreciated that in some other embodiment, can also be the chip-packaging structure of multiple above-described embodiments
Stacking.
It is the schematic flow sheet of chip package process provided in an embodiment of the present invention please continue to refer to Fig. 5, Fig. 5.
The chip package process of the present embodiment is comprised the following steps：
S11：The first metal pattern layer is formed on support plate.
The forming process of the first metal pattern layer 10 can be：On support plate, a metal level is first formed, then pass through gold-tinted system
Journey, forms default pattern through steps such as overexposure, development, etchings, so as to form the first metal pattern layer 10.
S12：Chip is arranged in the first metal pattern layer, wherein, chip includes the first side for being provided with connecting salient points
With the second side for being not provided with connecting salient points, second side contacted with the first metal pattern layer.
Specifically, the one side of support plate forms alignment mark by laser, and chip 20 is then configured according to alignment mark.This
The whole second side 23 of the chip 20 of embodiment is all contacted with the first metal pattern layer 10, so as to fully radiate.
S13：The first envelope bed of material is set on support plate, so that the first metal pattern layer and chip is coated, and makes the first envelope bed of material
Surface exposure connecting salient points.
Specifically, in the present embodiment, the setting of the first envelope bed of material 41 is comprised the following steps：First the first envelope is pressed on support plate
Material prefabricated film, so that the first envelope material prefabricated film coats the first metal pattern layer 10 and chip 20, then the first envelope material prefabricated film of polishing
Surface, to form the first envelope bed of material 41, and make connecting salient points 21 exposed out.
It is to be appreciated that in some other embodiment, connecting salient points 21 can also be exposed by forming through hole.
S14：The second metal pattern layer is formed on the first envelope bed of material, and makes at least part of region of the second metal pattern layer
Contact with connecting salient points.
The forming process of the second metal pattern layer 30 can be：On support plate, a metal level is first formed, then pass through gold-tinted system
Journey, forms default pattern through steps such as overexposure, development, etchings, so as to form the second metal pattern layer 30.Also, second
The subregion of metal pattern layer 30 is contacted with connecting salient points 21, so as to the connecting salient points 21 set up and the second metal pattern layer 30
Between connection so that external circuit is turned on chip 20 by the second metal pattern layer 30.
S15：The second envelope bed of material, second metal pattern layer of surface exposure of the second envelope bed of material are set on the first envelope bed of material.
In step S15, the setting of the second envelope bed of material 42 is comprised the following steps：First on the first envelope bed of material 41, second envelope is pressed
Material prefabricated film, so that the second envelope material prefabricated film coats the second metal pattern layer 30, then the surface of the second envelope material prefabricated film of polishing, with
Form the second envelope bed of material 42, and make the second metal pattern layer 30 exposed out.
S16：Support plate is removed, so that first metal pattern layer of surface exposure of the first envelope bed of material.
After step S16, the 10 exposed surface in the first envelope bed of material 41 of the first metal pattern layer, and the second side of chip 20
23 are contacted with first metal pattern layer 41, so that the heat that chip 20 is produced can be distributed by the first metal pattern layer 10
Go out, without causing the accumulation of heat, it is to avoid chip 20 overheated and cause performance reduce.
Refer to the schematic flow sheet that Fig. 6, Fig. 6 are the chip package process that another embodiment of the present invention is provided.
S21：The first metal pattern layer is formed on support plate.
As shown in Figure 7 and Figure 8, Fig. 7 is top view during step S21 in Fig. 6.Fig. 8 is the side view of a-quadrant in Fig. 7.This
First metal pattern layer 10 of embodiment is formed on support plate 90, and first metal pattern layer 10 includes base portion 11 and radiating part
12, wherein, base portion 11 is arranged on the periphery of radiating part 12, base portion 11 include multiple mutually disjunct wiring area 11a, 11b,
11c, 11d, 11e and 11f.Radiating part 12 is in netted.
Mutually it is not attached between base portion 11 and radiating part 12, so that base portion 11 is connected with external circuit as baseline,
Play conducting to act on, and 12 thermolysis of radiating part.
S22：Limiting component is formed on support plate, to limit the position of chip.
Refer to Fig. 9 and Figure 10, Fig. 9 are top views during step S22 in Fig. 6.Figure 10 is the side view of a-quadrant in Fig. 9.
Specifically, limiting component includes multiple spacing cylinders 50, and the spacing cylinder 50 is that metal cartridge, multiple spacing cylinders 50 surround one
Individual loading space 60, such as spacing cylinder 5 are centered around the periphery of radiating part 12 and form loading space in the top of radiating part 12
60.The multiple spacing cylinder 50 of the present embodiment is both formed on base portion 11, is made base portion 11 as the basis of spacing cylinder 50, is formed
Frame structure, can increase adhesion, improve the steadiness of spacing cylinder 50.On each wiring area of base portion 11 at least provided with
One spacing cylinder 50.
It is to be appreciated that in some other embodiment, limiting component can also be other structures, for example, limiting component
For the L-shaped part being arranged at 20 4 angles of chip, or the baffle plate being arranged on 20 four edges of chip etc., as long as chip can be limited
20 position, prevents chip 20 from offseting.
S23：Chip is arranged in the first metal pattern layer, wherein, chip includes the first side for being provided with connecting salient points
With the second side for being not provided with connecting salient points, second side contacted with the first metal pattern layer.
As is illustrated by figs. 11 and 12, Figure 11 is the top view of step S23 in Fig. 6, and Figure 12 is the side-looking of a-quadrant in Figure 11
Figure.
Chip 20 includes the first side 22 for being provided with connecting salient points 21 and the second side 23 for being not provided with connecting salient points 21.Will
Chip 20 is arranged in the loading space 60 of the formation of spacing cylinder 50, and when so as to prevent plastic packaging by spacing cylinder 50, envelope material exists
Harmomegathus in solidification process causes chip 20 to offset.Meanwhile, chip 20 is arranged on radiating part 12, is made second side 23 and dissipate
Hot portion 12 contacts.
S24：The first envelope bed of material is set on support plate, so that the first metal pattern layer, chip and limiting component is coated, and makes
The surface exposure connecting salient points of the one envelope bed of material and limiting component.
Step S24 is specifically included：
First the first envelope material prefabricated film 43 is pressed on support plate 90, so that the first envelope material prefabricated film 43 coats the first metal pattern
Layer 10, chip 20 and spacing cylinder 50.As shown in Figure 13, Figure 14, Figure 15 and Figure 16, Figure 13 is first of step S24 in Fig. 6
Top view before envelope material prefabricated film pressing.Figure 14 is the side view of a-quadrant in Figure 13.Figure 15 is the first envelope of step S24 in Fig. 6
Top view after material prefabricated film pressing.Figure 16 is the side view of a-quadrant in Figure 15.
Then, the surface of the first envelope material prefabricated film 43 of polishing, to form the first envelope bed of material 41, and makes connecting salient points 21 and limit
Position cylinder 50 is exposed out.As shown in Figure 17 and Figure 18, Figure 17 is the top view that in Fig. 6, step S24 forms after the first envelope bed of material,
Figure 18 is the side view of a-quadrant in Figure 17.
S25：The second metal pattern layer is formed on the first envelope bed of material, and makes at least part of region of the second metal pattern layer
Contact with connecting salient points, another end in contact of at least part of region and spacing cylinder.
As illustrated in figures 19 and 20, Figure 19 is the top view of step S25 in Fig. 6.Figure 20 is the side-looking of a-quadrant in Figure 19
Figure.In step S25, the second metal pattern layer 30 is formed on the first envelope bed of material 41, for example, the second gold medal in the present embodiment
Metal patterns layer 30 include multiple circle terminal pads 31 and cross structure 32, a part of region of the second metal pattern layer 30, such as
In the region of the centre of the present embodiment, each terminal pad 31 corresponds to connecting salient points 21 respectively, and connects with the connecting salient points 21
Connect, the terminal pad 31 in remaining region is then located at the periphery of zone line, in the terminal pad 31 of periphery, has part terminal pad 31 to pass through
Cross structure 32 is connected with the part terminal pad 31 of zone line.Additionally, cross structure 32 can also be arranged on zone line, and not
Connection is set up between same company connecting salient points 21.The shape and quantity of terminal pad 31 and cross structure 32 is according to actual needs setting
Put.It is to be appreciated that in further embodiments, the second metal pattern layer 30 can also have other patterns.
S26：The second envelope bed of material, second metal pattern layer of surface exposure of the second envelope bed of material are set on the first envelope bed of material.
Step S26 specifically includes following steps：
As shown in figure 21 and figure, Figure 21 is the top view that in Fig. 6, step S26 presses after the second envelope material prefabricated film, Figure 22
It is the side view of a-quadrant in Figure 21.The second envelope material prefabricated film 44 is pressed on the first envelope bed of material 41, so that the second envelope material prefabricated film
44 the second metal pattern layer 30 of cladding.
As shown in figure 23 and figure 24, Figure 23 is the top view that in Fig. 6, step S26 forms after the second envelope bed of material, and Figure 24 is figure
The side view of a-quadrant in 23.Polish the surface of the second envelope material prefabricated film 44, so that the second envelope bed of material 42 is formed, and make the second metal
Patterned layer 30 is exposed out.
S27：Support plate is removed, so that first metal pattern layer of surface exposure of the first envelope bed of material.
In step S27, after support plate is removed, chip-packaging structure as depicted in figs. 1 and 2 is obtained, the encapsulating structure
In, the 10 exposed surface in the first envelope bed of material 41 of the first metal pattern layer, the heat of chip 20 is distributed.
Further, since the first metal pattern layer 10 and the second metal pattern layer 30 are exposed in the both sides table for sealing the bed of material 40 respectively
Face, and as spacing cylinder 50 is that metal cartridge, the two ends of spacing cylinder 50 connect the first metal pattern layer 10 and the respectively
Two metal pattern layer 30, the second metal pattern layer 30 is connected with the connecting salient points 21 of chip 20, such that it is able to set up connecting salient points
Connection between 21 and spacing cylinder 50 and the first metal pattern layer 10.So that the first metal pattern layer 10 also can be used as base
Line, so that the first side 22 of chip 20 and second side 23 all can be connected with external circuit.
In other embodiments of the present invention, in the above-described embodiments, after step S21-S27, also include：To pass through
Two chip-packaging structures that above-mentioned steps S21-S27 are formed are stacked up, and are welded by soldered ball, ultimately form as figure
Chip-packaging structure shown in 4.Specifically, the second metal pattern layer 30 of the chip-packaging structure of bottom and spacing cylinder 50 pairs
At the position that answers, and lead at the 50 corresponding position of more than 10 spacing cylinder of the first metal pattern layer of the chip-packaging structure of top layer
Cross soldered ball 70 to be attached, to realize the conducting between two chips.
It is to be appreciated that in some other embodiment, can also be the chip-packaging structure of multiple above-described embodiments
Stacking.
To sum up shown, the heat that chip can be produced by the present invention in time is distributed, and is prevented accumulation of heat, is maintained chip
Performance.
Embodiments of the present invention are the foregoing is only, the scope of the claims of the present invention is not thereby limited, every using this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (10)
1. a kind of chip-packaging structure, it is characterised in that include：
First metal pattern layer；
Chip, including being provided with the first side of connecting salient points and being not provided with the second side of connecting salient points, the chip is arranged on
In first metal pattern layer, and the second side is contacted with first metal pattern layer；
Second metal pattern layer, is arranged on the chip, at least part of region of second metal pattern layer with described
Connecting salient points are contacted；And
The envelope bed of material, the envelope bed of material coats first metal pattern layer, the chip and second metal pattern layer, and institute
The side for stating the envelope bed of material exposes first metal pattern layer, and the opposite side of the envelope bed of material exposes the second metal figure
Pattern layer.
2. chip-packaging structure according to claim 1, it is characterised in that the chip periphery is provided with limiting component, with
Limit the position of the chip.
3. chip-packaging structure according to claim 2, it is characterised in that the limiting component includes multiple limited posts
Body, the plurality of spacing cylinder is embedded in envelope bed of material inside and surrounds a loading space, and the chip is arranged on the dress
Carry in space.
4. chip-packaging structure according to claim 3, it is characterised in that the limited post body is formed in first gold medal
On metal patterns layer, one end of the spacing cylinder is contacted with first metal pattern layer.
5. chip-packaging structure according to claim 4, it is characterised in that first metal pattern layer includes mutually not phase
Base portion even and radiating part, the base portion is arranged on the periphery of the radiating part；
The limited post body is formed on the base portion；
The chip is arranged on the radiating part, and the second side is contacted with the radiating part.
6. chip-packaging structure according to claim 5, it is characterised in that the spacing cylinder is metal cartridge, described
Another end in contact of at least part of region of the second metal pattern layer and the spacing cylinder.
7. chip-packaging structure according to claim 6, it is characterised in that the base portion includes multiple mutually disjunct cloth
Line region, at least provided with a spacing cylinder on each described wiring area.
8. chip-packaging structure according to claim 7, it is characterised in that the radiating part is in netted.
9. chip-packaging structure according to claim 1, it is characterised in that the envelope bed of material includes the first envelope bed of material and
The two envelope bed of materials, first metal pattern layer and the chip are embedded in the first envelope bed of material, second metal pattern layer
It is embedded in the second envelope bed of material.
10. chip-packaging structure according to claim 1, it is characterised in that the envelope bed of material be.
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| CN201610934324.1A CN106449560A (en) | 2016-10-25 | 2016-10-25 | Chip packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610934324.1A CN106449560A (en) | 2016-10-25 | 2016-10-25 | Chip packaging structure |
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