CN101211792A - Semi-conductor package and its manufacture method and stacking structure - Google Patents
Semi-conductor package and its manufacture method and stacking structure Download PDFInfo
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- CN101211792A CN101211792A CNA200610156691XA CN200610156691A CN101211792A CN 101211792 A CN101211792 A CN 101211792A CN A200610156691X A CNA200610156691X A CN A200610156691XA CN 200610156691 A CN200610156691 A CN 200610156691A CN 101211792 A CN101211792 A CN 101211792A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor encapsulation device, a manufacturing method and a stacking structure. The invention provides a substrate module chip provided with a plurality of substrates so as to arrange and electrically connect a semiconductor chip and a plurality of conductive projections on various substrates. The process of encapsulation and manufacturing is then carried out so as to form an encapsulation body coating the semiconductor and the conductive projection and ensure that the end part of the conductive projection is exposed out from the top surface of the encapsulation body and then is cut along the space between various substrates so as to form a plurlaity of semiconductor encapsulation devices with the the end part of the conductive projection exposed out from the top of the encapsulation bdoy, thereby ensureing that the other semiconductor encapsulation device is stacked and electrically connected to the conductive projection exposed out from the top of the encapsulation body through a conductive element. The invention has the advantages that the invention avoids the problems that the package resin in the stacking structure of the existing semiconductor encapsulation device contamiantes the welding pad, the number of the electrically connected I/Os is small, no sufficient space can be provided for arranging the passive element, the warping easily happens, etc.
Description
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, relate in particular to a kind of semiconductor package part and method for making and stacked structure that supplies a plurality of encapsulating structures to pile up.
Background technology
Electronic product still requires the lifting of performance and processing speed after miniaturization.Promote the preferred approach of performance and processing speed, nothing more than being number of chips or the size that increases in the semiconductor package part, but connect the storing that the area that can use on the substrate of putting often can't supply the chip of a plurality of chip level settings or large-size for chip.So, present development be the stack multiple package module that is conceived to a plurality of packaging part stacked on top (Package on Package, POP).
Consult Fig. 1, United States Patent (USP) the 5th, 222, disclose a kind of POP stacked structure of semiconductor package part for No. 014, it provides a upper surface to be provided with a plurality of ball grid array (BGA) substrates 11 that pile up weld pad (stacked pad) 110, put semiconductor chip 10 and form the packaging body 13 that coats this semiconductor chip 10 on this substrate 11, to connect, to form lower floor's semiconductor package part 101, then a upper strata semiconductor package part 102 of finishing encapsulation is connect piling up on the weld pad 110 of the substrate surface of putting and be electrically connected to this lower floor's semiconductor package part 101 by soldered ball 14, use the POP stacked structure that forms the semiconductor packaging part.
Yet, owing to aforementioned this upper strata semiconductor package part and lower floor's semiconductor package part are that the reflow of mat soldered ball electrically connects, and this ball height H is generally 0.5mm, the height h that so will limit the packaging body of lower floor's semiconductor package part must be less than ball height H, promptly the height h of this packaging body is normally greatly below 0.3mm, yet the height that packaging body is low excessively can have influence in order to electrically connect the bonding wire quality of chip to the bonding wire of substrate, causes the reliability of lower floor's semiconductor package part not good.
In addition, the distance of the nearest weld pad of packaging body of this lower floor's semiconductor package part must be 0.25mm at least, pollutes to weld pad to reduce the resin overflow that forms this packaging body, causes the electrical bad problem of piling up contact.But, so can make the weld pad number diminish for the space that this weld pad is set shrinkage limit, cause the I/O decreased number that electrically connects between upper strata and lower floor's semiconductor package part; In addition, packaging body at different size, shape, promptly must use corresponding different moulds, cause the raising of manufacturing cost and complexity, and the shape of this packaging body also limits and can supply follow-up application of piling up another semiconductor package part in lower floor's semiconductor package part.
Relatively, as keeping supplying the I/O number that electrically connects between layer and lower floor's semiconductor package part for increasing, promptly need increase this weld pad as far as possible, that is the package body sizes of limit lower floor semiconductor package part of must trying one's best, can be but so promptly there is adequate space for passive component being set to improve the packaging part electrical quality.
In addition, consult Fig. 2, packaging body 13 sizes as lower floor's semiconductor package part 101 are too small relatively, to cause these lower floor's semiconductor package part 101 structural strengths not good, and easy recurring structure warpage (warpage) problem, cause follow-up being difficult on this lower floor's semiconductor package part 101, to pile up upper strata semiconductor package part 102, even this upper and lower layer semiconductor package part 102,101 soldered ball 14 rhegma problems of electrical couplings each other are provided when causing piling up upper strata semiconductor package part 102.
So, how to provide a kind of semiconductor package part and method for making thereof can avoid semiconductor package part that lower floor piles up to pile up weld pad quantity and passive component setting because of the setting of its packaging body limits, pollute and pile up weld pad, structure warpage, and at problems such as different packaging body shapes, the size palpus preparation manufacturing expense that different corresponding production mould produced and complexity increase, the real problem of desiring most ardently solution at present that become.
Summary of the invention
The shortcoming of prior art in view of the above, main purpose of the present invention is to provide a kind of semiconductor package part and method for making and stacked structure, limits the weld pad quantity problem of piling up to avoid existing lower floor semiconductor package part because of the setting of packaging body.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof and stacked structure, pollute the weld pad problem of piling up because of the setting of packaging body to avoid existing lower floor semiconductor package part.
Another purpose of the present invention is to provide a kind of semiconductor package part and method for making and stacked structure, with the structure warpage issues of avoiding existing lower floor semiconductor package part to be caused because of package body sizes is too small.
A further object of the present invention is to provide a kind of semiconductor package part and method for making and stacked structure, and passive component can effectively be set, to improve the packaging part electrical quality.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof and stacked structure, only use single mold can finish Chip Packaging, thereby can avoid in the existing lower floor semiconductor package part at problems such as different packaging body shapes, the size palpus preparation manufacturing expense that different corresponding production mould produced and complexity increases.
For reaching above-mentioned and other purpose, the method for making of semiconductor package part of the present invention comprises: the substrate module sheet of a plurality of substrates of a tool is provided, and respectively the surface of this substrate is provided with a chip connecting area and a plurality of weld pad that piles up; Pile up to connect on the weld pad in this substrate and put conductive projection and on this chip connecting area, connect and put and electrically connect semiconductor chip; Carry out package fabrication process, coat the packaging body of this semiconductor chip and conductive projection with formation on the substrate module sheet, and make the end of this conductive projection expose outside this packaging body end face; And, expose the semiconductor package part that the conductive projection end is arranged to form a plurality of packaging body end faces along respectively carrying out cutting operation between this substrate.In addition, on this substrate, also can connect and put and electrically connect a plurality of passive components, to improve the packaging part electrical quality.This substrate can be thin spherical grid array (TFBGA) substrate or planar lattice array (Land Grid Array, LGA) substrate.
This semiconductor package part can be prior to form the packaging body that coats this semiconductor chip and conductive projection comprehensively when carrying out package fabrication process on this substrate module sheet; Then carry out the thinning operation, make this conductive projection end expose outside this packaging body end face to remove the part packaging body.In addition also can be when carrying out package fabrication process in this semiconductor package part, this is connect the die cavity that the substrate module sheet that is equipped with semiconductor chip and conductive projection places an encapsulating mould, wherein the end face of this die cavity is laid with a thin layer in advance, and the film laminating that makes this die cavity end face is butted on this conductive projection end, then in this die cavity, fill potting resin, use forming the packaging body that coats this semiconductor chip and conductive projection; Promptly remove this mould and thin layer afterwards, use directly making this conductive projection end expose outside this packaging body.
By aforementioned method for making, the present invention also discloses a kind of semiconductor package part, comprising: substrate, this substrate surface are provided with a chip connecting area and a plurality of weld pad that piles up; Semiconductor chip connects and places this chip connecting area and be electrically connected to this substrate; Conductive projection connects and places this to pile up on the weld pad; And packaging body, be formed on this substrate and coat this semiconductor chip and conductive projection, and make this conductive projection end expose outside this packaging body end face.In addition, on this substrate, also can connect and put and electrically connect a plurality of passive components, to improve the packaging part electrical quality.
The present invention also discloses a kind of semiconductor package part stacked structure, includes lower floor's semiconductor package part; An and upper strata semiconductor package part, pile up and be electrically connected on this lower floor's semiconductor package part, wherein, this lower floor's semiconductor package part comprises that the surface is provided with a chip connecting area and a plurality of substrate that piles up weld pad, connect the semiconductor chip that places this chip connecting area and be electrically connected to this substrate, connect and place this to pile up the conductive projection of weld pad, and be formed on this substrate to coat the packaging body of this semiconductor chip and conductive projection, this conductive projection end exposes to this packaging body end face, connects by a plurality of conducting elements for this upper strata semiconductor package part and puts and be electrically connected to the conductive projection end that this lower floor's semiconductor package part exposes outside this packaging body end face.
Therefore, semiconductor package part of the present invention and method for making thereof and stacked structure, provide the substrate module sheet of a plurality of substrates of a tool, respectively the surface of this substrate is provided with a chip connecting area and a plurality of weld pad that piles up, put and electrically connect semiconductor chip to pile up in this substrate to connect on the weld pad to put conductive projection and on this chip connecting area, connect, then carry out package fabrication process, on the substrate module sheet, to form the packaging body that coats this semiconductor chip and conductive projection, and the end that makes this conductive projection exposes outside this packaging body end face, afterwards can be along respectively carrying out cutting operation between this substrate, expose the semiconductor package part that the conductive projection end is arranged to form a plurality of packaging body end faces, be able to connect for other semiconductor package part and put and be electrically connected to the conductive projection end that this semiconductor package part exposes outside this packaging body end face by a plurality of conducting elements.
So can avoid in the existing semiconductor package part stacked structure, because of the packaging body of the semiconductor chip that coats in lower floor's semiconductor package part height-limited not good in product reliability that ball height causes, overflow is polluted to weld pad, or can be for the space that weld pad is set for exempting from weld pad pollution shrinkage limit, cause the I/O decreased number problem that electrically connects between the semiconductor package part that is piled up, also or for increasing the I/O number that electrically connects between semiconductor package part, the package body sizes of limit lower floor semiconductor package part, cause no adequate space to reach problems such as warpage takes place easily for passive component is set, simultaneously only need utilize single encapsulating mould can make semiconductor package part of the present invention and stacked structure thereof, to reduce manufacturing expense and complexity.
Description of drawings
Fig. 1 is a United States Patent (USP) the 5th, 222, the stacked structure of a kind of semiconductor package part that is disclosed for No. 014;
Fig. 2 is the schematic diagram of lower floor's semiconductor package part generation warpage in the stacked structure of existing semiconductor package part;
Fig. 3 A to 3E is the generalized section of semiconductor package part of the present invention and method for making first embodiment thereof;
Fig. 4 A to 4C is the generalized section of method for producing semiconductor packaging part second embodiment of the present invention;
Fig. 5 is the generalized section of semiconductor package part the 3rd embodiment of the present invention; And
Fig. 6 is a semiconductor package part stacked structure schematic diagram of the present invention.
The main element symbol description
10 semiconductor chips
11 substrates
110 pile up weld pad
13 packaging bodies
14 soldered balls
101 lower floor's semiconductor package parts
102 upper strata semiconductor package parts
30 semiconductor chips
31 substrates
31A substrate module sheet
311 chip connecting areas
312 pile up weld pad
32 conductive projections
33 packaging bodies
35 passive components
40 semiconductor chips
41 substrates
41A substrate module sheet
42 conductive projections
43 packaging bodies
45 passive components
46 encapsulating moulds
460 die cavitys
47 thin layers
50 semiconductor chips
51 substrates
60 semiconductor chips
61 substrates
62 conductive projections
63 packaging bodies
64 conducting elements
601 lower floor's semiconductor package parts
602 upper strata semiconductor package parts
611 chip connecting areas
612 pile up weld pad
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.
First embodiment
Consult Fig. 3 A to 3E, be the schematic diagram of semiconductor package part of the present invention and method for making first embodiment thereof.
As shown in Figure 3A, provide the substrate module sheet 31A of a plurality of substrates 31 of a tool, respectively the surface of this substrate 31 is provided with a chip connecting area 311 and a plurality of weld pad 312 that piles up.This substrate can be thin spherical grid array (TFBGA) substrate or planar lattice array (LGA) substrate etc.
Shown in Fig. 3 B, connect on the weld pad 312 in piling up of this substrate 31 and to put conductive projection 32, and on this chip connecting area 311, connect and put and electrically connect semiconductor chip 30, wherein this conductive projection 32 for example is a solder bump, and this semiconductor chip 30 can the lead-in wire mode be electrically connected to this substrate 31, also can fully connect in addition to be equipped with as a plurality of passive components 35 such as capacitor, resistor or inductors on this substrate 31.
Shown in Fig. 3 C and 3D, carry out package fabrication process, at first go up and form the packaging body 33 that comprehensively coats this semiconductor chip 30, passive component 35 and conductive projection 32 in this substrate module sheet 31A.
Then by as the thinning operation of grinding, removing packaging body 33 tops,, and then make these conductive projection 32 ends expose outside this packaging body 33 so that these conductive projection 32 ends flush with these packaging body 33 end faces.
Shown in Fig. 3 E, cutting operation is carried out on edge respectively 31 of this substrates, to form thin spherical grid array (TFBGA) or planar lattice array (LGA) semiconductor package part that a plurality of packaging body 33 end faces expose conductive projection 32 ends, wherein this packaging body 33 flushes mutually with substrate 31 sides.
By aforementioned method for making, the present invention also discloses a kind of semiconductor package part, comprising: substrate 31, these substrate 31 surfaces are provided with a chip connecting area 311 and a plurality of weld pad 312 that piles up; Semiconductor chip 30 connects and places this chip connecting area 311 and be electrically connected to this substrate 31; Conductive projection 32 connects and places this to pile up on the weld pad 312; And packaging body 33, be formed on this substrate 31 coating this semiconductor chip 30 and conductive projection 32, and make these conductive projection 32 ends expose outside this packaging body 33 end faces.In addition, on this substrate 31, also can connect and put and electrically connect a plurality of passive components 35, to improve the packaging part electrical quality.
In addition, because semiconductor package part of the present invention forms the TFBGA or the LGA packaging body 33 of a coating semiconductor chip 30 and conductive projection 32 (but exposing outside the conductive projection end) on this substrate 31 comprehensively, its structure equilibrium can prevent effectively that warpage issues from producing, and the weld pad that piles up of also unlikely generation such as prior art is polluted and package body sizes restricted problem by potting resin.
Second embodiment
Consult Fig. 4 A to 4C, be the schematic diagram of method for producing semiconductor packaging part second embodiment of the present invention.
Shown in Fig. 4 A, the method for making of present embodiment is main and previous embodiment is roughly the same, the substrate module sheet 41A of a plurality of substrates 41 of one tool at first is provided, put and electrically connect semiconductor chip 40 on this substrate 41 respectively, to connect, passive component 45 and conductive projection 42, and this is connect be equipped with semiconductor chip 40, the substrate module sheet 41A of passive component 45 and conductive projection 42 places the die cavity 460 of an encapsulating mould 46, wherein the end face of this die cavity 460 is laid with a thin layer 47 in advance, as be polyimides (polyimide) film, and make this thin layer 47 that is laid in die cavity 460 end faces be pressed against this conductive projection 42 ends, then in this die cavity 460, fill potting resin, use to form coating this semiconductor chip 40, the packaging body 43 of passive component 45 and conductive projection 42.
Shown in Fig. 4 B, then remove this mould 46 and thin layer 47, directly expose outside this packaging body 43 for these conductive projection 42 ends.
Shown in Fig. 4 C, cutting operation is carried out on edge respectively 41 of this substrates, to form TFBGA or the LGA semiconductor package part that a plurality of packaging body 43 end faces expose conductive projection 42 ends.
The 3rd embodiment
Consult Fig. 5, be the generalized section of semiconductor package part the 3rd embodiment of the present invention.
As shown in the figure, the semiconductor package part of present embodiment and aforementioned enforcement are roughly the same, and main difference is semiconductor chip 50 except that can being electrically connected to this substrate by aforementioned lead-in wire mode, can also flip chip and be electrically connected to this substrate 51.
Other consults Fig. 6, the generalized section that shows semiconductor package part stacked structure of the present invention, mainly with aforesaid TFBGA or LGA semiconductor package part as the lower floor's semiconductor package part in the stacked structure, put and electrically connect other semiconductor package part to connect thereon, and constitute the semiconductor package part stacked structure.
This semiconductor package part stacked structure includes: a TFBGA of lower floor or LGA semiconductor package part 601; An and upper strata semiconductor package part 602, pile up and be electrically connected on this lower floor's semiconductor package part 601, wherein, this lower floor's semiconductor package part 601 comprises that the surface is provided with a chip connecting area 611 and a plurality of substrate 61 that piles up weld pad 612, connect the semiconductor chip 60 that places this chip connecting area 611 and be electrically connected to this substrate 61, connect and place this conductive projection that piles up weld pad 612 62, and be formed on this substrate 61 to coat the packaging body 63 of this semiconductor chip 60 and conductive projection 62, these conductive projection 62 ends expose outside this packaging body 63 end faces, connect conductive projection 62 ends of putting and being electrically connected to these lower floor's semiconductor package part 601 these packaging body 63 end faces that expose outside for this upper strata semiconductor package part 602 by a plurality of conducting elements 64 as soldered ball.
Therefore, semiconductor package part of the present invention and method for making thereof and stacked structure, provide the substrate module sheet of a plurality of substrates of a tool, respectively the surface of this substrate is provided with a chip connecting area and a plurality of weld pad that piles up, put and electrically connect semiconductor chip to pile up in this substrate to connect on the weld pad to put conductive projection and on this chip connecting area, connect, then carry out package fabrication process, on the substrate module sheet, to form the packaging body that coats this semiconductor chip and conductive projection, and the end that makes this conductive projection exposes outside this packaging body end face, afterwards can be along respectively carrying out cutting operation between this substrate, forming TFBGA or the LGA semiconductor package part that a plurality of packaging body end faces expose the conductive projection end, be able to connect for other semiconductor package part and put and be electrically connected to the conductive projection end that this semiconductor package part exposes outside this packaging body end face by a plurality of conducting elements.
So can avoid in the existing semiconductor package part stacked structure, because of the packaging body of the semiconductor chip that coats in lower floor's semiconductor package part height-limited not good in product reliability that ball height causes, overflow is polluted to weld pad, or can be for the space that weld pad is set for exempting from weld pad pollution shrinkage limit, cause the I/O decreased number problem that electrically connects between the semiconductor package part that is piled up, also or for increasing the I/O number that electrically connects between semiconductor package part, the package body sizes of limit lower floor semiconductor package part, cause no adequate space to reach problems such as warpage takes place easily for passive component is set, simultaneously only need utilize single TFBGA or LGA encapsulating mould can make semiconductor package part of the present invention and stacked structure thereof, to reduce manufacturing expense and complexity.
The above embodiments are only in order to illustration principle of the present invention and effect thereof, but not be used to limit the present invention, therefore any those skilled in the art all can be under spirit of the present invention and scope, and the foregoing description is modified and changed, and decides on implementing kenel.
Claims (15)
1. the method for making of a semiconductor package part comprises:
The substrate module sheet of a plurality of substrates of one tool is provided, and respectively the surface of this substrate is provided with a chip connecting area and a plurality of weld pad that piles up;
Pile up to connect on the weld pad in this substrate and put conductive projection and on this chip connecting area, connect and put and electrically connect semiconductor chip;
Carry out package fabrication process, coat the packaging body of this semiconductor chip and conductive projection with formation on the substrate module sheet, and make the end of this conductive projection expose outside this packaging body end face; And
Along respectively carrying out cutting operation between this substrate, expose the semiconductor package part that the conductive projection end is arranged to form a plurality of packaging body end faces.
2. the method for making of semiconductor package part according to claim 1, wherein, this semiconductor package part is one of them of thin spherical grid array semiconductor package part and planar lattice array semiconductor package part.
3. the method for making of semiconductor package part according to claim 1, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.
4. the method for making of semiconductor package part according to claim 1 wherein, also connects on this substrate and is equipped with a plurality of passive components.
5. the method for making of semiconductor package part according to claim 1, wherein, this package fabrication process comprises:
On this substrate module sheet, form the packaging body that comprehensively coats this semiconductor chip and conductive projection; And
Carry out the thinning operation, make this conductive projection end expose outside this packaging body end face to remove the part packaging body.
6. the method for making of semiconductor package part according to claim 1, wherein, this package fabrication process comprises:
This is connect the die cavity that the substrate module sheet that is equipped with semiconductor chip and conductive projection places an encapsulating mould, and wherein the end face of this die cavity is laid with a thin layer in advance, and makes the film laminating of this die cavity end face be butted on this conductive projection end;
In this die cavity, fill potting resin, use forming the packaging body that coats this semiconductor chip and conductive projection; And
Remove this mould and thin layer, use directly making this conductive projection end expose outside this packaging body.
7. the method for making of semiconductor package part according to claim 6, wherein, this thin layer is the polyimides film.
8. semiconductor package part comprises:
Substrate, this substrate surface are provided with a chip connecting area and a plurality of weld pad that piles up;
Semiconductor chip connects and places this chip connecting area and be electrically connected to this substrate;
Conductive projection connects and places this to pile up on the weld pad; And
Packaging body is formed on this substrate and coats this semiconductor chip and conductive projection, and makes this conductive projection end expose outside this packaging body end face.
9. semiconductor package part according to claim 8, wherein, this semiconductor package part be thin spherical grid array semiconductor package part and planar lattice array semiconductor package part wherein it
10. semiconductor package part according to claim 8, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.
11. semiconductor package part according to claim 8 wherein, also connects on this substrate and is equipped with a plurality of passive components.
12. a semiconductor package part stacked structure comprises:
One lower floor's semiconductor package part; And
One upper strata semiconductor package part, pile up and be electrically connected on this lower floor's semiconductor package part, wherein, this lower floor's semiconductor package part includes the surface and is provided with a chip connecting area and a plurality of substrate that piles up weld pad, connect the semiconductor chip that places this chip connecting area and be electrically connected to this substrate, connect and place this to pile up the conductive projection of weld pad, and be formed on this substrate to coat the packaging body of this semiconductor chip and conductive projection, this conductive projection end exposes outside this packaging body end face, connects by a plurality of conducting elements for this upper strata semiconductor package part and puts and be electrically connected to the conductive projection end that this lower floor's semiconductor package part exposes outside this packaging body end face.
13. semiconductor package part stacked structure according to claim 12, wherein, this lower floor's semiconductor package part is one of them of thin spherical grid array semiconductor package part and planar lattice array semiconductor package part.
14. semiconductor package part stacked structure according to claim 12, wherein, the semiconductor chip of this lower floor's semiconductor package part is electrically connected to this substrate in a wherein mode of lead-in wire and flip-chip.
15. semiconductor package part stacked structure according to claim 12 wherein, also connects on the substrate of this lower floor's semiconductor package part and is equipped with a plurality of passive components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610156691XA CN101211792A (en) | 2006-12-30 | 2006-12-30 | Semi-conductor package and its manufacture method and stacking structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610156691XA CN101211792A (en) | 2006-12-30 | 2006-12-30 | Semi-conductor package and its manufacture method and stacking structure |
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| Publication Number | Publication Date |
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| CN101211792A true CN101211792A (en) | 2008-07-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200610156691XA Pending CN101211792A (en) | 2006-12-30 | 2006-12-30 | Semi-conductor package and its manufacture method and stacking structure |
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| Country | Link |
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| CN (1) | CN101211792A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136459A (en) * | 2010-01-25 | 2011-07-27 | 矽品精密工业股份有限公司 | Packaging structure and manufacture method thereof |
| CN104347557A (en) * | 2013-07-26 | 2015-02-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging member and manufacturing method thereof |
| CN113098234A (en) * | 2020-01-08 | 2021-07-09 | 台达电子企业管理（上海）有限公司 | Power supply system |
| US11320879B2 (en) | 2020-01-08 | 2022-05-03 | Delta Electronics (Shanghai) Co., Ltd | Power supply module and electronic device |
| US11812545B2 (en) | 2020-01-08 | 2023-11-07 | Delta Electronics (Shanghai) Co., Ltd | Power supply system and electronic device |
-
2006
- 2006-12-30 CN CNA200610156691XA patent/CN101211792A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136459A (en) * | 2010-01-25 | 2011-07-27 | 矽品精密工业股份有限公司 | Packaging structure and manufacture method thereof |
| CN104347557A (en) * | 2013-07-26 | 2015-02-11 | 日月光半导体制造股份有限公司 | Semiconductor packaging member and manufacturing method thereof |
| CN113098234A (en) * | 2020-01-08 | 2021-07-09 | 台达电子企业管理（上海）有限公司 | Power supply system |
| US11320879B2 (en) | 2020-01-08 | 2022-05-03 | Delta Electronics (Shanghai) Co., Ltd | Power supply module and electronic device |
| CN113098234B (en) * | 2020-01-08 | 2022-11-01 | 台达电子企业管理（上海）有限公司 | Power supply system |
| US11621254B2 (en) | 2020-01-08 | 2023-04-04 | Delta Electronics (Shanghai) Co., Ltd. | Power supply system |
| US11812545B2 (en) | 2020-01-08 | 2023-11-07 | Delta Electronics (Shanghai) Co., Ltd | Power supply system and electronic device |
| US11876084B2 (en) | 2020-01-08 | 2024-01-16 | Delta Electronics (Shanghai) Co., Ltd. | Power supply system |
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