CN104347557A - Semiconductor packaging member and manufacturing method thereof - Google Patents
Semiconductor packaging member and manufacturing method thereof Download PDFInfo
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- CN104347557A CN104347557A CN201310320107.XA CN201310320107A CN104347557A CN 104347557 A CN104347557 A CN 104347557A CN 201310320107 A CN201310320107 A CN 201310320107A CN 104347557 A CN104347557 A CN 104347557A
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- substrate
- solder projection
- packaging body
- electrically connect
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Provided is a semiconductor packaging member and a manufacturing method thereof. The semiconductor packaging member comprises a first substrate, solder convex blocks, a packaging body, a second substrate, electrical connection elements, electrical contacts and an adhesive layer. The solder convex blocks are formed on the surface of the first substrate. The packaging body wraps the surface of the first substrate and the solder convex blocks and is provided with openings. The solder convex blocks are exposed out of the openings, and internal diameter of the openings is equal to external diameter of the projection of the solder convex blocks to the openings. The second substrate is provided with a first surface and a second surface which are opposite. The electrical connection elements are formed on the first surface of the second substrate and connected with the solder convex blocks in an abutting way. The electrical contacts are formed on the second surface of the second substrate and electrically connected with the solder convex blocks. The adhesive layer is formed between the packaging body and the second substrate and surrounds the solder convex blocks and the electrical connection elements.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method, and relate to especially a kind of there is bonding coat semiconductor package part and manufacture method.
Background technology
Tradition stacking type semiconductor package part comprises multiple substrate, with electrical connection element docking between several substrate.But in docking operation, two substrates are easy to horizontally slip and misplace, cause the electrically connect element misalignment each other of two substrates on the contrary.In addition, in the reflow process after docking, electrically connect element can because fusing and in mobility, and then flow to contiguous electrically connect element and cause because the electrical short (short) that occurs of bridge joint (bridge).Therefore, how solving the deviation problem of docking operation and improve short circuit problem, is that the art industry makes great efforts one of emphasis.
Summary of the invention
The present invention have about a kind of semiconductor package part and manufacture method, two substrates can be avoided in the excessive off normal of docking operation.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a first substrate, a solder projection, a packaging body, a second substrate, an electrically connect element, an electrical contact and a bonding coat.First substrate has a surface.Solder projection is formed on the surface of first substrate.The surface of packaging body coats first substrate and solder projection, and there is an opening, solder projection exposes from opening, and the external diameter that the internal diameter of opening and solder projection are projected to opening is equal.Second substrate has a first surface and a second surface, and second surface is away from first surface, and wherein the surface of the first surface of second substrate and first substrate toward each other.Electrically connect element is formed at the first surface of second substrate and docks with solder projection.Electrical contact is formed at the second surface of second substrate, with solder projection electrically connect.Bonding coat to be formed between packaging body and second substrate and around solder projection and electrically connect element.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.There is provided a first substrate, first substrate has a surface; Form a solder projection in the surface of first substrate; The part that one diaphragm covers solder projection is set; Form another part of a packaging body coats solder projection, wherein packaging body has an opening, and solder projection exposes from opening, and the external diameter that the internal diameter of opening and solder projection are projected to opening is equal; Remove diaphragm; There is provided a second substrate, second substrate has a first surface and a second surface, and second surface, away from first surface, the first surface of second substrate is formed with an electrically connect element, and the second surface of second substrate is formed with an electrical contact; Form an adherend between first substrate and second substrate; Docking first substrate and second substrate, makes this solder projection dock with electrically connect element, and makes adherend under pressure, bind first substrate and packaging body and around solder projection and electrically connect element; And solidification adherend forms a bonding coat.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below:
Accompanying drawing explanation
Figure 1A illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Figure 1B illustrates the vertical view of the solder projection of Figure 1A.
Fig. 2 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the warpage resolution chart of the semiconductor package part according to the embodiment of the present invention.
Fig. 4 A to 4J illustrates the process drawing of the semiconductor package part of Figure 1A.
Fig. 5 A to 5B illustrates the process drawing of the semiconductor package part of Fig. 2.
Main element symbol description:
100,200: semiconductor package part
110: first substrate
110b, 235b: lower surface
110s, 130s, 160s, 170s: lateral surface
110u, 160u: upper surface
120: chip
121: projection
130,230: second substrate
130b: first surface
130u: second surface
140: electrically connect element
150: electrical contact
160: packaging body
160a: opening
165: necking section
170: bonding coat
170 ': adherend
180: solder projection
181: a part
182: another part
190: projection
195: diaphragm
235: protuberance
235r2: accommodating recess
235r1: groove
235a: opening
D1: internal diameter
D2: external diameter
H1: the first projecting height
H2: the second projecting height
H2: spacing
H1, H3: distance
S1, S2: curve
Embodiment
Please refer to Figure 1A, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises first substrate 110, chip 120, second substrate 130, at least one electrically connect element 140, at least one electrical contact 150, packaging body 160, bonding coat 170, at least one solder projection 180 and at least one projection 190.
First substrate 110 is such as single layer substrate or multilager base plate.In this example, substrate 110 is as non-active element, that is, substrate 110 does not comprise any active member (as active chip or active lines), such as a printed circuit board (PCB) (Printed Circuit Board).In another example, substrate 110 can comprise active lines or initiatively chip and become active member.First substrate 110 has upper surface 110u, and chip 120 and solder projection 180 are formed on the upper surface 110u of first substrate 110.
Chip 120 is located between first substrate 110 and second substrate, and is subject to the coated of packaging body 160.In this example, chip 120 is located on first substrate 110 in orientation down with its active surface, and is electrically connected at first substrate 110 by least one projection 121, and this kind of chip is called and covers crystalline substance (flip chip).In another embodiment, chip 120 can be located on first substrate 110 in orientation by its active surface upward, and is electrically connected at first substrate 110 by least one bonding wire.
A part for chip 120 is subject to the coated of packaging body 160, and another part of chip 120 exposes packaging body 160 and is subject to the coated of bonding coat 170; That is, the packed body of chip 120 160 and the coated of bonding coat 170 and be subject to complete protection.In another example, whole chip 120 is imbedded in packaging body 160 and is subject to the coated of packaging body 160.
Second substrate 130 is such as single layer substrate or multilager base plate.In this example, second substrate 130 is as non-active element, that is, second substrate 130 does not comprise any active member (as active chip or active lines), a such as printed circuit board (PCB).In another example, second substrate 130 can comprise active lines or initiatively chip and become active member.Second substrate 130 has relative first surface 130b and second surface 130u, and wherein the upper surface 110u of first surface 130b and first substrate 110 toward each other.
Electrically connect element 140 is formed at the first surface 130b of second substrate 130, and docks with solder projection 180, makes second substrate 130 be electrically connected first substrate 110 by electrically connect element 140 and solder projection 180.Electrically connect element 140 is such as solder or conductive pole (not shown), and wherein the material of solder and solder projection 180 is close, therefore and between solder projection 180 produces excellent associativity.When electrically connect element 140 is conductive poles, conductive pole has good signal transmission character and can reduce the risk of bridge joint between solder.When electrically connect element 140 is solders, in a specific embodiment, electrically connect element 140 tin solder.
Electrical contact 150 is formed on the second surface 130u of second substrate 130, and is electrically connected with solder projection 180 by the conductive layer (not illustrating) in second substrate 130 and/or conductive hole (not illustrating).Electrical contact 150 can be connection pad, projection or conductive pole, and the embodiment of the present invention illustrates for connection pad.Electrical contact 150 is as the defeated in/out contact of semiconductor package part 100, its quantity and/or distribution can be same as electrically connect element 140 by phase XOR, to accept the layout of the chip of different configuration, packaging part or circuit board, make the design of semiconductor package part 100 and this little element more flexible.Such as, if omit second substrate 130, that semiconductor package part 100 can only be electrically connected with solder projection 180 and the element stacked thereon, therefore limits the configuration of semiconductor package part 100 and this element on the contrary.Review the present embodiment, due to the design of electrical contact 140, the configuration elasticity that the defeated in/out contact design flexibility of semiconductor package part 100 and lifting stack the element above second substrate 130 can be promoted
The upper surface 110u of the coated first substrate 110 of packaging body 160, some solder projection 180 and electrically connect element 140.Packaging body 160 have at least one opening 160a(as the enlarged drawing of Figure 1A the dotted line that illustrates), wherein each opening 160a exposes corresponding solder projection 180, so that dock with electrically connect element 140.
Packaging body 160 can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-based resin), silicone (silicone-based resin) or other suitable coverings.Packaging body 160 also can comprise suitable filler, such as, be the silicon dioxide of powdery.Several encapsulation technologies can be utilized to form packaging body 160, such as, be compression forming (compression molding), liquid encapsulation type (liquid encapsulation), injection moulding (injection molding) or metaideophone shaping (transfer molding).
Bonding coat 170 non-conductive adhesive (Non-conductive Paste, NCP) or non-conductive film (Non-conductive Film, NCF).Bonding coat 170 to be formed between packaging body 160 and second substrate 130 and around solder projection 180 and electrically connect element 140.Specifically, bonding coat 170 directly covered section solder projection 180 and electrically connect element 140 bonding coat can protect solder projection 180 and electrically connect element 140, such as, in thermal process, the effect that the thermal stress (thermal stress) produced because of thermal coefficient of expansion (CTE) difference between material can absorb stress because of bonding coat reduces the risk of fracture (crack) between solder projection 180 and electrically connect element 140; In addition, solder projection 180 can soften and pressure between the upper and lower and expanding outward because of solder with the engaging process of the first electric surname contact 140, bonding coat 170 can limit to the expansion of solder projection 180, therefore can reduce between several solder projection 180 because of the short circuit problem that causes of bridge joint phenomenon that expansion produces.
In addition, bonding coat 170 binds the upper surface 160u of the packaging body 160 and first surface 130b of second substrate 130, can reduce the amount of warpage (structure compared to without bonding coat) of semiconductor package part 100.In addition, packaging body 160 has the upper surface 160u away from first substrate 110.The upper surface 160u of bonding coat 170 the bonding packaging body 160 and first surface 130b of second substrate 130, make in the process cutting into single encapsulating structure, Absorbable rod cutting time produce stress and between second substrate 130 and packaging body 160, there is cohesive force, therefore can reduce between first substrate 110 and packaging body 160 risk peeling off (peeling off).
Bonding coat 170, first substrate 110 have lateral surface 170s, 110s and 130s respectively with second substrate 130, wherein the lateral surface 170s of bonding coat 170, the lateral surface 110s of first substrate 110 align with the lateral surface 130s of second substrate 130, haply as flushed.Because bonding coat 170 extends between the lateral surface 110s of the first substrate 110 and lateral surface 130s of second substrate 130 continuously, therefore promote the intensity of semiconductor package part 100, the amount of warpage (structure compared to without bonding coat) of semiconductor package part 100 can be reduced.
Solder projection 180 is formed at the upper surface 110u of first substrate 110, with electrically connect element 140 physical bonds and electrically connect, forms linking part (interconnection part) in.Specifically, solder projection 180 can be tin solder.In addition, a necking section 165 is formed between solder projection 180 and electrically connect element 140, necking section 165 1 inner shrinking structure, the external surface area of electrically connect element 140 and solder projection 180 can be increased, and then increase the contact area of bonding coat 170 and electrically connect element 140 and solder projection 180, and promote the associativity between bonding coat 170 and electrically connect element 140 and solder projection 180.The opening 160a place of the contiguous packaging body 160 in necking section 165.In this example, some solder projection 180 protrudes past opening 160a, makes necking section 165 be positioned at above opening 140a; So.The upper and lower parts of necking section 165 can be subject to the coated and survivable of bonding coat 170.In another example, although figure does not illustrate, right necking section 165 just can be positioned at the opening 160a edge of packaging body 160.
Please refer to Figure 1B, it illustrates the vertical view of the solder projection of Figure 1A.In the present embodiment, the feature that solder projection 180 protrudes past opening 160a is formed by non-demolition formula method, therefore packaging body 160(Figure 1A) opening 160a can not excessive enlargement and be greater than solder projection 180 dimensionally.The feature that solder projection 180 due to the present embodiment protrudes past opening 160a is formed by non-demolition formula method, makes internal diameter D1(Figure 1A of the opening 160a of packaging body 160) to be projected to the outer diameter D 2 of opening 160a equal or close in foozle with solder projection 180.
Please refer to Fig. 2, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises first substrate 110, chip 120, second substrate 230, at least one electrically connect element 140, at least one electrical contact 150, packaging body 160, bonding coat 170, at least one solder projection 180 and at least one projection 190 and protuberance 235.
Protuberance 235 is such as welding resisting layer, and it can be integrated in the technique of second substrate 230.The first surface 130b that protuberance 235 is formed at second substrate 230 has at least one groove 235r1, and electrically connect element 140 is formed in groove 235r1.Protuberance 235, around accommodating recess 235r2, can make chip 120 be placed in accommodating recess 235r2.Protuberance 235 has the lower surface 235b towards packaging body 160, and bonding coat 170 binds the lower surface 235b of the protuberance 235 and upper surface 160u of packaging body 160.
Protuberance 235 is as same barricade, and can stop in the reflow process of electrically connect element 140, the electrically connect element 140 of fusing flow to contiguous electrically connect element 140 and is short-circuited with it.
In this example, necking section 165 is formed between solder projection 180 and electrically connect element 140, necking section 165 1 inner shrinking structure, the external surface area of electrically connect element 140 and solder projection 180 can be increased, and then increase the contact area of bonding coat 170 and electrically connect element 140 and solder projection 180, and promote the associativity between bonding coat 170 and electrically connect element 140 and solder projection 180.The opening 235a(of the groove 235r1 of the contiguous protuberance 235 in necking section 165 is as the dotted line place of the enlarged drawing of Fig. 2).In this example, necking section 165 is positioned at opening 235a; So in another example, although figure does not illustrate, right necking section 165 also just can be positioned on opening 235a or be positioned at outside opening 235a.
Please refer to Fig. 3, it illustrates the warpage resolution chart of the semiconductor package part according to the embodiment of the present invention.Curve S 1 represents known and does not have the amount of warpage of the semiconductor package part of bonding coat 180 and the relation of probe temperature, and curve S 2 represents that the present embodiment has the amount of warpage of semiconductor package part 100 or 200 and the relation of probe temperature of bonding coat 180.As seen from the figure, the amount of warpage of semiconductor package part 100 or 200 obviously reduces.
Please refer to Fig. 4 A to 4J, it illustrates the process drawing of the semiconductor package part of Figure 1A.
As shown in Figure 4 A, provide first substrate 110, wherein first substrate 110 has upper surface 110u.
As shown in Figure 4 A, can adopt is such as that technology (Surface-mount Technology, SMT) is pasted on surface, arranges at least one chip 120 on first substrate 110 upper surface 110u.
As shown in Figure 4 B, can adopt is such as plant playing skill art, forms at least one solder projection 180 on the upper surface 110u of first substrate 110.
As shown in Figure 4 C, diaphragm 195 is set and covers a part 181 for solder projection 180 and a part for chip 120.
As shown in Figure 4 D, can adopt is such as that compression forming, liquid encapsulation type, injection moulding or metaideophone are shaping, form another part 182 of packaging body 160 coated solder projection 180 and another part of chip 120, wherein packaging body 160 has at least one opening 160a, solder projection 180 exposes from opening 160a, and a part 181 for solder projection 180 protrudes past the upper surface 160u of packaging body 160 specifically.
Compared to failure mode (as laser beam perforation) on packaging body several irregular openings exposing solder projection 180 of being formed; because the present embodiment adopts non-demolition mode (completing with diaphragm 195) to form opening 160a, the internal diameter D1 of opening 160a is equaled haply outer diameter D 2 that solder projection 180 is projected to opening 160a.The external diameter difference of each solder projection 180 is little, makes the size difference of each opening 160a little accordingly, and provides contraposition reference more accurately in docking step.So, the contraposition precision of solder projection 180 and electrically connect element 140 can be promoted.In addition, because exempting laser opening and related process thereof, therefore cost can be reduced.
As shown in Figure 4 E, remove diaphragm 195, to expose a part 181 for solder projection 180.
As illustrated in figure 4f, second substrate 130 is provided, second substrate 130 has relative first surface 130b and second surface 130u, second surface 130u is away from first surface 130b, the first surface 130b of second substrate 130 is formed with at least one electrically connect element 140, and the second surface 130u of second substrate 130 is formed with at least one electrical contact 150.In this example, electrically connect element 140 solder.
As shown in Figure 4 G, can adopt is such as coating method, forms adherend 170 ' between first substrate 110 and second substrate 130.In this example, adherend 170 ' is formed on chip 120; In another example, when packaging body 160 covers whole chip 120, adherend 170 ' can be formed on packaging body 160.Adherend 170 ' is positioned at the zone line of several solder projection 180, so in follow-up docking operation, could move and coated solder projection 180 and electrically connect element 140 after adherend 170 ' pressurized toward two effluents.
In this example, adherend 170 ' non-conductive adhesive, it has the thermosetting resin of B-stage (B-stage) characteristic.The adherend 170 ' with B-stage characteristic can be heated to soften, in a liquid also swellable, but can not dissolve completely and melting.In addition, its outward appearance presents semisolid (as such as in jelly colloidal state), and the stability had to a certain degree can not be stained with easily and be bonded to other objects, but not yet reaches completely crued phase (that is being the C stage).In another example, adherend 170 ' can be non-conductive film.When adherend 170 ' is for non-conductive film, although figure does not illustrate, right adherend 170 ' can be located on second substrate 130 and to have at least one perforation; In follow-up docking step, electrically connect element 140 docks with solder projection 180 via perforation.
In addition, solder projection 180 protrudes past opening 160a mono-first projecting height h1, and the lower surface 130b mono-second projecting height h2 of second substrate 130 given prominence to by electrically connect element 140, wherein the upper surface 170u of adherend 170 ' and opening 160a(or say it is the upper surface 160u of packaging body 160) distance H1 be greater than the conjunction of the first projecting height h1 and the second projecting height h2.So, in docking operation, the first surface 130b of second substrate 130 first can touch adherend 170 ', makes adherend 170 ' receive pressure and move toward two effluents, and then is covered with between first substrate 110 and second substrate 130.
As shown at figure 4h, docking first substrate 110 and second substrate 130, solder projection 180 is docked with electrically connect element 140, and makes adherend 170 ' under pressure, bind second substrate 130 and packaging body 160 and around solder projection 180 and electrically connect element 140.Because adherend 170 ' has stickiness, therefore in docking operation, the stickiness that first substrate 110 and second substrate 130 are subject to adherend 170 ' limits, make first substrate 110 and second substrate 130 can not excessive off normal, so, the contraposition precision of electrically connect element 140 and solder projection 180 can be promoted.
After docking, the spacing H2 of the upper surface 110u of first substrate 110 and the first surface 130b of second substrate 130 is greater than the distance H3 of the upper surface 110u of first substrate 110 and the upper surface 120u of chip 120.This one, in docking operation, the first surface 130b of the unlikely interference second substrate 130 of upper surface 120u of chip 120, makes adherend 170 ' can successfully flow between the upper surface 120u of the chip 120 and first surface 130b of second substrate 130.
In addition, the part 181 due to solder projection 180 is exposed and is protruded from the upper surface 160u of packaging body 160, makes electrically connect element 140 be convenient to dock with solder projection 180.
In solder projection 180 reflow process with electrically connect element 140, first substrate 110 or second substrate 130 can first be preheated to the first temperature, and this first temperature is lower than the fusing point of solder projection 180 and electrically connect element 140; After first substrate 110 docks with second substrate 130, heat first substrate 110 or second substrate 130 to the second temperature again, the fusing point higher than solder projection 180 and electrically connect element 140 of this second temperature, with melting solder projection 180 and electrically connect element 140.Owing to being first preheated to the first temperature before docking, therefore the heating after docking can comparatively relax, and then can reduce the injury to semiconductor element.When solder projection 180 and electrically connect element 140 tin solder, the first temperature is such as 150 degree Celsius, and the second temperature is such as 300 degree Celsius.
Then, continuous heating adherend 170 ', allows the complete slaking of adherend 170 ' solidify to the C stage, to form bonding coat 170.In one embodiment, can 165 degree of continuous heating adherends 170 ' about Celsius about 30 minutes.The C stage is the terminal stage of thermosetting resin reaction, and the material in this stage can not melting and dissolving, and its outward appearance presents solid-state.
As shown in fig. 41, at least one projection 190 is formed in the lower surface 110b of first substrate 110; Then, reflow projection 190.Because bonding coat 170 just has cured before the reflow step of projection 190, therefore in the reflow step of projection 190, bonding coat 170 can not soften and can stop the flowing of the electrically connect element 140 of adjacent two fusings, and then adjacent two electrically connect elements 140 can be avoided because the electrical short of flowing.Specifically, if without the design of bonding coat 170, electrically connect element 140 still can melt and flows to contiguous electrically connect element 120 and cause short circuit in the reflow step of projection 190.
As shown in fig. 4j, to be such as cutter or laser, at least all cut P through second substrate 130, bonding coat 170, packaging body 160 and first substrate 110, to be formed at least just like the semiconductor package part 100 shown in Figure 1A in formation.The stress produced in cutting process can make the risk occurring between second substrate 130 and packaging body 160 to peel off.So due to generation when bonding coat 170 Absorbable rod cut stress and between second substrate 130 and packaging body 160, produce cohesive force, therefore the stripping between second substrate 130 and packaging body 160 can be reduced.After cutting, second substrate 130, bonding coat 170, packaging body 160 form lateral surface 130s, 170s, 160s and 110s respectively with first substrate 110, and wherein lateral surface 130s, 170s, 160s and 110s align haply, as flushed.
Please refer to Fig. 5 A to 5B, it illustrates the process drawing of the semiconductor package part of Fig. 2.
As shown in Figure 5A, provide second substrate 230, wherein second substrate 230 is formed with protuberance 235, it is such as welding resisting layer.Protuberance 235 is such as formed by exposure imaging technology, and it can be integrated in the technique of second substrate 230.
The first surface 130b that protuberance 235 is formed at second substrate 230 has at least one groove 235r1.At least one electrically connect element 140 is formed in corresponding groove 235r1.The end of electrically connect element 140 is positioned at groove 235r1, and that is, electrically connect element 140 does not protrude past the opening of groove 235r1.In addition, protuberance 235, around accommodating recess 235r2, can make the chip 120 in subsequent step be placed in accommodating recess 235r2.
As shown in Figure 5 B, docking first substrate 110 and second substrate 230, solder projection 180 is docked with electrically connect element 140 via the opening 235a of groove 235r1, and makes adherend 170 ' under pressure, bind first substrate 110 and packaging body 160 and around solder projection 180 and electrically connect element 140.Because adherend 170 ' has stickiness, therefore in docking operation, the stickiness that first substrate 110 and second substrate 230 are subject to adherend 170 ' limits, make first substrate 110 and second substrate 130 can not excessive off normal, so, the contraposition precision of electrically connect element 140 and solder projection 180 can be promoted.
In addition, protuberance 235 has towards the lower surface 235b of the upper surface 160u of packaging body 160.After docking, bonding coat 170 binds the lower surface 235b of the protuberance 235 and upper surface 160u of packaging body 160.After docking, protuberance 235, as barricade, produces barrier effect to the electrically connect element 140 melted in reflow process, and it therefore can be avoided to flow to contiguous electrically connect element 140 and be short-circuited with it.In addition, after docking, bonding coat 170 is formed between the upper surface 160u of lower surface 235b and packaging body 160, produces barrier effect to the electrically connect element 140 melted in reflow process, and it therefore can be avoided to flow to contiguous electrically connect element 140 and be short-circuited with it.
All the other steps of the manufacture process of semiconductor package part 200, similar in appearance to the corresponding step of the manufacture process of semiconductor package part 100, are held this and are repeated no more.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (23)
1. a semiconductor package part, is characterized in that, comprising:
One first substrate, comprises a surface;
One solder projection, be formed at this first substrate this on the surface;
One packaging body, this surface of this first substrate coated and this solder projection, and there is an opening, this solder projection exposes from this opening, and the internal diameter of this opening is equal with the external diameter that this solder projection is projected to this opening;
One second substrate, has a first surface and a second surface, and this second surface is away from this first surface, and wherein this surface of this first surface of this second substrate and this first substrate toward each other;
One electrically connect element, is formed at this first surface of this second substrate and docks with this solder projection;
One electrical contact, is formed at this second surface of this second substrate, with this solder projection electrically connect; And
One bonding coat, to be formed between this packaging body and this second substrate and around this solder projection and this electrically connect element.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this electrically connect element is solder.
3. semiconductor package part as claimed in claim 1, it is characterized in that, this solder projection protrudes past this opening.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this solder projection and this electrically connect element form a necking section, wherein this opening part of this necking section this packaging body contiguous.
5. semiconductor package part as claimed in claim 1, is characterized in that, this bonding coat is this electrically connect element coated and this solder projection of part directly.
6. semiconductor package part as claimed in claim 1, it is characterized in that, this bonding coat is non-conductive adhesive or non-conductive film.
7. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One chip, is located between this first substrate and this second substrate, and is subject to the coated of this packaging body.
8. semiconductor package part as claimed in claim 7, it is characterized in that, a part for this this chip of packaging body coats, and another part of this chip exposes this packaging body and is subject to the coated of this bonding coat.
9. semiconductor package part as claimed in claim 1, is characterized in that, more comprise:
One protuberance, is formed on this first surface of this second substrate, and has a groove, and this electrically connect element is formed in this groove.
10. semiconductor package part as claimed in claim 9, it is characterized in that, this protuberance is welding resisting layer.
11. semiconductor package parts as claimed in claim 9, is characterized in that, more comprise:
One chip, is located between this first substrate and this second substrate, and is subject to the coated of this packaging body;
Wherein this protuberance is around an accommodating recess, and this receive chips is in this accommodating recess.
12. semiconductor package parts as claimed in claim 9, it is characterized in that, this protuberance has a lower surface towards this packaging body, and this bonding coat binds this lower surface and this packaging body.
The manufacture method of 13. 1 kinds of semiconductor package parts, is characterized in that, comprising:
There is provided a first substrate, this first substrate has a surface;
Form a solder projection in this surface of this first substrate;
The part that one diaphragm covers this solder projection is set;
Form another part of this solder projection of packaging body coats, wherein this packaging body has an opening, and this solder projection exposes from this opening, and the internal diameter of this opening is equal with the external diameter that this solder projection is projected to this opening;
Remove this diaphragm;
One second substrate is provided, this second substrate has a first surface and a second surface, this second surface, away from this first surface, this first surface of this second substrate is formed with an electrically connect element, and this second surface of this second substrate is formed with an electrical contact;
Form an adherend between this first substrate and this second substrate;
Dock this first substrate and this second substrate, this solder projection is docked with this electrically connect element, and make this adherend under pressure, bind this first substrate and this packaging body and around this solder projection and this electrically connect element; And
Solidify this adherend and form a bonding coat.
14. manufacture methods as claimed in claim 13, it is characterized in that, this electrically connect element is solder.
15. manufacture methods as claimed in claim 13; it is characterized in that; cover in the step of this part of this solder projection in arranging this bag cuticula; this part of this solder projection is absorbed in this diaphragm; make after the step forming this this solder projection of packaging body coats, this part of this solder projection protrudes past this opening.
16. manufacture methods as claimed in claim 15, is characterized in that, in the step forming this this solder projection of packaging body coats, this part of this solder projection protrudes past this opening one first projecting height; In the step providing this second substrate, this first surface one second projecting height of this second substrate given prominence to by this electrically connect element; In being formed in the step of this adherend between this first substrate and this second substrate, a surface of this adherend is towards this second substrate, and the spacing of this surface of this adherend and this opening is greater than the conjunction of this first projecting height and this second projecting height.
17. manufacture methods as claimed in claim 14, is characterized in that, in the step of docking this first substrate and this second substrate, this adherend is this electrical contact coated and this solder projection of part directly.
18. manufacture methods as claimed in claim 14, it is characterized in that, this bonding coat is non-conductive adhesive.
19. manufacture methods as claimed in claim 14, is characterized in that, in being formed in the step of this bonding coat between this first substrate and this second substrate, this adherend is in colloidal state.
20. manufacture methods as claimed in claim 14, is characterized in that, more comprise:
Arrange a chip in this first substrate this on the surface;
In the step of this another part forming this this solder projection of packaging body coats, this packaging body this chip more coated.
21. manufacture methods as claimed in claim 14, is characterized in that, before the step of this adherend of solidification, this manufacture method more comprises:
This first substrate to one of preheating first temperature, this first temperature is lower than the fusing point of this solder projection;
Step in this first substrate of docking and this second substrate more comprises:
Heat this second substrate to one second temperature, wherein this second temperature is higher than this first temperature and higher than the fusing point of this solder projection.
22. manufacture methods as claimed in claim 14, it is characterized in that, in the step providing this second substrate, this second substrate is more formed with a protuberance, this protuberance has a groove, and this electrical contact is formed in this groove.
23. manufacture methods as claimed in claim 22, is characterized in that, this protuberance exposure imaging mode is formed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201310320107.XA CN104347557A (en) | 2013-07-26 | 2013-07-26 | Semiconductor packaging member and manufacturing method thereof |
| CN201810303736.4A CN108321142B (en) | 2013-07-26 | 2013-07-26 | Semiconductor package and method of manufacturing the same |
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| CN201310320107.XA CN104347557A (en) | 2013-07-26 | 2013-07-26 | Semiconductor packaging member and manufacturing method thereof |
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| CN201810303736.4A Active CN108321142B (en) | 2013-07-26 | 2013-07-26 | Semiconductor package and method of manufacturing the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN108321142B (en) | 2020-08-28 |
| CN108321142A (en) | 2018-07-24 |
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