JP2015026638A - Semiconductor chip, semiconductor chip bonding method and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip bonding method which can favorably and electrically connect bump electrodes with each other.SOLUTION: A semiconductor chip bonding method comprises: a step of preparing a first semiconductor chip 70 having a first bump electrode 76 and a second semiconductor chip 10 having a second bump electrode 24; and a step of bonding the first bump electrode 76 and the second bump electrode 24. The first bump electrode 70 has a convex top face 76a. The second bump electrode 24 has a concave top face 24a. A conductive bonding material 26 having a convex surface 26a is provided on the top face 24a of the second bump electrode 24. A non-conductive material 38 covers the second bump electrode 24 and the conductive bonding material 26. The first bump electrode 76 and the second bump electrode 24 are bonded with each other via the conductive bonding material 26 by impressing the first semiconductor chip 70 and the second semiconductor chip 10 with each other while softening or melting the non-conductive material 38.

Description

  The present invention relates to a semiconductor chip bonding method in which a bump electrode of a semiconductor chip and a bump electrode of another semiconductor chip are bonded to each other, a method of manufacturing a semiconductor device using the bonding method, and the like.

  2. Description of the Related Art In recent years, with the downsizing and higher functionality of electronic devices, chip-on-chip (CoC) type semiconductor devices in which a plurality of semiconductor chips are stacked on each other have been developed.

  Patent Document 1 discloses a method for manufacturing a CoC type semiconductor device including mounting a second semiconductor chip on a first semiconductor chip. The first semiconductor chip has a substrate, first and second bump electrodes, and a through electrode. The first bump electrode is provided on the surface of the substrate. The second bump electrode is provided on the back surface of the substrate. The through electrode penetrates the substrate and electrically connects the first bump electrode and the second bump electrode. An insulating resin layer is formed on one surface of the first semiconductor chip on which the second bump electrode is provided.

  The second semiconductor chip has a third bump electrode. The second semiconductor chip is held on the stage with the third bump electrode facing upward. Next, the third bump electrode of the second semiconductor chip is opposed to the second bump electrode of the first semiconductor chip. Next, the insulating resin layer provided on the first semiconductor chip is brought into contact with the third bump electrode of the second semiconductor chip. Thereafter, the first semiconductor chip is pressed toward the second semiconductor chip, whereby the second bump electrode of the first semiconductor chip and the third bump electrode of the second semiconductor chip are thermocompression bonded. At this time, the insulating resin layer is filled between the first semiconductor chip and the second semiconductor chip.

  Patent Document 2 discloses another method for manufacturing a CoC type semiconductor device including mounting a second semiconductor chip on a first semiconductor chip. The first and second semiconductor chips have a substrate, first and second bump electrodes, and a through electrode. The first bump electrode is provided on the surface of the substrate. The top surface of the first bump electrode is a convex surface. The second bump electrode is provided on the back surface of the substrate. The top surface of the second bump electrode is a concave surface. When the second semiconductor chip is flip-chip connected to the first semiconductor chip, the first bump electrode of the first semiconductor chip is joined to the second bump electrode of the second semiconductor chip. As a result, side-slip between the bump electrodes during flip-chip connection is prevented.

  Patent Document 2 also discloses that after forming a chip stack in which a plurality of semiconductor chips are stacked on each other, an underfill material is filled in a gap between adjacent semiconductor chips.

JP 2013-016577 A JP 2012-248732 A

  In the method described in Patent Document 1, when the first semiconductor chip is pressed toward the second semiconductor chip, the positions of the bump electrodes may be shifted. Thereby, there is a case where the bump electrodes cannot be bonded satisfactorily.

  In the method described in Patent Document 2, after the chip stack is formed, a step of filling an underfill material in the gap between the semiconductor chips is performed. For this reason, the number of manufacturing steps of the semiconductor device increases.

  Therefore, an improved method for joining semiconductor chips is desired.

  The inventor of the present application newly considered a semiconductor chip bonding method as follows. First, a first semiconductor chip and a second semiconductor chip are prepared. The first semiconductor chip has a first bump electrode having a convex top surface. A nonconductive material is formed on one surface of the first semiconductor chip on which the first bump electrode is provided. The second semiconductor chip has a second bump electrode having a concave top surface.

  Next, the first bump electrode of the first semiconductor chip and the second bump electrode of the second semiconductor chip are joined while softening or melting the nonconductive material provided on the first semiconductor chip. .

  However, the inventor of the present application has found that in this bonding method, a part of the nonconductive material may remain on the concave top surface of the second bump electrode. If a non-conductive material exists between the first bump electrode and the second bump electrode, good electrical connection between the bump electrodes is hindered, and the reliability of the semiconductor device is reduced.

  According to one embodiment, a semiconductor chip bonding method includes preparing a first semiconductor chip having a first bump electrode and a second semiconductor chip having a second bump electrode, and a first bump. Bonding the electrode and the second bump electrode.

  The first bump electrode of the first semiconductor chip has a convex top surface. The second bump electrode of the second semiconductor chip has a concave top surface. A conductive bonding material having a convex surface is provided on the top surface of the second bump electrode. In addition, a non-conductive material that covers the first bump electrode or covers the second bump electrode and the bonding material is provided in the first semiconductor chip or the second semiconductor chip.

  By pressing or pressing the first semiconductor chip and the second semiconductor chip while softening or melting the non-conductive material, the first bump electrode and the second bump electrode are bonded via the conductive bonding material. Is done.

  When the first semiconductor chip and the second semiconductor chip are pressed against each other, the conductive bonding material having a convex surface is softened from the region between the first bump electrode and the second bump electrode. Or extrude molten non-conductive material. For this reason, the non-conductive material hardly remains in the region between the first bump electrode and the second bump electrode. As a result, the first bump electrode and the second bump electrode can be electrically connected satisfactorily.

  A method for manufacturing a semiconductor device according to an embodiment relates to a method for manufacturing a semiconductor device including a chip stacked body in which a plurality of semiconductor chips are stacked together. This manufacturing method includes bonding semiconductor chips adjacent to each other by the semiconductor chip bonding method described above.

  In one embodiment, the semiconductor chip includes a bump electrode having a concave top surface and a conductive bonding material provided on the top surface of the bump electrode and having a convex surface. This semiconductor chip can be used to realize the above bonding method.

  The terms “first” and “second” are simply added to distinguish a plurality of semiconductor chips or a plurality of bump electrodes from each other. Therefore, the “first semiconductor chip” and the “second semiconductor chip” described in the summary of the invention and in the claims are respectively referred to as “first semiconductor chip” described in the column of the embodiment for carrying out the invention. "Semiconductor chip" and "second semiconductor chip" are not necessarily shown, and may correspond to any one of a plurality of semiconductor chips described in the column of the embodiment for carrying out the invention. Note that the first and second bump electrodes should be interpreted similarly.

  According to the bonding method, the bump electrodes can be electrically connected to each other satisfactorily.

(A) is a top view of the semiconductor chip in 1st Embodiment, (b) is sectional drawing of the semiconductor chip along the 1B-1B line. FIG. 2 is an enlarged view of a region 2A shown in FIG. 1B of the semiconductor chip. (A)-(f) is process drawing which shows the formation method of the semiconductor chip of 1st Embodiment in steps. (A)-(f) is process drawing which shows the method of forming a penetration electrode and a 2nd bump electrode in a board | substrate in steps. (A)-(d) is process drawing which shows the formation method of the chip laminated body formed by a several semiconductor chip mutually laminated | stacked in steps. (A)-(c) is process drawing which shows the joining method of the semiconductor chip which concerns on 1st Embodiment which mutually bonds the bump electrodes of two semiconductor chips. (A) is a top view of a chip laminated body, (b) is sectional drawing of a chip laminated body. (A)-(e) is process drawing which shows the method of manufacturing a semiconductor device using a chip | tip laminated body in steps. It is sectional drawing of the semiconductor device containing a chip laminated body. It is sectional drawing which shows the 1st modification of a semiconductor chip. It is sectional drawing which shows the 2nd modification of a semiconductor chip. (A)-(c) is process drawing which shows the joining method of the semiconductor chip which concerns on 2nd Embodiment which joins the bump electrodes of two semiconductor chips mutually.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A is a schematic plan view of the semiconductor chip in the first embodiment. FIG. 1B shows a schematic cross section of the semiconductor chip along the line 1B-1B in FIG. FIG. 2 is an enlarged view showing a detailed configuration of the region 2A shown in FIG.

  The semiconductor chip 10 includes a substrate 12, first and second bump electrodes 20 and 24, and a circuit layer 14 formed on one surface of the substrate 12. The substrate 12 may be a semiconductor substrate, and is preferably a silicon substrate. The circuit layer 14 has a predetermined circuit corresponding to the function of the semiconductor chip 10. For example, the semiconductor chip 10 may be a memory chip having a memory circuit as the circuit layer 14. As the memory circuit, for example, a circuit for DRAM (Dynamic Random Access Memory) can be used.

  An electrode pad 16 electrically connected to the circuit of the circuit layer 14 is formed on one surface of the substrate 12. The circuit layer 14 is covered with an insulating film (passivation film) 18. The insulating film 18 can be formed using, for example, a polyimide resin. The insulating film 18 protects the circuit layer 14. The insulating film 18 is provided with an opening. The electrode pad 16 is exposed from the opening of the insulating film 18.

  The first bump electrode 20 is provided on the electrode pad 16 exposed from the insulating film 18. The first bump electrode 20 has a convex top surface 20a.

  More specifically, the first bump electrode 20 has a pillar portion 21 made of a conductor. The pillar portion 21 is made of, for example, copper. The pillar portion 21 protrudes from the substrate 12. The pillar portion 21 has a convex top surface. The top surface of the pillar portion 21 may have, for example, a shape in which the central portion protrudes in an arc shape.

  Conductive protective films 22 and 23 may be formed on the top surface of the pillar portion 21. In this embodiment, an Ni plating layer 22 that prevents diffusion of elements constituting the pillar portion 21 and an Au plating layer 23 for preventing oxidation are formed on the pillar portion 21.

  The second bump electrode 24 is formed on one surface of the substrate 12 opposite to the one surface on which the first bump electrode 20 is formed. The semiconductor chip 10 further includes a through electrode 30 that penetrates the substrate 12. The through electrode 30 may be made of copper, for example. The through electrode 30 is electrically connected to the second bump electrode 24 and the electrode pad 16. Thereby, the second bump electrode 24 is electrically connected to the corresponding first bump electrode 20.

  The second bump electrode 24 has a concave top surface 24a. Specifically, the second bump electrode 24 has a pillar portion 25 made of a conductor. The pillar portion 25 is made of, for example, copper. The pillar portion 25 may be formed integrally with the through electrode 40. The pillar portion 25 protrudes from the substrate 12. The pillar portion 25 has a concave top surface, and this top surface constitutes the top surface 24 a of the second bump electrode 24. The top surface of the pillar portion 25 may have, for example, a shape in which a central portion is recessed in an arc shape.

  A conductive bonding material 26 is formed on the top surface 24 a of the second bump electrode 24. The surface 26a of the conductive bonding material 26 is a convex curved surface, for example, a substantially spherical surface. The conductive bonding material 26 is preferably solder made of, for example, Sn / Ag.

  The semiconductor chip 10 further includes a non-conductive material 38 that covers the second bump electrode 24 and the bonding material 26. The non-conductive material 38 may cover one surface of the substrate 12, that is, the entire surface on which the second bump electrode 24 is formed. The non-conductive material 38 may be a non-conductive film (NCF). NCF is preferably a thermosetting resin, but may be a thermoplastic resin. Examples of such thermosetting resins include epoxy curable resin compositions and acrylic curable resin compositions.

  The softening temperature or melting temperature of the non-conductive material 38 is preferably lower than the softening temperature or melting temperature of the conductive bonding material 26. Here, when the non-conductive material 38 is a thermosetting resin, the softening temperature or melting temperature means the softening temperature or melting temperature of the uncured thermosetting resin.

  The semiconductor chip 10 may have a cylindrical insulator 36 that penetrates the substrate 12. The cylindrical insulator 36 surrounds the through electrode 30.

  The semiconductor chip 10 may further include reinforcing bumps 60 and 62. The first reinforcing bump 60 has substantially the same configuration as the first bump electrode 20. The second reinforcing bump 62 has substantially the same configuration as the second bump electrode 24. The first reinforcing bump 60 and the second reinforcing bump 62 can be formed of the same material as the first bump electrode 20 and the second bump electrode 24, respectively.

  The first reinforcing bump 60 and the second reinforcing bump 62 are connected by a penetrating member 64 that penetrates the substrate 12. The penetrating member 64 can be formed from the same member as the penetrating electrode 30.

  The first reinforcing bump 60 may have a convex top surface. The second reinforcing bump 62 may have a concave top surface. A conductive bonding material 66 may be provided on the top surface of the second reinforcing bump 62. The conductive bonding material 66 may be the same as the conductive bonding material 26 provided on the second bump electrode 24.

  The first reinforcing bump 60 and the second reinforcing bump 62 do not function as electrodes, and are used to reinforce the bonding between the semiconductor chip 10 and another semiconductor chip. Therefore, the first reinforcing bump 60 and the second reinforcing bump 62 do not have to be electrically connected to the circuit layer 14.

  3A to 3F show a method for forming the semiconductor chip 10 described above. First, as shown in FIG. 3A, a semiconductor wafer 40 including a plurality of chip formation regions 42 that are regions to be semiconductor chips 10 is prepared. The semiconductor wafer 40 includes a substrate 12 made of single crystal silicon, for example. The semiconductor wafer 40 is partitioned into chip formation regions 42 by dicing lines 44.

  Next, the circuit layer 14 and the electrode pad 16 are formed on one surface of each chip formation region 42 of the semiconductor wafer 40. Next, an insulating film 18 having an opening exposing the electrode pad 16 is formed on the surface of the circuit layer 14.

  Next, a first bump electrode 20 is formed on the electrode pad 16 exposed from the insulating film 18. At this time, the first bump electrode 20 is formed so as to protrude from the surface of the insulating film 18. As an example, the first bump electrode 20 can be formed by depositing a Ni layer and an Au layer on the top surface of the pillar portion 21 made of copper by a plating method. The top surface of the first bump electrode 20 can be made convex by adjusting the metal deposition time by plating.

  Next, a support substrate 48 is bonded to the surface of the semiconductor wafer 40 on which the first bump electrode 20 is formed via an adhesive member 46 (see FIG. 3B). As a material of the adhesive member 46, it is preferable to use a material whose firing power or adhesive strength is reduced by reacting with specific light, for example, laser light or UV light. As the support substrate 48, it is preferable to use a light-transmitting substrate such as a glass substrate. Further, the adhesive member 46 preferably has a thickness that allows the first bump electrode 20 to be completely embedded.

  Next, the semiconductor wafer 40 is thinned (see FIG. 3B). More specifically, one surface of the semiconductor wafer 40 where the first bump electrode 20 is not formed is ground or polished. Since the thinned semiconductor wafer 40 is supported by the support substrate 48, it can be easily handled.

  Next, a cylindrical insulator 36 penetrating the substrate 12 is formed as necessary (see also FIG. 2). The cylindrical insulator 36 can be formed by forming a through hole penetrating the substrate 12 and then filling the insulator in the through hole.

  Next, the through electrode 30 and the second bump electrode 24 are formed (see FIG. 3C). 4A to 4F show the method of forming the through electrode 30 and the second bump electrode 24 step by step.

  First, a through hole 70 for forming the through electrode 30 is formed in the substrate 12 (see FIG. 4A). The through hole 70 is formed in a portion facing the first bump electrode 20. The electrode pad 16 is exposed at the bottom of the through hole 70. Note that the through hole 70 may be formed simultaneously with the through hole for forming the cylindrical insulator 36.

  Next, a plating resist film 72 is formed in a region where the through electrode 30 and the second bump electrode 24 are not formed (see FIG. 4B). Next, the seed layer 32 is formed on the inner surface and the bottom surface of the through hole 70. The seed layer 32 can be formed of copper, for example.

  Next, the through electrode 30 inside the through hole 70 and the second bump electrode 24 protruding from the through electrode 30 are formed by an electrolytic plating method using the seed layer 32 as a power feeding layer (FIG. 4C and FIG. 4). (Refer FIG.4 (d)).

  In the plating method, the plating metal is gradually deposited from the surface of the seed layer 32. Therefore, in the process of depositing the plating metal, a recess is formed on the top surface 24a of the second bump electrode 24 (see FIG. 4C). The plating metal deposition is stopped before the recess is completely filled. As a result, as shown in FIG. 4D, the top surface 24a of the second bump electrode 24 is a surface having a recessed central portion.

  Next, a conductive bonding material 26 made of, for example, solder is formed on the top surface 24a of the second bump electrode 24 (see FIG. 4E). As the bonding material 26, for example, solder can be used. The conductive bonding material 26 can be formed by, for example, an electrolytic plating method. The plating resist film 72 is removed from the substrate 12 in a timely manner.

  Thereafter, the conductive bonding material 26 is heated and softened or melted (annealing process). Then, the conductive bonding material 26 is solidified. The softened or melted surface 26a of the bonding material 26 becomes substantially spherical due to surface tension (see FIG. 4F). By such annealing treatment, the conductive bonding material 26 having the convex surface 26a can be formed.

  Next, a non-conductive material 38 is provided on one surface of the semiconductor wafer 40 on which the second bump electrode 24 is formed (see FIG. 3D). The non-conductive material 38 may be a non-conductive film (NCF). NCF may be a thermosetting resin or a thermoplastic resin. As described above, the softening temperature or melting temperature of the non-conductive material 38 is preferably lower than the softening temperature or melting temperature of the conductive bonding material 26.

  The non-conductive material 38 is preferably provided on almost the entire surface of the semiconductor wafer 40. As described above, by providing the non-conductive material 38 on the semiconductor wafer 40, warpage of the semiconductor wafer 40 can be suppressed.

  Next, the dicing tape 52 is attached to the nonconductive material 38. Next, the adhesive member 46 is irradiated with specific light, for example, laser light or UV light, through the support substrate 48 to foam the adhesive member 46 or reduce the adhesive force. Then, the adhesive member 46 and the support substrate 48 are removed from the semiconductor wafer 40. As a result, the first bump electrode 20 formed on the semiconductor wafer 40 is exposed (see FIG. 3E).

  Next, the semiconductor wafer 40 is cut along the dicing line 44 by a dicing blade (not shown) (see FIG. 3F). Thereby, the semiconductor wafer 40 is separated into a plurality of semiconductor chips 10. Since the non-conductive material 38 suppresses the warp of the semiconductor wafer 40, the semiconductor wafer 40 can be cut with high accuracy.

  Next, the semiconductor chip 10 is picked up from the dicing tape 52. Since the flat surface of the nonconductive material 38 is bonded to the dicing tape 52, the semiconductor chip 10 can be easily peeled from the dicing tape 52.

  If a protrusion such as a bump electrode is directly bonded to the dicing tape 52, the protrusion may be caught by the adhesive layer of the dicing tape 52, and the semiconductor chip 10 may be damaged during pickup. . However, according to the above method, since the flat surface of the non-conductive material 38 is bonded to the dicing tape 52, such a problem is prevented.

  By the above method, the semiconductor chip 10 shown in FIGS. 1A, 1B, and 2 is obtained.

  FIG. 5A to FIG. 5D show a method of forming a chip stacked body in which a plurality of semiconductor chips are stacked on each other. At least one of the plurality of semiconductor chips constituting the chip stack may be the semiconductor chip 10 described above.

  First, the first semiconductor chip 70 is placed on the bonding stage 56. The bonding stage 56 preferably has a heating mechanism (not shown) for heating the first semiconductor chip 70. A suction hole 57 for sucking and holding the first semiconductor chip 70 is formed in the bonding stage 56. The suction hole 57 is connected to a vacuum pump (not shown). The first semiconductor chip 70 is sucked and held on the bonding stage 56 through the suction hole 57.

  The first semiconductor chip 70 may have the same configuration as the semiconductor chip 10 illustrated in FIG. 3, but may have a configuration different from that of the semiconductor chip 10. In the present embodiment, the first semiconductor chip 70 includes a substrate 72, bump electrodes 76, and a circuit layer 74 formed on one surface of the substrate 12. The substrate 72 may be a substrate made of a semiconductor, preferably a silicon substrate. The circuit layer 74 has a predetermined circuit corresponding to the function of the semiconductor chip 70, for example, a memory circuit.

  On one surface of the substrate 72, electrode pads (not shown) electrically connected to the circuit of the circuit layer 74 are formed. The circuit layer 74 is covered with an insulating film (passivation film) not shown. This passivation film can be formed from, for example, a polyimide resin. The electrode pad is exposed from the opening of the passivation film.

  The bump electrode 76 is provided on the electrode pad exposed from the passivation film. The configuration of the bump electrode 76 of the first semiconductor chip 70 is the same as the configuration of the first bump electrode 20 of the semiconductor chip 10 shown in FIG. That is, the bump electrode 76 of the first semiconductor chip 70 has a convex top surface 76a.

  The first semiconductor chip 70 may have reinforcing bumps 78 having the same configuration as the first reinforcing bumps 60 of the semiconductor chip 10 shown in FIG.

  Bump electrodes are not provided on one surface of the substrate 72 opposite to the one surface on which the bump electrodes 76 are provided. The first semiconductor chip 70 does not have a through electrode. The surface of the first semiconductor chip 70 where the bump electrode 76 is not provided is flat. Therefore, the bonding stage 56 can satisfactorily hold the first semiconductor chip 70 by suction.

  Next, the second semiconductor chip 10 is mounted on the first semiconductor chip 70 by the bonding tool 58. The second semiconductor chip 10 is the semiconductor chip shown in FIG. The second semiconductor chip 10 is held by the bonding tool 58 so that the second bump electrode 24 of the second semiconductor chip 10 and the bump electrode 76 of the first semiconductor chip 10 face each other. At this time, the non-conductive material 38 provided on the second semiconductor chip 10 faces the first semiconductor chip 70.

  The bonding tool 58 has a suction hole 59 for sucking and holding the semiconductor chip, and a heating mechanism for heating the semiconductor chip. Moreover, it is preferable that the bonding tool 58 has a recess 55 on the surface holding the semiconductor chip so as not to contact the first bump electrode 10 and the first reinforcing bump 60 of the second semiconductor chip 10. Thereby, the bonding tool 58 can suck and hold the second semiconductor chip 10 satisfactorily.

  Next, the first semiconductor chip 70 and the second semiconductor chip 10 are pressed against each other while the non-conductive material 38 is softened or melted, so that the bump electrode 76 and the second electrode are connected to each other through the conductive bonding material 26. The bump electrode 24 is joined (see FIG. 5B).

  Specifically, the positions of the bump electrodes 24 and 76 are recognized by recognition marks (not shown) provided on the respective semiconductor chips 10 and 70. Then, the second bump electrode 24 of the second semiconductor chip 10 is aligned with the bump electrode 76 of the first semiconductor chip 70. Then, the second semiconductor chip 10 is pressed toward the first semiconductor chip 70 while the second semiconductor chip 10 is heated to a predetermined temperature by the bonding tool 58. At this time, the second semiconductor chip 10 is preferably heated to a temperature at which the non-conductive material 38 is softened or melted and at which the conductive bonding material 26 is not softened or melted. For example, the second semiconductor chip 10 is heated to a temperature of about 150 ° C., and a load of 10 N is applied to the second semiconductor chip 10.

  6A to 6C show the semiconductor according to the first embodiment in which the bump electrode 76 of the first semiconductor chip 70 and the second bump electrode 24 of the second semiconductor chip 10 are joined. The chip joining method is shown. First, the second semiconductor chip 10 is heated to a temperature at which the non-conductive material 38 is softened or melted, and the second semiconductor chip 10 is pressed toward the first semiconductor chip 70. At this time, the conductive bonding material 26 is not softened or melted. Then, the conductive bonding material 26 formed on the second bump electrode 24 of the second semiconductor chip 10 contacts the convex top surface 76a of the bump electrode 76 of the first semiconductor chip 70 (FIG. 6 (a)). Since the bump electrode 76 of the first semiconductor chip 70 has a convex top surface 76a and the conductive bonding material 26 has a convex surface 26a, the soft or melted nonconductive material 38 is a bump electrode. It is extruded from the region between 76 and the second bump electrode 24.

  Next, the temperature of the bonding stage 56 and the bonding tool 58 is raised to, for example, about 260 ° C., and the conductive bonding material 26 is softened or melted. At this time, the state in which the second semiconductor chip 10 is pressed toward the first semiconductor chip 70 is maintained. As a result, as shown in FIG. 6B, a part of the conductive bonding material 26 flows outward to push the softened or melted nonconductive material 38 further outward. Thereby, it is possible to prevent the non-conductive material 38 from remaining in the region between the bump electrodes 24 and 76. If the non-conductive material 38 is a thermosetting resin, the non-conductive material 38 starts to be cured at this stage.

  As the non-conductive material 38 is softened or melted, the convex top surface 76a of the bump electrode 76 and the concave top surface 24a of the second bump electrode 24 come into contact with each other. Even if the positions of the bump electrodes 24 and 76 are slightly shifted from each other, the positions of the bump electrodes 24 and 76 are corrected by the irregularities on the top surfaces of the bump electrodes 24 and 76 (see FIG. 6C). . Thereby, there is an advantage that the positional deviation between the first semiconductor chip 70 and the second semiconductor chip 10 is corrected.

  It should be noted that the reinforcing bumps 62 and 78 are similarly bonded together when the bump electrodes 24 and 76 are bonded together.

  Thereafter, both the semiconductor chips 10 and 70 are cooled to about 100 ° C. while the second semiconductor chip 10 is pressed against the first semiconductor chip 70. Thereby, the conductive bonding material 26 is cured. In this way, both the bump electrodes 24 and 76 are bonded to each other via the conductive bonding material 26. In the above method, the non-conductive material 38 can be prevented from remaining in the region between the bump electrodes 24 and 76, so that the bump electrodes 24 and 76 can be electrically connected to each other satisfactorily.

  When the non-conductive material 38 is softened or melted, it spreads in the space between the first semiconductor chip 70 and the second semiconductor chip 10 and fills the space. By providing the non-conductive material 38 on the second semiconductor chip 10 in advance, a separate step of applying an underfill material that fills the gap between the semiconductor chips 10 and 70 becomes unnecessary.

  Further, when the second semiconductor chip 10 is pressed toward the first semiconductor chip 70, the nonconductive material 38 functions as a supporter that suppresses the warp of the second semiconductor chip 10. Therefore, damage to the second semiconductor chip 10 can be suppressed.

  Next, the third-stage semiconductor chip 10 is mounted on the second semiconductor chip 10 by the same method as described above (see FIG. 5C). The third-stage semiconductor chip 10 may have the same configuration as the second-stage second semiconductor chip 10. The second bump electrode 24 of the third-stage semiconductor chip 10 is joined to the first bump electrode 20 of the second-stage semiconductor chip 10.

  The fourth-stage semiconductor chip 10 is flip-chip connected to the third-stage semiconductor chip 10 by the same method as described above. The fourth-stage semiconductor chip 10 may have the same configuration as the second-stage second semiconductor chip 10.

  Further, the fifth-stage semiconductor chip 80 is mounted on the fourth-stage semiconductor chip 10 by the same method as described above (see FIG. 5D). The fifth (uppermost) semiconductor chip 80 is smaller than the first to fourth semiconductor chips 70 and 10 and does not need to have reinforcing bumps. The uppermost semiconductor chip 80 may be an interface chip having an interface circuit as a circuit layer. Other configurations of the uppermost semiconductor chip 80, particularly the configurations related to the bump electrode, the conductive bonding material, and the nonconductive material, are the same as the configurations of the semiconductor chips 10 in the second to fourth stages.

  Next, if necessary, the uppermost semiconductor chip 80 is pressed in a state where the semiconductor chips 10, 70, 80 stacked on each other are heated to, for example, about 300 ° C. As a result, the first to fifth semiconductor chips 10, 70, 80 are finally bonded. When the nonconductive material 38 is a thermosetting resin, the nonconductive material 38 may be completely thermoset at this stage. In this way, a chip stack 90 is formed in which a plurality of semiconductor chips 10, 70, 80 are stacked on each other.

  FIG. 7A is a plan view of the chip stack 90 manufactured by the above method. FIG. 7B is a cross-sectional view of the chip stack 90 taken along line 7B-7B in FIG. A non-conductive material 38 is filled in the gaps between the respective semiconductor chips 10, 70, 80 constituting the chip stack 90.

  The first semiconductor chip 70 arranged at the lowermost stage of the chip stack 90 is as described above. The first semiconductor chip 70 may be a memory chip having a memory circuit as a circuit layer. The second semiconductor chip 10 may be a memory chip having a memory circuit as a circuit layer.

  The thickness of the lowermost first semiconductor chip 70 may be thicker than the other semiconductor chips 10 and 80. For example, the first semiconductor chip 70 may have a thickness of about 100 μm, and the second semiconductor chip 10 may have a thickness of about 50 μm.

  As described above, the first semiconductor chip 70 does not have to have another bump electrode on the surface opposite to the surface on which the through electrode penetrating the substrate 72 or the bump electrode 76 is provided. Therefore, the lowermost semiconductor chip 70 can be manufactured in the same manner as the second semiconductor chip 10 except that unnecessary processes are omitted from the manufacturing process of the second semiconductor chip 10.

  The uppermost third semiconductor chip 80 may be an interface chip having an interface circuit as a circuit layer. The interface chip may be smaller than the memory chip.

  The third semiconductor chip 80 has a bump electrode 82 on the surface facing away from the second semiconductor chip 10. The bump electrode 82 may have the same configuration as that of the first bump electrode 20 of the second semiconductor chip 10. The bump electrode 82 is connected to a wiring board described later.

  Here, the third semiconductor chip 80 is smaller than the first semiconductor chip 70 and the second semiconductor chip 10. Not limited to this, the size of the third semiconductor chip 80 may be determined as appropriate.

  Here, the chip stacked body 90 in which four memory chips and one interface chip are stacked is illustrated. However, each type of semiconductor chip 10, 70, 80 may be any type of chip. The number of semiconductor chips 10, 70, 80 constituting the chip stack 90 is not limited to five, but may be four or less or six or more.

  Next, a method for manufacturing a semiconductor device using the chip stack 90 will be described. FIG. 8A to FIG. 8E show a flow for manufacturing a semiconductor device.

  First, a wiring mother board 100 in which a plurality of wiring boards 102 are connected is prepared (see FIG. 8A). Each wiring board 102 corresponds to a wiring board constituting one semiconductor device. The wiring mother board 100 is divided into each wiring board 102 by dicing lines 104.

  Each wiring board 102 includes an insulating base 106, a connection pad 108, an external connection pad 110, a wiring pattern, a through wiring 112, a first insulating film 114, a second insulating film 116, Have For example, a glass epoxy substrate can be used as the insulating base 106.

  The wiring pattern is formed on one surface of the insulating substrate 106. The connection pad 108 is integrated with the wiring pattern. The connection pad 108 is provided at the center of the surface of the insulating base 106. The connection pad 108 is an electrode connected to the bump electrode 82 provided on the uppermost semiconductor chip 80 constituting the chip stack 90.

  The external connection pads 110 are provided on the back surface of the insulating base 106, that is, on one surface opposite to the one surface on which the connection pads 108 are provided. The through wiring 112 penetrates the insulating substrate 106. The upper part of the through wiring 112 is connected to the wiring pattern, and the lower part of the through wiring 112 is connected to the external connection pad 110. Thereby, the through wiring 112 electrically connects the external connection pad 110 and the connection pad 108.

  The first insulating film 114 covers the wiring pattern and protects the wiring pattern. The connection pad 108 is exposed from the first insulating film 114. The second insulating film 116 is provided on the back surface of the insulating substrate 106. The external connection pad 110 is exposed from the second insulating film 116.

  Next, stud bumps 118 are formed on the connection pads 108. Specifically, the stud bump 118 is formed by, for example, crimping a molten ball formed on the tip of a wire made of Au, Cu, or the like to the upper surface of the connection pad 108 by using an ultrasonic wave, and then the rear end of the wire It is formed by pulling out.

  Next, a non-conductive paste (NCP) 120 is applied to the center portion of each wiring substrate 102 so as to cover the stud bump 118. The non-conductive paste 120 may be a liquid underfill resin.

  Next, the chip stack 90 is mounted on each wiring board 102 (see FIG. 8B). Specifically, the bump electrode 82 of the third semiconductor chip 80 constituting the chip stacked body 90 is connected to the connection pad 108 of the wiring board 102 via the stud bump 118.

  The bonding between the bump electrode 82 and the connection pad 108 is performed by pressing the chip stack 90 against the wiring board 102 while the chip stack 90 and the wiring mother board 100 are heated. Thereby, the bump electrode 82 and the connection pad 108 are thermocompression bonded via the stud bump 118. At this time, the non-conductive paste 120 spreads in the space between the chip stack 90 and the wiring substrate 102 and fills the space. In this way, the chip stack 90 is connected to the wiring board 102.

  Next, the plurality of chip stacks 90 mounted on the wiring motherboard 100 are collectively sealed with a sealing body 130. The sealing body 130 may be a mold resin, for example. As the mold resin, for example, a thermosetting resin such as an epoxy resin can be used.

  The mold resin can be formed by, for example, a transfer mold method. More specifically, the wiring mother board 100 on which the chip stack 90 is mounted is accommodated in a space formed between the upper mold and the lower mold, and then the mold is heated and melted in the space. Inject resin. Next, the molten mold resin is heated (cured) at a predetermined temperature, for example, about 180 ° C., and then baked at the predetermined temperature to completely cure the mold resin. Thereby, the sealing body 130 that collectively seals the plurality of chip stacks 90 is formed.

  Next, external connection terminals 132 are formed on the plurality of external connection pads 110 formed on the wiring board 102. As the external connection terminal 132, for example, a solder ball can be used. Next, a dicing tape (not shown) is attached to the upper surface of the sealing body 130, and the wiring mother board 100 and the sealing body 130 are cut along the dicing line 104 by a dicing blade (not shown). Thereby, a plurality of semiconductor devices 134 are obtained.

  Next, by peeling the semiconductor device 134 from the dicing tape, a semiconductor device including the chip stacked body 90, that is, a CoC type (Chip on Chip) semiconductor device 134 is obtained. FIG. 9 shows a semiconductor device 134 obtained by this method. Since the configuration of the semiconductor device 134 is apparent from the above description, the description thereof is omitted.

  FIG. 10 shows a first modification of the semiconductor chip. FIG. 10 is an enlarged view of a region corresponding to the region 2A of FIG. In the semiconductor chip 140 shown in FIG. 10, the sizes of the first and second bump electrodes are different from those shown in FIG. Other configurations are the same as those shown in FIG. 1A, FIG. 1B, and FIG. 10, the same components as those in FIG. 2 are denoted by the same reference numerals.

  The semiconductor chip 140 according to the first modification includes a first bump electrode 142 having a convex top surface 142a and a second bump electrode 144 having a concave top surface 144a. A conductive bonding material 146 is provided on the top surface 144 a of the second bump electrode 144. Further, a non-conductive material 38 is provided to cover the second bump electrode 144 and the conductive bonding material 146.

  In the semiconductor chip 140 according to the first modification, the diameter of the second bump electrode 144 is larger than the diameter of the first bump electrode 142. As a result, a large-capacity conductive bonding material 146 can be formed on the second bump electrode 144. Thereby, when joining with another semiconductor chip, bump electrodes can be favorably joined.

  The semiconductor chip 140 according to the first modification can be used as the second semiconductor chip 10 or the third semiconductor chip 80 shown in FIG.

  FIG. 11 shows a second modification of the semiconductor chip. FIG. 11 is an enlarged view of a region corresponding to the region 2A in FIG. In the semiconductor chip 150 shown in FIG. 11, the shapes of the first and second bump electrodes are different from those shown in FIG. Other configurations are the same as those shown in FIG. 1A, FIG. 1B, and FIG. In FIG. 11, the same components as those in FIG. 2 are denoted by the same reference numerals.

  The semiconductor chip 150 according to the second modified example includes a first bump electrode 152 having a convex top surface 152a and a second bump electrode 154 having a concave top surface 154a. A conductive bonding material 156 is provided on the top surface 154 a of the second bump electrode 154. Further, a nonconductive material 38 is provided to cover the second bump electrode 154 and the conductive bonding material 156.

  In the semiconductor chip 150 according to the second modification, the convex top surface 152a of the first bump electrode 152 has a substantially conical shape. Further, the convex top surface 154a of the second bump electrode 154 is recessed in an inverted conical shape.

  The shape of the convex top surface 152a of the first bump electrode 152 and the shape of the convex top surface 154a of the second bump electrode 154 may be other shapes. The top surfaces of the first and second bump electrodes 152 and 154 may have any shape as long as the displacement can be corrected by pressing each other.

  The semiconductor chip 150 according to the second modification can be used as the second semiconductor chip 10 or the third semiconductor chip 80 shown in FIG.

  12A to 12C show a semiconductor chip bonding method according to the second embodiment. First, the first semiconductor chip 160 and the second semiconductor chip 170 are prepared.

  The first semiconductor chip 160 has substantially the same configuration as the first semiconductor chip 70 shown in FIGS. However, in this embodiment, the nonconductive material 180 is provided so as to cover the bump electrodes of the first semiconductor chip 160.

  The second semiconductor chip 170 has substantially the same configuration as the second semiconductor chip 10 shown in FIGS. However, in this embodiment, a non-conductive material that covers the second bump electrode 24 and the conductive bonding material 26 of the second semiconductor chip 170 is not provided.

  As described above, in this embodiment, the nonconductive material 180 is formed not on the second semiconductor chip 170 but on the first semiconductor chip 160. Other configurations of the semiconductor chip are the same as those shown in FIGS.

  Similar to the method already described with reference to FIG. 6, the bump electrode 76 of the first semiconductor chip 160 and the second bump electrode 24 of the second semiconductor chip 170 can be bonded to each other. Even in this case, the positions of the bump electrodes 24 and 76 are corrected by the irregularities on the top surfaces of the bump electrodes 24 and 76. Further, since the bump electrode 76 of the first semiconductor chip 160 has the convex top surface 76a and the conductive bonding material 26 has the convex surface 26a, the bump electrodes 24 and 76 are being bonded to each other. The softened or melted non-conductive material 180 is extruded from the region between the bump electrodes 24 and 76. As a result, the nonconductive material 180 is prevented from remaining in the region between the bump electrodes 24 and 76.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on the Example, this invention is not limited to the said Example, It cannot be overemphasized that it can change variously in the range which does not deviate from the summary.

  For example, in the above embodiment, the bump electrode provided on the surface on which the circuit layer of the semiconductor chip is formed has a convex top surface, and the bump electrode provided on the opposite surface is a concave top surface. Has a surface. Instead, the bump electrode provided on the surface of the semiconductor chip on which the circuit layer is formed has a concave top surface, and the bump electrode provided on the opposite surface has a convex top surface. You may have.

10 Semiconductor chip 20 First bump electrode 24 Second bump electrode 26 Conductive bonding material 38 Non-conductive material 70 Semiconductor chip 76 Bump electrode 140 Semiconductor chip 142 First bump electrode 144 Second bump electrode 146 Conductivity Bonding material 150 semiconductor chip 152 first bump electrode 154 second bump electrode 156 conductive bonding material 160 first semiconductor chip 170 second semiconductor chip 180 non-conductive material

Claims (15)

Providing a first semiconductor chip having a first bump electrode having a convex top surface;
A second bump electrode having a concave top surface; a conductive bonding material having a convex surface provided on the top surface of the second bump electrode; and the second bump electrode and the bonding material. Providing a second semiconductor chip having a non-conductive material covering;
The first bump electrode and the second bump electrode are pressed through the bonding material by pressing the first semiconductor chip and the second semiconductor chip together while softening or melting the nonconductive material. And bonding the semiconductor chip. Providing a first semiconductor chip having a first bump electrode having a convex top surface and a non-conductive material covering the first bump electrode;
Preparing a second semiconductor chip having a second bump electrode having a concave top surface, and a conductive bonding material having a convex surface provided on the top surface of the second bump electrode. When,
The first bump electrode and the second bump electrode are pressed through the bonding material by pressing the first semiconductor chip and the second semiconductor chip together while softening or melting the nonconductive material. And bonding the semiconductor chip.   The semiconductor chip bonding method according to claim 1, wherein a softening temperature or melting temperature of the non-conductive material is lower than a softening temperature or melting temperature of the bonding material.   During joining of the first bump electrode and the second bump electrode, after heating to the first temperature equal to or higher than the softening temperature or the melting temperature of the non-conductive material, the bonding material is softened or melted. The semiconductor chip bonding method according to claim 3, further heating to a second temperature or higher.   During the joining of the first bump electrode and the second bump electrode, the first non-conductive material is filled until the space between the first semiconductor chip and the second semiconductor chip is filled. The semiconductor chip bonding method according to claim 1, wherein the semiconductor chip and the second semiconductor chip are pressed against each other. The bonding material is solder;
The semiconductor chip bonding method according to claim 1, wherein the non-conductive material is a thermosetting resin or a thermoplastic resin.   The semiconductor chip bonding method according to claim 1, wherein a diameter of the second bump electrode is larger than a diameter of the first bump electrode. A method of manufacturing a semiconductor device including a chip stack formed by stacking a plurality of semiconductor chips,
A method for manufacturing a semiconductor device, comprising the step of bonding the semiconductor chips adjacent to each other by the method for bonding semiconductor chips according to claim 1. A bump electrode having a concave top surface;
And a conductive bonding material provided on the top surface of the bump electrode and having a convex surface.   The semiconductor chip according to claim 9, further comprising a nonconductive material that covers the bump electrode and the bonding material.   The semiconductor chip according to claim 10, wherein the non-conductive material covers one surface of the semiconductor chip on which the bump electrode is formed.   The semiconductor chip according to claim 10 or 11, wherein a softening temperature or melting temperature of the non-conductive material is lower than a softening temperature or melting temperature of the bonding material. The bonding material is solder;
The semiconductor chip according to claim 10, wherein the non-conductive material is a thermosetting resin or a thermoplastic resin. A substrate on which the bump electrode is formed;
The bump electrode according to claim 9, further comprising another bump electrode having a convex top surface, which is formed on the one surface of the substrate opposite to the one surface on which the bump electrodes are formed. Semiconductor chip.   The semiconductor chip according to claim 14, wherein a diameter of the bump electrode having the concave top surface is larger than a diameter of the another bump electrode having the convex top surface.