JP2012099693A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2012099693A
JP2012099693A JP2010247125A JP2010247125A JP2012099693A JP 2012099693 A JP2012099693 A JP 2012099693A JP 2010247125 A JP2010247125 A JP 2010247125A JP 2010247125 A JP2010247125 A JP 2010247125A JP 2012099693 A JP2012099693 A JP 2012099693A
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semiconductor
manufacturing
semiconductor device
support plate
semiconductor wafer
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Japanese (ja)
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Mitsuhisa Watabe
光久 渡部
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Micron Memory Japan Ltd
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Elpida Memory Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of improving handleability in an assembly process of a semiconductor chip and capable of suppressing damage of the semiconductor chip.SOLUTION: A method of manufacturing a semiconductor device 1 comprises: a first step of preparing a semiconductor wafer 2 including a plurality of semiconductor chips 4 partitioned by dicing lines 16; a second step of adhering a support plate 13 to the semiconductor wafer 2; a third step of dicing the semiconductor wafer 2 and the support plate 13 along the dicing lines 16 to form a laminate 3 comprising of the semiconductor chips 4 and the divided support plates 13; and a fourth step of mounting the laminate 3 on a wiring substrate 18 and electrically connecting the semiconductor chips 4 of the laminate 3 and the wiring substrate 18.

Description

本発明は、半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device.

従来、表裏に貫通した貫通電極を有する半導体チップを回路基板上に積層配置してなる半導体装置が知られている（例えば、特許文献１参照。）。   2. Description of the Related Art Conventionally, a semiconductor device is known in which semiconductor chips having through electrodes penetrating front and back are stacked on a circuit board (see, for example, Patent Document 1).

この特許文献１に記載されるような貫通電極が形成された半導体チップでは、ビア加工のアスペクト比に限界があり、シリコン基板の厚みを、要求された貫通電極の配置ピッチ以下に設定する必要がある。そのため、貫通電極の配置ピッチが微細になるにつれて、シリコン基板の厚みを薄くする必要が生じていた。そして、シリコン基板の厚みが７０μｍ以下になると、半導体チップのハンドリング性に難が生じるという問題があった。   In the semiconductor chip on which the through electrode as described in Patent Document 1 is formed, there is a limit in the aspect ratio of via processing, and it is necessary to set the thickness of the silicon substrate to be equal to or less than the required through electrode arrangement pitch. is there. Therefore, as the arrangement pitch of the through electrodes becomes finer, it is necessary to reduce the thickness of the silicon substrate. When the thickness of the silicon substrate is 70 μm or less, there is a problem that the handling property of the semiconductor chip is difficult.

そこで、半導体ウエハのハンドリング性を向上する従来技術として、支持基板で被処理基板（半導体ウエハ）を支持した状態で被処理基板を処理する工程を有する基板処理方法が知られている（例えば、特許文献２参照。）。   Thus, as a conventional technique for improving the handling properties of a semiconductor wafer, a substrate processing method having a process of processing a substrate to be processed while the substrate to be processed (semiconductor wafer) is supported by a support substrate is known (for example, a patent) Reference 2).

特開２００７−３６１８４号公報JP 2007-36184 A 特開２００７−３２４４０６号公報JP 2007-324406 A

ところが、特許文献２に記載の従来の基板処理方法では、限定された工程における半導体ウエハのハンドリング性については考慮されているものの、半導体ウエハのダイシング工程等を含む半導体チップの組立工程におけるハンドリング性については一切考慮されていなかった。   However, in the conventional substrate processing method described in Patent Document 2, although the handling property of the semiconductor wafer in a limited process is considered, the handling property in the assembly process of the semiconductor chip including the dicing process of the semiconductor wafer and the like is considered. Was not considered at all.

そこで、本発明は、従来の問題を解決するものであって、すなわち、本発明の目的は、半導体チップの組立工程におけるハンドリング性を向上し、しかも、半導体チップの損傷を回避する半導体装置の製造方法を提供することである。   Therefore, the present invention solves the conventional problems, that is, the object of the present invention is to manufacture a semiconductor device that improves handling in the semiconductor chip assembly process and avoids damage to the semiconductor chip. Is to provide a method.

本発明の半導体装置の製造方法は、ダイシングラインによって区画された複数の半導体チップを含む半導体ウエハを準備する第１の工程と、前記半導体ウエハに支持板を付着する第２の工程と、前記半導体ウエハおよび前記支持板をダイシングラインに沿って切断し、前記半導体チップおよび分割された前記支持板からなる積層体を形成する第３の工程と、前記積層体を配線基板に搭載し、前記積層体の半導体チップおよび前記配線基板を電気的に接続する第４の工程とを有することにより、前述した課題を解決したものである。   The method for manufacturing a semiconductor device of the present invention includes a first step of preparing a semiconductor wafer including a plurality of semiconductor chips partitioned by dicing lines, a second step of attaching a support plate to the semiconductor wafer, and the semiconductor A third step of cutting the wafer and the support plate along a dicing line to form a laminate comprising the semiconductor chip and the divided support plate; and mounting the laminate on a wiring board; And the fourth step of electrically connecting the wiring substrate to solve the above-described problems.

本発明では、半導体ウエハのダイシング工程等を含む半導体チップの組立工程における半導体チップのハンドリング性の向上および半導体チップの損傷の回避を実現できる。   According to the present invention, it is possible to improve the handling of the semiconductor chip and avoid the damage to the semiconductor chip in the semiconductor chip assembly process including the dicing process of the semiconductor wafer.

本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体ウエハの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the manufacturing flow of a semiconductor wafer typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体ウエハの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the manufacturing flow of a semiconductor wafer typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体ウエハの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the manufacturing flow of a semiconductor wafer typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体ウエハの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the manufacturing flow of a semiconductor wafer typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第１実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 1st Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第２実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 2nd Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第２実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 2nd Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第２実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 2nd Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第２実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 2nd Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第２実施例である半導体装置の製造方法を説明する図であり、半導体装置の組立フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 2nd Example of this invention, and is process drawing which shows the assembly flow of a semiconductor device typically. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップの製造フローを模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the manufacture flow of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate. 本発明の第３実施例である半導体装置の製造方法を説明する図であり、支持基板付半導体チップのボンディング工程を模式的に示す工程図である。It is a figure explaining the manufacturing method of the semiconductor device which is 3rd Example of this invention, and is process drawing which shows typically the bonding process of the semiconductor chip with a support substrate.

以下に、具体例に沿って、本発明に係る半導体装置の製造方法を説明する。なお、本発明で用いる「表面」は、半導体ウエハの回路形成面のことを意味し、また、「裏面」は、前記表面の反対側の面のことを意味しており、配線基板や半導体装置の現実の姿勢を限定するものではない。また、以下の説明に用いる各図面は、各部を認識可能な大きさとするため、各部材の縮尺を適宜変更している。   A method for manufacturing a semiconductor device according to the present invention will be described below with reference to specific examples. The “front surface” used in the present invention means a circuit forming surface of a semiconductor wafer, and the “back surface” means a surface on the opposite side of the front surface. The real attitude is not limited. In the drawings used for the following description, the scale of each member is appropriately changed to make each part recognizable.

以下に、本発明の第１実施例である半導体装置の製造方法を図１Ａ乃至図４Ｅを用いて説明する。   A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIGS. 1A to 4E.

初めに、第１実施例における半導体ウエハ２の製造フローを図１Ａ乃至図１Ｄに基づいて説明する。   First, the manufacturing flow of the semiconductor wafer 2 in the first embodiment will be described with reference to FIGS. 1A to 1D.

まず、図１Ａに示すように、シリコン基板６の回路形成面（以下、表面と称する）２６には、半導体ウエハ２の個々のチップ領域毎に、所定の回路（例えばメモリ回路と電極パッド）上に、表面側バンプ電極８が形成される。表面側バンプ電極８は、例えばＣｕ等からなり、表面側バンプ電極８の外面（表面）には、Ｎｉ／Ａｕメッキ層が形成されている。また、表面側バンプ電極８の下方には、絶縁層に囲まれた導体層９が所定の深さで形成されている。この導体層９は、例えばＣｕから成る。なお、図１Ａ乃至図１Ｄの符号１６は、ダイシングラインを示している。   First, as shown in FIG. 1A, a circuit formation surface (hereinafter referred to as a surface) 26 of the silicon substrate 6 is provided on a predetermined circuit (for example, a memory circuit and an electrode pad) for each chip region of the semiconductor wafer 2. Then, the front surface side bump electrode 8 is formed. The surface side bump electrode 8 is made of, for example, Cu, and a Ni / Au plating layer is formed on the outer surface (surface) of the surface side bump electrode 8. A conductor layer 9 surrounded by an insulating layer is formed at a predetermined depth below the surface-side bump electrode 8. The conductor layer 9 is made of Cu, for example. In addition, the code | symbol 16 of FIG. 1A thru | or FIG. 1D has shown the dicing line.

次に、図１Ｂに示すように、半導体ウエハ２は、第１接着層１２を介して、ウエハサポート部材（支持板）１１により、その表面側を保持される。このウエハサポート部材１１としては、例えばガラス基板が用いられる。また、第１接着層１２としては、例えばＵＶ硬化型アクリル系の接着材が使用される。また、第１接着層１２は、例えば２０μｍ程度の高さの表面側バンプ電極８を覆う場合には、５０μｍ程度の厚さで形成される。
このように、表面側バンプ電極８を突出形成した半導体ウエハ２の表面側と、ウエハサポート部材１１との間に、第１接着層１２を介在させることにより、表面側バンプ電極８を損傷することなく、ウエハサポート部材１１により半導体ウエハ２を良好に保持することができる。 Next, as shown in FIG. 1B, the surface side of the semiconductor wafer 2 is held by the wafer support member (support plate) 11 through the first adhesive layer 12. For example, a glass substrate is used as the wafer support member 11. Further, as the first adhesive layer 12, for example, a UV curable acrylic adhesive is used. The first adhesive layer 12 is formed with a thickness of about 50 μm, for example, when covering the surface side bump electrode 8 with a height of about 20 μm.
Thus, the surface-side bump electrode 8 is damaged by interposing the first adhesive layer 12 between the surface side of the semiconductor wafer 2 on which the surface-side bump electrode 8 is protruded and the wafer support member 11. The semiconductor wafer 2 can be satisfactorily held by the wafer support member 11.

次に、図１Ｃに示すように、ウエハサポート部材１１により表面側を保持された半導体ウエハ２は、バックグラインド工程に移行され、ウエハサポート部材１１に保持された状態で半導体ウエハ２の裏面を所定の厚さ、例えば５０μｍ厚まで研削し、半導体ウエハ２の裏面から導体層９を露出させると共に、半導体ウエハ２を薄型化する。
このように、ウエハサポート部材１１により、薄型化された半導体ウエハ２を保持しているため、薄型化された半導体ウエハ２の搬送等、取り扱いが容易になる。 Next, as shown in FIG. 1C, the semiconductor wafer 2 held on the front surface side by the wafer support member 11 is transferred to a back grinding process, and the back surface of the semiconductor wafer 2 is set to a predetermined state while being held on the wafer support member 11. To a thickness of 50 μm, for example, to expose the conductor layer 9 from the back surface of the semiconductor wafer 2 and to reduce the thickness of the semiconductor wafer 2.
Thus, since the thinned semiconductor wafer 2 is held by the wafer support member 11, handling such as transportation of the thinned semiconductor wafer 2 is facilitated.

次に、図１Ｄに示すように、半導体ウエハ２の裏面側（すなわち、後述する支持基板１３を搭載する半導体ウエハ２の搭載面側）から露出した導体層９上に、裏面側バンプ電極１０を形成する。この裏面側バンプ電極１０は、シリコン基板６の厚み方向において表面側バンプ電極８に対応する位置に形成される。この裏面側バンプ電極１０は、例えばＣｕからなり、裏面側バンプ電極１０の外面（表面）には、ＳｎＡｇメッキ層が形成されている。   Next, as shown in FIG. 1D, the back surface side bump electrode 10 is formed on the conductor layer 9 exposed from the back surface side of the semiconductor wafer 2 (that is, the mounting surface side of the semiconductor wafer 2 on which the support substrate 13 described later is mounted). Form. The back side bump electrode 10 is formed at a position corresponding to the front side bump electrode 8 in the thickness direction of the silicon substrate 6. The back surface side bump electrode 10 is made of, for example, Cu, and an SnAg plating layer is formed on the outer surface (front surface) of the back surface side bump electrode 10.

以上のように、一面に複数のチップ領域と、貫通電極７を有し、第１接着層１２を介してウエハサポート部材１１により表面側を保持された半導体ウエハ２が準備される。   As described above, the semiconductor wafer 2 having a plurality of chip regions and the through electrodes 7 on one surface and having the surface side held by the wafer support member 11 via the first adhesive layer 12 is prepared.

次に、第１実施例における支持基板付半導体チップ３の製造フローを図２Ａ乃至図２Ｃに基づいて説明する。   Next, a manufacturing flow of the semiconductor chip 3 with the supporting substrate in the first embodiment will be described based on FIGS. 2A to 2C.

まず、図２Ａに示すように、ウエハサポート部材１１により表面側を保持された半導体ウエハ２は、第２接着層１４を介して、支持基板（支持板）１３により裏面側を保持される。この支持基板１３としては、例えば、シリコン基板、ガラスエポキシ基板、エポキシ樹脂基板、ＳＵＳ基板、Ａｌ基板が用いられる。また、第２接着層１４としては、例えばウエハサポート部材１１と同様に、ＵＶ硬化型アクリル系の接着材が使用される。また、第２接着層１４は、例えば２０μｍ程度の高さの裏面側バンプ電極１０を覆う場合には、５０μｍ程度の厚さで構成される。   First, as shown in FIG. 2A, the semiconductor wafer 2 held on the front side by the wafer support member 11 is held on the back side by the support substrate (support plate) 13 through the second adhesive layer 14. As the support substrate 13, for example, a silicon substrate, a glass epoxy substrate, an epoxy resin substrate, a SUS substrate, or an Al substrate is used. As the second adhesive layer 14, for example, a UV curable acrylic adhesive is used as in the wafer support member 11. In addition, the second adhesive layer 14 is configured to have a thickness of about 50 μm, for example, when the back surface side bump electrode 10 having a height of about 20 μm is covered.

次に、図２Ｂに示すように、半導体ウエハ２は、ウエハサポート部材１１のデマウント工程に移行される。このデマウント工程では、例えば、ウエハサポート部材１１の第１接着層１２に紫外線を照射し、接着力を低下させ、ウエハサポート部材１１を除去する。これにより、半導体ウエハ２の表面側を露出させる。この際、支持基板１３の第２接着層１４が、ウエハサポート部材１１の第１接着層１２への紫外線照射時に影響を受け可能性もあるため、支持基板１３の第２接着層１４として、ウエハサポート部材１１の第１接着層１２とは異なるＵＶ硬化特性を有する接着材を用いる方が好ましい。例えば、有る一定の温度以上で剥離性を発現する接着材が挙げられる。   Next, as shown in FIG. 2B, the semiconductor wafer 2 is transferred to a demounting process of the wafer support member 11. In this demounting process, for example, the first adhesive layer 12 of the wafer support member 11 is irradiated with ultraviolet rays to reduce the adhesive force, and the wafer support member 11 is removed. Thereby, the surface side of the semiconductor wafer 2 is exposed. At this time, since the second adhesive layer 14 of the support substrate 13 may be affected when the first adhesive layer 12 of the wafer support member 11 is irradiated with ultraviolet rays, the second adhesive layer 14 of the support substrate 13 is used as the wafer. It is preferable to use an adhesive having a UV curing property different from that of the first adhesive layer 12 of the support member 11. For example, an adhesive that exhibits peelability at a certain temperature or higher can be used.

次に、図２Ｃに示すように、ダイシング工程に移行され、半導体ウエハ２の裏面側に配置された支持基板１３にダイシングテープ１５を貼り付ける。このダイシング工程では、ダイシング装置（図示しない）により、半導体ウエハ２の表面側のチップ領域間のダイシングライン１６を認識し、認識されたダイシングライン１６に基づき、半導体ウエハ２の裏面側から、高速回転するダイシングブレード（図示しない）によりダイシングライン１６を切断する。このダイシングでは、支持基板１３の第２接着層１４の一部まで切断されるように調整されており、半導体ウエハ２と支持基板１３は、完全にチップ領域（半導体チップ４）毎に切断される。そして、半導体ウエハ２を表面側からダイシングライン１６を切断し、半導体ウエハ２は、個々の半導体チップ４毎に切断分離され、支持基板付半導体チップ（積層体）３が得られる。   Next, as shown in FIG. 2C, the dicing process is performed, and the dicing tape 15 is attached to the support substrate 13 disposed on the back surface side of the semiconductor wafer 2. In this dicing process, a dicing apparatus (not shown) recognizes a dicing line 16 between chip regions on the front surface side of the semiconductor wafer 2 and rotates at high speed from the back surface side of the semiconductor wafer 2 based on the recognized dicing line 16. The dicing line 16 is cut by a dicing blade (not shown). In this dicing, adjustment is made so that a part of the second adhesive layer 14 of the support substrate 13 is cut, and the semiconductor wafer 2 and the support substrate 13 are completely cut for each chip region (semiconductor chip 4). . Then, the dicing line 16 is cut from the front surface side of the semiconductor wafer 2, and the semiconductor wafer 2 is cut and separated for each individual semiconductor chip 4 to obtain a semiconductor chip (laminated body) 3 with a supporting substrate.

このように支持基板付半導体チップ３を構成したことにより、ダイシングテープ１５からピックアップ装置（図示しない）により各半導体チップ４（支持基板付半導体チップ３）を突き上げてピックアップする際に、貫通電極７を有する半導体チップ４が支持基板１３により補強されているため、チップクラックの発生等を抑制し、良好にダイシングテープ１５から半導体チップ４（支持基板付半導体チップ３）をピックアップすることができる。また、ダイシングテープ１５に貼り付けられる面側に支持基板１３を配置していることにより、半導体チップ４（支持基板付半導体チップ３）が直接的に突き上げられることを回避するため、突き上げ時におけるチップクラックの発生をより一層低減できる。   Since the semiconductor chip 3 with the support substrate is configured as described above, when the semiconductor chip 4 (the semiconductor chip 3 with the support substrate) is pushed up and picked up from the dicing tape 15 by the pickup device (not shown), the through electrode 7 is inserted. Since the semiconductor chip 4 is reinforced by the support substrate 13, generation of chip cracks and the like can be suppressed, and the semiconductor chip 4 (semiconductor chip 3 with support substrate) can be picked up from the dicing tape 15 satisfactorily. In addition, since the support substrate 13 is arranged on the side to be attached to the dicing tape 15, the semiconductor chip 4 (semiconductor chip with support substrate 3) is prevented from being pushed up directly, so that the chip at the time of pushing up The generation of cracks can be further reduced.

次に、第１実施例における支持基板付半導体チップ３を用いたボンディング工程を図３Ａ乃至図３Ｅに基づいて説明する。   Next, a bonding process using the semiconductor chip 3 with a support substrate in the first embodiment will be described with reference to FIGS. 3A to 3E.

まず、図３Ａに示すように、支持基板付半導体チップ３が搭載される配線基板１８が準備される。この配線基板１８は、例えば０．１４ｍｍ厚のガラスエポキシ配線基板であり、マトリックス状に配置された複数の製品形成部１９を有している。配線基板１８の複数の製品形成部１９には、それぞれ所定の配線パターンが形成され、配線２２は、部分的に絶縁膜、例えばソルダーレジストで覆われている。また、製品形成部１９間は、ダイシングライン１７となる。製品形成部１９の一面側の配線２２のソルダーレジストから露出された部位には、複数の接続パッド２１が形成されている。また、製品形成部１９の他面の配線２２のソルダーレジストから露出された部位には、複数のランド２０が形成されている。そして、接続パッド２１と、接続パッド２１に対応するランド２０とは、配線基板１８の配線２２によりそれぞれ電気的に接続されている。   First, as shown in FIG. 3A, a wiring substrate 18 on which the semiconductor chip 3 with a supporting substrate is mounted is prepared. The wiring board 18 is a glass epoxy wiring board having a thickness of 0.14 mm, for example, and has a plurality of product forming portions 19 arranged in a matrix. A predetermined wiring pattern is formed on each of the plurality of product forming portions 19 of the wiring substrate 18, and the wiring 22 is partially covered with an insulating film, for example, a solder resist. Further, a dicing line 17 is formed between the product forming portions 19. A plurality of connection pads 21 are formed in a portion exposed from the solder resist of the wiring 22 on one surface side of the product forming portion 19. In addition, a plurality of lands 20 are formed in a portion exposed from the solder resist of the wiring 22 on the other surface of the product forming portion 19. The connection pad 21 and the land 20 corresponding to the connection pad 21 are electrically connected to each other by the wiring 22 of the wiring board 18.

次に、図３Ｂに示すように、配線基板１８は、ボンディング工程に移行される。このボンディング工程では、例えばボンディング装置（図示しない）のボンディングツール（図示しない）により、支持基板付半導体チップ３の支持基板１３を配置した裏面側を吸着保持する。そして、配線基板１８の各製品形成部１９に、支持基板付半導体チップ３を、ボンディングツールにより高温、例えば３００℃程度で荷重を印加し、フリップチップボンディングする。これにより、図３Ｂに示すように、配線基板１８の各製品形成部１９に、支持基板付半導体チップ３が搭載され、支持基板付半導体チップ３の表面側バンプ電極８と配線基板１８の接続パッド２１とが電気的に接続される。なお、支持基板付半導体チップ３の接合は、荷重だけでなく、超音波も印加するように構成してもよい。   Next, as shown in FIG. 3B, the wiring board 18 is transferred to a bonding process. In this bonding step, for example, the back surface side on which the support substrate 13 of the semiconductor chip 3 with the support substrate is arranged is suction-held by a bonding tool (not shown) of a bonding apparatus (not shown). Then, a flip chip bonding is performed on each product forming portion 19 of the wiring substrate 18 by applying a load at a high temperature, for example, about 300 ° C., using a bonding tool to the semiconductor chip 3 with a supporting substrate. As a result, as shown in FIG. 3B, the semiconductor chip 3 with the support substrate is mounted on each product forming portion 19 of the wiring substrate 18, and the front surface bump electrodes 8 of the semiconductor chip 3 with the support substrate and the connection pads of the wiring substrate 18. 21 is electrically connected. In addition, you may comprise the joining of the semiconductor chip 3 with a support substrate so that not only a load but an ultrasonic wave may be applied.

ここで、本実施例では、支持基板付半導体チップ３の裏面側バンプ電極１０にはＳｎＡｇメッキ層が形成されているが、支持基板１３を介して、ボンディングツールに保持されることで、ＳｎＡｇメッキ層の溶融温度までボンディングツールが加熱されても、裏面側バンプ電極１０のＳｎＡｇメッキがボンディングツールに付着することなく、支持基板付半導体チップ３の表面側を配線基板１８に対して良好にフリップチップボンディングすることができる。   Here, in this embodiment, the SnAg plating layer is formed on the back-side bump electrode 10 of the semiconductor chip 3 with the support substrate. However, the SnAg plating is held by the bonding tool via the support substrate 13. Even if the bonding tool is heated up to the melting temperature of the layer, the SnAg plating of the back-side bump electrode 10 does not adhere to the bonding tool, and the front surface side of the semiconductor chip 3 with the support substrate is flip-chip well with respect to the wiring substrate 18. Can be bonded.

次に、図３Ｃに示すように、配線基板１８に搭載された支持基板付半導体チップ３の第２接着層１４に紫外線を照射し、第２接着層１４の接着力を低下させ、個片化された支持基板１３を除去する。これにより、配線基板１８に搭載された半導体チップ４の裏面側は露出される。なお、支持基板１３の除去は、他の支持基板１３に各支持基板１３を貼り付け、一括で除去、或いは、支持基板１３を研削することで、除去するように構成してもよい。   Next, as shown in FIG. 3C, the second adhesive layer 14 of the semiconductor chip 3 with the supporting substrate mounted on the wiring board 18 is irradiated with ultraviolet rays to reduce the adhesive force of the second adhesive layer 14 and to singulate. The formed support substrate 13 is removed. Thereby, the back surface side of the semiconductor chip 4 mounted on the wiring board 18 is exposed. The support substrate 13 may be removed by attaching each support substrate 13 to another support substrate 13 and removing the support substrate 13 at a time or grinding the support substrate 13.

次に、図３Ｄに示すように、配線基板１８上に搭載された半導体チップ４の裏面側に、２段目の支持基板付半導体チップ３をフリップチップボンディングにより搭載する。これにより、配線基板１８上に搭載された１段目の半導体チップ４の裏面上に、２段目の支持基板付半導体チップ３が搭載され、１段目の半導体チップ４の裏面側バンプ電極１０のＳｎＡｇメッキ層と２段目の支持基板付半導体チップ３の表面側バンプ電極８のＮｉ／Ａｕメッキ層とが電気的に接続される。   Next, as shown in FIG. 3D, the second-stage semiconductor chip with support substrate 3 is mounted on the back side of the semiconductor chip 4 mounted on the wiring substrate 18 by flip chip bonding. As a result, the second-stage semiconductor chip 3 with the supporting substrate is mounted on the back surface of the first-stage semiconductor chip 4 mounted on the wiring substrate 18, and the back-side bump electrode 10 of the first-stage semiconductor chip 4. The SnAg plating layer is electrically connected to the Ni / Au plating layer of the front surface side bump electrode 8 of the semiconductor chip 3 with the second support substrate.

次に、図３Ｅに示すように、１段目の支持基板付半導体チップ３と同様に、２段目の支持基板付半導体チップ３の支持基板１３が除去され、配線基板１８の各製品形成部１９に、２段の半導体チップ４により構成されたチップ積層体５が形成される。   Next, as shown in FIG. 3E, the support substrate 13 of the second-stage semiconductor substrate 3 with the support substrate is removed as in the first-stage semiconductor chip 3 with the support substrate, and each product forming portion of the wiring board 18 In 19, a chip stacked body 5 constituted by the two-stage semiconductor chips 4 is formed.

このように、半導体チップ４に支持基板１３を固着し、５０μｍ程度の厚さで貫通電極７を有する半導体チップ４を支持基板１３により保持するように構成したことにより、既存のボンディング装置で、５０μｍ程度の薄い半導体チップ４を、チップクラックを発生させることなく良好にハンドリングすることができ、半導体装置１の組立工程での歩留を向上させることができる。また、支持基板付半導体チップ３を配線基板１８に実装した後、支持基板１３を除去するように構成することで、貫通電極７を有する半導体チップ４を多段に積層できる。
また、半導体チップ４の裏面側に支持基板１３を設けることで、半導体チップ４の裏面側バンプ電極１０にＳｎＡｇメッキ層が形成されていても、支持基板１３を介してボンディングツール（図示しない）により保持されるため、ＳｎＡｇメッキ層の溶融温度までボンディングツールが加熱されても、裏面側バンプ電極１０のＳｎＡｇメッキがボンディングツールに付着することなく、半導体チップ４のＳｎＡｇメッキ層側を保持することができる。 As described above, the support substrate 13 is fixed to the semiconductor chip 4 and the semiconductor chip 4 having the through electrode 7 having a thickness of about 50 μm is held by the support substrate 13. The thin semiconductor chip 4 can be satisfactorily handled without generating a chip crack, and the yield in the assembly process of the semiconductor device 1 can be improved. In addition, the semiconductor chip 4 having the through electrodes 7 can be stacked in multiple stages by removing the support substrate 13 after mounting the semiconductor chip 3 with the support substrate on the wiring substrate 18.
Further, by providing the support substrate 13 on the back surface side of the semiconductor chip 4, even if a SnAg plating layer is formed on the back surface side bump electrode 10 of the semiconductor chip 4, a bonding tool (not shown) is interposed through the support substrate 13. Therefore, even when the bonding tool is heated to the melting temperature of the SnAg plating layer, the SnAg plating layer side of the semiconductor chip 4 can be held without the SnAg plating of the back surface side bump electrode 10 adhering to the bonding tool. it can.

次に、第１実施例における半導体装置１の組立フローを図４Ａ乃至図４Ｅに基づいて説明する。   Next, an assembly flow of the semiconductor device 1 in the first embodiment will be described with reference to FIGS. 4A to 4E.

まず、図４Ａに示すように、チップ積層体５が形成された配線基板１８は、アンダーフィル封止工程に移行される。このアンダーフィル封止工程では、ポッティング装置（図示しない）により、各チップ積層体５の端部の近傍位置にアンダーフィル材２３を供給する。供給されたアンダーフィル材２３は、毛細管現象により、積層された半導体チップ４間の隙間に充填される。そして、チップ積層体５へのアンダーフィル材２３の充填完了後、所定温度、例えば１５０℃程度でキュアすることで、アンダーフィル材２３が硬化され、図４Ａに示すように、配線基板１８上のチップ積層体５の周囲及び半導体チップ４間にアンダーフィル材２３の層が形成される。   First, as shown to FIG. 4A, the wiring board 18 in which the chip | tip laminated body 5 was formed transfers to an underfill sealing process. In this underfill sealing step, the underfill material 23 is supplied to a position near the end of each chip stack 5 by a potting device (not shown). The supplied underfill material 23 is filled in the gaps between the stacked semiconductor chips 4 by capillary action. Then, after the filling of the underfill material 23 into the chip laminate 5 is completed, the underfill material 23 is cured by curing at a predetermined temperature, for example, about 150 ° C., and as shown in FIG. A layer of underfill material 23 is formed around the chip stack 5 and between the semiconductor chips 4.

次に、図４Ｂに示すように、チップ積層体５が搭載された配線基板１８は、モールド工程に移行される。このモールド工程では、配線基板１８は、トランスファモールド装置（図示しない）の上型と下型からなる成型金型（図示しない）にセットされる。成型金型の上型には複数のチップ搭載部を一括的に覆うようにキャビティが形成されており、このキャビティ内に配線基板１８上のチップ積層体５が配置される。そして、ゲート部からキャビティ内に加熱溶融された封止樹脂２４を注入し、配線基板１８のチップ積層体５の搭載面側を封止する。この封止樹脂２４としては、例えばエポキシ樹脂等の熱硬化性樹脂が用いられる。そして、配線基板１８の一面側のキャビティが封止樹脂２４で充填された状態で、所定の温度、例えば１８０℃程度でキュアすることで、封止樹脂２４が熱硬化され、図４Ｂに示すように、配線基板１８の複数の製品形成部１９を一括的に覆う封止樹脂２４の層が形成される。その後、封止樹脂２４の層が形成された配線基板１８を、所定の温度でベークすることで、封止樹脂２４が完全に硬化される。   Next, as shown in FIG. 4B, the wiring board 18 on which the chip stack 5 is mounted is transferred to a molding process. In this molding step, the wiring board 18 is set in a molding die (not shown) composed of an upper mold and a lower mold of a transfer mold apparatus (not shown). A cavity is formed in the upper mold of the molding die so as to collectively cover a plurality of chip mounting portions, and the chip stack 5 on the wiring board 18 is disposed in the cavity. Then, a sealing resin 24 heated and melted is injected into the cavity from the gate portion, and the mounting surface side of the chip stack 5 of the wiring substrate 18 is sealed. As the sealing resin 24, for example, a thermosetting resin such as an epoxy resin is used. Then, in a state where the cavity on one surface side of the wiring board 18 is filled with the sealing resin 24, the sealing resin 24 is cured by curing at a predetermined temperature, for example, about 180 ° C., as shown in FIG. 4B. In addition, a layer of the sealing resin 24 that collectively covers the plurality of product forming portions 19 of the wiring board 18 is formed. Thereafter, the wiring substrate 18 on which the layer of the sealing resin 24 is formed is baked at a predetermined temperature, whereby the sealing resin 24 is completely cured.

このように、配線基板１８とチップ積層体５間と、チップ積層体５の半導体チップ４間とに接着部材（アンダーフィル材２３）が充填された状態で、配線基板１８上を一括的に覆う封止樹脂２４層を形成したことで、モールド時における半導体チップ４間へのボイドの発生を抑制できる。   As described above, the wiring substrate 18 is collectively covered with the adhesive member (underfill material 23) filled between the wiring substrate 18 and the chip stack 5 and between the semiconductor chips 4 of the chip stack 5. By forming the sealing resin 24 layer, generation of voids between the semiconductor chips 4 during molding can be suppressed.

次に、図４Ｃに示すように、封止樹脂２４の層が形成された配線基板１８は、ボールマウント工程に移行され、配線基板１８の他面に形成されたランド２０に、導電性の金属ボール２５、例えば半田ボールを搭載し、外部端子を形成する。このボールマウント工程では、配線基板１８上に配置された複数のランド２０に合せて、複数の吸着孔が形成されたボールマウンター（図示しない）のマウントツール（図示しない）を用いて、半田等からなる金属ボール２５をマウントツールで吸着保持し、吸着保持された金属ボール２５にフラックスを転写形成し、配線基板１８上の複数のランド２０に一括搭載する。そして、全ての製品形成部１９への金属ボール２５搭載後、配線基板１８をリフローすることで外部端子が形成される。   Next, as shown in FIG. 4C, the wiring substrate 18 on which the sealing resin 24 layer is formed is transferred to a ball mounting process, and a conductive metal is formed on the land 20 formed on the other surface of the wiring substrate 18. A ball 25, such as a solder ball, is mounted to form an external terminal. In this ball mounting process, a mounting tool (not shown) of a ball mounter (not shown) in which a plurality of suction holes are formed in accordance with the plurality of lands 20 arranged on the wiring board 18 is used to perform soldering or the like. The metal balls 25 are sucked and held by a mounting tool, a flux is transferred and formed on the sucked and held metal balls 25, and are collectively mounted on a plurality of lands 20 on the wiring board 18. Then, after the metal balls 25 are mounted on all the product forming portions 19, the external terminals are formed by reflowing the wiring board 18.

次に、図４Ｄに示すように、金属ボール２５が搭載された配線基板１８は、基板ダイシング工程に移行され、配線基板１８を切断し、個々の製品形成部１９毎に分離する。この基板ダイシング工程では、配線基板１８の封止樹脂２４の層側にダイシングテープ１５を貼着し、ダイシングテープ１５によって配線基板１８を支持する。その後、ダイシング装置（図示しない）のダイシングブレード（図示しない）により縦横に切断して、製品形成部１９毎に分離する。そして配線基板１８の切断分離後、ダイシングテープ１５からピックアップすることで、図４Ｅに示すような複数のＣｏＣ型の半導体装置１が得られる。   Next, as shown in FIG. 4D, the wiring board 18 on which the metal balls 25 are mounted is transferred to a substrate dicing process, and the wiring board 18 is cut and separated into individual product forming portions 19. In this substrate dicing process, the dicing tape 15 is adhered to the layer side of the sealing resin 24 of the wiring substrate 18, and the wiring substrate 18 is supported by the dicing tape 15. Thereafter, the product is cut into vertical and horizontal directions by a dicing blade (not shown) of a dicing apparatus (not shown) and separated into product forming portions 19. After the wiring substrate 18 is cut and separated, a plurality of CoC type semiconductor devices 1 as shown in FIG. 4E are obtained by picking up from the dicing tape 15.

次に、本発明の第２実施例である半導体装置の製造方法を図５Ａ乃至図５Ｅに基づいて説明する。
ここで、第１実施例においては、配線基板１８のアンダーフィル封止工程へ移行する際に、最上段に位置する支持基板付半導体チップ３から支持基板１３を除去したが、第２実施例においては、後述するように、最上段に位置する支持基板付半導体チップ３に支持基板１３を残存させている。そして、この事以外の構成については、前述した第１実施例の内容と全く同じであるため、その説明を省略する。 Next, a semiconductor device manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. 5A to 5E.
Here, in the first embodiment, the support substrate 13 is removed from the semiconductor chip 3 with the support substrate positioned at the uppermost stage when the process proceeds to the underfill sealing step of the wiring substrate 18, but in the second embodiment, As will be described later, the support substrate 13 is left on the semiconductor chip 3 with the support substrate positioned at the uppermost stage. Since the configuration other than this is exactly the same as that of the first embodiment described above, the description thereof is omitted.

第２実施例である半導体装置の製造方法では、配線基板１８のアンダーフィル封止工程へ移行する際に、最上段の支持基板１３をチップ積層体５に残存させている。詳述すると、支持基板１３が絶縁部材、或いは、支持基板１３が導電材料であっても絶縁性の接着材で絶縁分離されている場合には、図５Ａに示すように、最上段に積層される支持基板付半導体チップ３に支持基板１３を残存させても何ら構わない。これにより、第１実施例における効果に加えて、配線基板１８上のチップ積層体５を補強することができ、チップ積層体５にかかる熱膨張率の差異による応力を緩和できる。また、最上段の支持基板１３の除去工程も不要となり、製造負担を低減できる。また、支持基板１３が導電材である場合、すなわち、放熱特性の高い材料から成る場合には、半導体装置１の放熱性を向上できる。   In the semiconductor device manufacturing method according to the second embodiment, the uppermost support substrate 13 is left in the chip stack 5 when the process proceeds to the underfill sealing process of the wiring substrate 18. More specifically, when the support substrate 13 is an insulating member, or when the support substrate 13 is a conductive material and is insulated and separated by an insulating adhesive, it is stacked at the top as shown in FIG. 5A. The support substrate 13 may be left on the semiconductor chip 3 with the support substrate. Thereby, in addition to the effects in the first embodiment, the chip stack 5 on the wiring board 18 can be reinforced, and the stress due to the difference in thermal expansion coefficient applied to the chip stack 5 can be relieved. Further, the process of removing the uppermost support substrate 13 is not required, and the manufacturing burden can be reduced. Further, when the support substrate 13 is a conductive material, that is, when the support substrate 13 is made of a material having high heat dissipation characteristics, the heat dissipation of the semiconductor device 1 can be improved.

次に、本発明の第３実施例である半導体装置の製造方法を図６Ａ乃至図７Ｅに基づいて説明する。
ここで、第１実施例においては、第２接着層１４を介して支持基板１３を半導体ウエハ２上に設けたが、第３実施例においては、後述するように、第２接着層１４を介することなく支持基板１３を半導体ウエハ２上に設けている。そして、この事に関する事以外の構成については、前述した第１実施例の内容と全く同じであるため、その説明を省略する。 Next, a semiconductor device manufacturing method according to the third embodiment of the present invention will be described with reference to FIGS. 6A to 7E.
Here, in the first embodiment, the support substrate 13 is provided on the semiconductor wafer 2 via the second adhesive layer 14. However, in the third embodiment, the second adhesive layer 14 is interposed as described later. The support substrate 13 is provided on the semiconductor wafer 2 without any problem. Since the configuration other than that related to this is exactly the same as the contents of the first embodiment described above, the description thereof is omitted.

第３実施例である半導体装置の製造方法では、図６Ａに示すように、ウエハサポート部材１１に支持された半導体ウエハ２の裏面上に、絶縁性の樹脂をスピンナー塗布により均一で所定の厚さの支持基板１３の層が形成される。次に、図６Ｂに示すように、実施例１と同様に、ウエハサポート部材１１が除去され、図６Ｃに示すように、ダイシングされて、図６Ｃに示すような支持基板付半導体チップ３が形成できる。次に、図７Ｂに示すように、実施例１と同様に、支持基板付半導体チップ３が配線基板１８に搭載される。次に、図７Ｃに示すように、バックグラインドにより支持基板１３を研削し、裏面側バンプ電極１０が露出されるまで支持基板１３を除去する。   In the method of manufacturing a semiconductor device according to the third embodiment, as shown in FIG. 6A, an insulating resin is uniformly applied to the predetermined thickness by spinner application on the back surface of the semiconductor wafer 2 supported by the wafer support member 11. A layer of the support substrate 13 is formed. Next, as shown in FIG. 6B, the wafer support member 11 is removed and diced as shown in FIG. 6C to form the semiconductor chip 3 with a supporting substrate as shown in FIG. 6C, as in the first embodiment. it can. Next, as shown in FIG. 7B, the semiconductor chip 3 with a supporting substrate is mounted on the wiring substrate 18 as in the first embodiment. Next, as shown in FIG. 7C, the support substrate 13 is ground by back grinding, and the support substrate 13 is removed until the back surface side bump electrode 10 is exposed.

このように、第３実施例においては、半導体ウエハ２に、スピンナー塗布により、絶縁樹脂からなる支持基板１３の層を形成し、支持基板付半導体チップ３を配線基板１８に実装した後、支持基板１３の層を研削して除去することで、実施例１と同様に、半導体チップ３のハンドリング性を向上できると共に、支持基板１３の層形成の際、薄化された半導体ウエハ２に面方向荷重がかからないためダメージのより少ない形成が可能である。   Thus, in the third embodiment, a layer of the support substrate 13 made of an insulating resin is formed on the semiconductor wafer 2 by spinner coating, and the semiconductor chip 3 with the support substrate is mounted on the wiring substrate 18 and then the support substrate. By removing the 13 layers by grinding, the handling property of the semiconductor chip 3 can be improved as in the first embodiment, and the surface load is applied to the thinned semiconductor wafer 2 when forming the layer of the support substrate 13. Since it does not take up, formation with less damage is possible.

以上、本発明者によってなされた発明を上記の実施例に基づき具体的に説明したが、本発明は上記の実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   The invention made by the present inventor has been specifically described based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

例えば、上記の実施例では、半導体チップを２段に積層する場合について説明したが、３段以上に積層するように構成しても何ら構わない。   For example, in the above-described embodiment, the case where the semiconductor chips are stacked in two stages has been described. However, the semiconductor chips may be stacked in three or more stages.

また、上記の実施例では、同一サイズのメモリチップを積層した場合について説明したが、異なるサイズの半導体チップを積層する場合に適用しても何ら構わない。   In the above embodiment, the case where the same size memory chips are stacked has been described. However, the present invention may be applied to the case where different size semiconductor chips are stacked.

さらに、上記の実施例では、ＳｎＡｇメッキが形成された裏面側に支持基板を搭載し、ウエハサポート部材から支持基板に半導体ウエハを移し替えるように構成したが、ＳｎＡｇメッキがなく、ボンディングツールへのＳｎＡｇメッキの付着の恐れがない半導体ウエハの場合には、ウエハサポート部材を支持基板として、半導体ウエハと共に切断し、積層体を形成するように構成しても何ら構わない。   Further, in the above embodiment, the support substrate is mounted on the back side where the SnAg plating is formed, and the semiconductor wafer is transferred from the wafer support member to the support substrate. However, there is no SnAg plating, In the case of a semiconductor wafer that does not have the risk of SnAg plating adhesion, the wafer support member may be cut as a support substrate together with the semiconductor wafer to form a laminated body.

１ ・・・ 半導体装置
２ ・・・ 半導体ウエハ
３ ・・・ 支持基板付半導体チップ（積層体）
４ ・・・ 半導体チップ
５ ・・・ チップ積層体
６ ・・・ シリコン基板
７ ・・・ 貫通電極
８ ・・・ 表面側バンプ電極
９ ・・・ 導体層
１０ ・・・ 裏面側バンプ電極
１１ ・・・ ウエハサポート部材（支持板）
１２ ・・・ 第１接着層
１３ ・・・ 支持基板（支持板）
１４ ・・・ 第２接着層
１５ ・・・ ダイシングテープ
１６ ・・・ ダイシングライン
１７ ・・・ ダイシングライン
１８ ・・・ 配線基板
１９ ・・・ 製品形成部
２０ ・・・ ランド
２１ ・・・ 接続パッド
２２ ・・・ 配線
２３ ・・・ アンダーフィル材
２４ ・・・ 封止樹脂
２５ ・・・ 金属ボール
２６ ・・・ 回路形成面（表面） DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor wafer 3 ... Semiconductor chip with support substrate (laminated body)
DESCRIPTION OF SYMBOLS 4 ... Semiconductor chip 5 ... Chip laminated body 6 ... Silicon substrate 7 ... Through electrode 8 ... Front side bump electrode 9 ... Conductive layer 10 ... Back side bump electrode 11 ...・ Wafer support member (support plate)
12: First adhesive layer 13: Support substrate (support plate)
DESCRIPTION OF SYMBOLS 14 ... 2nd contact bonding layer 15 ... Dicing tape 16 ... Dicing line 17 ... Dicing line 18 ... Wiring board 19 ... Product formation part 20 ... Land 21 ... Connection pad 22 ... Wiring 23 ... Underfill material 24 ... Sealing resin 25 ... Metal ball 26 ... Circuit forming surface (surface)

Claims (10)

ダイシングラインによって区画された複数の半導体チップを含む半導体ウエハを準備する第１の工程と、
前記半導体ウエハに支持板を付着する第２の工程と、
前記半導体ウエハおよび前記支持板をダイシングラインに沿って切断し、前記半導体チップおよび分割された前記支持板からなる積層体を形成する第３の工程と、
前記積層体を配線基板に搭載し、前記積層体の半導体チップおよび前記配線基板を電気的に接続する第４の工程とを有することを特徴とする半導体装置の製造方法。 A first step of preparing a semiconductor wafer including a plurality of semiconductor chips partitioned by a dicing line;
A second step of attaching a support plate to the semiconductor wafer;
A third step of cutting the semiconductor wafer and the support plate along a dicing line to form a laminate including the semiconductor chip and the divided support plate;
A method for manufacturing a semiconductor device, comprising: mounting the stacked body on a wiring board; and electrically connecting the semiconductor chip of the stacked body and the wiring board. 前記第１の工程において準備される前記半導体ウエハの前記支持板を付着した側の一方面には、前記半導体ウエハの外部に露出するバンプ電極が設けられており、
前記バンプ電極の外面には、ＳｎＡｇメッキ層が形成されていることを特徴とする請求項１に記載の半導体装置の製造方法。 A bump electrode exposed to the outside of the semiconductor wafer is provided on one surface of the semiconductor wafer prepared in the first step on the side where the support plate is attached,
The method for manufacturing a semiconductor device according to claim 1, wherein a SnAg plating layer is formed on an outer surface of the bump electrode. 前記第１の工程において準備される前記半導体ウエハには、前記半導体ウエハの他方面側に配置されたバンプ電極と、前記半導体ウエハを貫通し前記一方面側のバンプ電極および前記他方面側のバンプ電極の間を接続する導体層とが設けられていることを特徴とする請求項２に記載の半導体装置の製造方法。   The semiconductor wafer prepared in the first step includes a bump electrode disposed on the other surface side of the semiconductor wafer, a bump electrode on the one surface side and a bump on the other surface side that penetrates the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 2, further comprising a conductor layer that connects the electrodes. 前記第４の工程は、前記積層体を前記配線基板に搭載する工程と、前記積層体の半導体チップおよび前記配線基板を電気的に接続する工程と、前記積層体から支持板を除去する工程と、前記支持板を除去された半導体チップ上に他の積層体を搭載する工程とを含むことを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体装置の製造方法。   The fourth step includes a step of mounting the laminate on the wiring substrate, a step of electrically connecting the semiconductor chip of the laminate and the wiring substrate, and a step of removing a support plate from the laminate. 4. The method of manufacturing a semiconductor device according to claim 1, further comprising: mounting another stacked body on the semiconductor chip from which the support plate has been removed. 前記第１の工程において準備される前記半導体ウエハには、前記支持板を付着した一方面とは反対側の他方面に、他の支持板が付着されていることを特徴とする請求項１乃至請求項４のいずれか１項に記載の半導体装置の製造方法。   2. The semiconductor wafer prepared in the first step has another support plate attached to the other side opposite to the one side to which the support plate is attached. The manufacturing method of the semiconductor device of any one of Claim 4. 前記他方面側の支持板は、第１接着層を介して前記半導体ウエハに付着され、
前記一方面側の支持板は、第２接着層を介して前記半導体ウエハに付着されることを特徴とする請求項５に記載の半導体装置の製造方法。 The support plate on the other side is attached to the semiconductor wafer via a first adhesive layer,
6. The method of manufacturing a semiconductor device according to claim 5, wherein the one side support plate is attached to the semiconductor wafer via a second adhesive layer. 前記第１接着層および第２接着層は、ＵＶ硬化型の接着材からそれぞれ成り、
前記第１接着層の接着材と前記第２接着層の接着材とは、互いに異なるＵＶ硬化特性を有することを特徴とする請求項６に記載の半導体装置の製造方法。 The first adhesive layer and the second adhesive layer are each made of a UV curable adhesive,
The method for manufacturing a semiconductor device according to claim 6, wherein the adhesive of the first adhesive layer and the adhesive of the second adhesive layer have different UV curing characteristics. 前記第３の工程において、前記支持板にダイシングテープを貼り付けた状態で、前記半導体ウエハおよび前記支持板をダイシングラインに沿って切断することを特徴とする請求項１乃至請求項７のいずれか１項に記載の半導体装置の製造方法。   The said 3rd process WHEREIN: The said semiconductor wafer and the said support plate are cut | disconnected along a dicing line in the state which affixed the dicing tape on the said support plate, The any one of Claim 1 thru | or 7 characterized by the above-mentioned. 2. A method for manufacturing a semiconductor device according to item 1. 前記配線基板および前記配線基板に搭載された半導体チップをモールドする第５の工程を更に有し、
前記第５の工程において、前記配線基板に搭載された半導体チップのうち最上段に位置する半導体チップには、前記支持板が付着された状態で残されていることを特徴とする請求項１乃至請求項８のいずれか１項に記載の半導体装置の製造方法。 A fifth step of molding the wiring substrate and a semiconductor chip mounted on the wiring substrate;
6. The fifth step, wherein the support plate is left attached to a semiconductor chip located at the uppermost stage among the semiconductor chips mounted on the wiring board. The method for manufacturing a semiconductor device according to claim 8. 前記支持板は、放熱特性の高い材料から成ることを特徴とする請求項９に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 9, wherein the support plate is made of a material having high heat dissipation characteristics.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015119109A (en) * 2013-12-19 2015-06-25 国立大学法人東京工業大学 Semiconductor device manufacturing method
JP2019125769A (en) * 2018-01-11 2019-07-25 日立化成株式会社 Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015119109A (en) * 2013-12-19 2015-06-25 国立大学法人東京工業大学 Semiconductor device manufacturing method
JP2019125769A (en) * 2018-01-11 2019-07-25 日立化成株式会社 Method of manufacturing semiconductor device

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