CN102623359A - Semiconductor encapsulation structure and manufacturing method thereof - Google Patents

Semiconductor encapsulation structure and manufacturing method thereof Download PDF

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Publication number
CN102623359A
CN102623359A CN2012101121470A CN201210112147A CN102623359A CN 102623359 A CN102623359 A CN 102623359A CN 2012101121470 A CN2012101121470 A CN 2012101121470A CN 201210112147 A CN201210112147 A CN 201210112147A CN 102623359 A CN102623359 A CN 102623359A
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China
Prior art keywords
substrate
chip
adhesive material
conducting element
film
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Pending
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CN2012101121470A
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Chinese (zh)
Inventor
洪嘉临
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN2012101121470A priority Critical patent/CN102623359A/en
Publication of CN102623359A publication Critical patent/CN102623359A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor encapsulation structure and a manufacturing method thereof. The manufacturing method is characterized in that a mould covers on electric conduction elements, an inner surface of the mould is provided with a thin film, the thin film is contact with one surface of a chip and accommodates part of the electric conduction elements, and an encapsulation gum material covers a first surface of a substrate, the chip and part of the electric conduction elements and exposes the surface of the chip. Because the thin film is used to contact the surface of the chip and accommodate part of the electric conduction elements, the part of the electric conduction elements and the surface of the chip are exposed, so that the known step of removing partial encapsulation gum material is omitted, residual gum is unnecessary to remove, and the pollution to the surface of a solder ball cannot be caused. Therefore, the advantages of simplifying a process, shortening the process time and reducing the manufacturing cost are achieved, and the mass production is facilitated.

Description

Semiconductor package and manufacturing approach thereof
Technical field
The present invention is about a kind of semiconductor package and manufacturing approach thereof.
Background technology
(package on package PoP) comprises encapsulating structure on the encapsulating structure and to known stacking type encapsulation laminated construction.Soldered ball and last encapsulating structure that known encapsulating structure utilization down exposes electrically connect, so must remove the part adhesive material to soldered ball is exposed, in order to engaging with last encapsulating structure.Removing the part adhesive material at present has dual mode, and first kind is to utilize cutting mode to remove the part adhesive material, and another kind of mode is to utilize laser to burn the mode of melting to remove the part adhesive material.These two kinds of modes except in the required precision of board be very high, after removing the part adhesive material, except meeting causes cull; Also can cause the pollution on soldered ball surface; In order to remove above two kinds of extraneous contaminations, must to increase by one and remove technology, and then cost is risen.
Summary of the invention
The present invention provides a kind of manufacturing approach of semiconductor package.At first, a substrate is provided, this substrate has a first surface and a second surface.Then, form several conducting elements this first surface in this substrate.This first surface of one chip to this substrate is set again, and this chip is electrically connected to this substrate.Then, cover a mould on these conducting elements, an inner surface of this mould has a film, a surface of this this chip of film contact, and the part of ccontaining these conducting elements of this film.Then, form an adhesive material first surface, this chip and these conducting elements of part, and expose this surface of this chip to coat this substrate.
The present invention provides a kind of semiconductor package in addition, comprising: a substrate, a chip, several conducting elements and an adhesive material.This substrate has a first surface and a second surface.This chip is arranged at this first surface of this substrate, and is electrically connected to this substrate.These conducting elements are arranged at this first surface of this substrate.This adhesive material utilizes a mould to irritate mold technique and forms; One inner surface of this mould has a film; One surface of this this chip of film contact; And the part of ccontaining these conducting elements of this film, this adhesive material coat this first surface, this chip and these conducting elements of part of this substrate, and expose this surface of this chip.
The present invention provides a kind of semiconductor package again, comprising: chip and one second adhesive material on a substrate, a chip, several conducting elements, one first adhesive material, the upper substrate.This substrate has a first surface and a second surface.This chip is arranged to this first surface of this substrate, and is electrically connected to this substrate.These conducting elements are arranged at this first surface of this substrate.This first adhesive material utilizes a mould to irritate mold technique and forms; One inner surface of this mould has a film; One surface of this this chip of film contact; And the part of ccontaining these conducting elements of this film, this first adhesive material coat this first surface, this chip and these conducting elements of part of this substrate, and expose this surface of this chip.This upper substrate has a first surface and a second surface, and this second surface electrically connects these conducting elements.Should go up chip and be arranged to this first surface of this upper substrate, and be electrically connected to this upper substrate.This second adhesive material coats this first surface of this upper substrate and should go up chip.
Owing to utilize this surface of this this chip of film contact; And the part of ccontaining these conducting elements of this film, so that this surface exposure of these conducting elements of part and this chip, so must knownly not remove the step of part adhesive material; And must not remove cull, can not cause the pollution on soldered ball surface yet.Therefore can simplify technology, shorten the process time and reduce manufacturing cost, be beneficial to volume production.
Description of drawings
Fig. 1 shows the sketch map of an embodiment of semiconductor package of the present invention;
Fig. 2 to Fig. 8 shows the sketch map of an embodiment of the manufacturing approach of semiconductor package of the present invention;
Fig. 9 shows the sketch map of another embodiment of semiconductor package of the present invention;
Figure 10 shows the sketch map of another embodiment of the last encapsulating structure of semiconductor package of the present invention;
Figure 11 shows the sketch map of an embodiment again of semiconductor package of the present invention;
Figure 12 shows the sketch map of the another embodiment of semiconductor package of the present invention; And
Figure 13 is the conducting element of Figure 12 and the local enlarged diagram of part of groove.
Embodiment
With reference to figure 1, show the sketch map of an embodiment of semiconductor package of the present invention.Semiconductor package 10 of the present invention comprises: chip 16 and one second adhesive material 17 on a substrate 11, several conducting elements 12, a chip 13, one first adhesive material 14, the upper substrate 15.In the present embodiment, semiconductor package 10 of the present invention for stacking type encapsulation laminated construction (package on package, PoP).
This substrate 11 has a first surface 111 and a second surface 112, and this second surface 112 is with respect to this first surface 111.These conducting elements 12 are arranged at this first surface 111 of this substrate 11.This chip 13 is arranged to this first surface 111 of this substrate 11, and is electrically connected to this substrate 11.In the present embodiment, utilize several projections 131, be arranged at 13 of this substrate 11 and this chips, electrically connect this substrate 11 and this chip 13; And utilize a primer 132, be arranged at 13 of this substrate 11 and this chips, coat these projections 131.
These conducting elements 12 are arranged at around this chip 13, and a summit of these conducting elements 12 with respect to the height of this first surface of this substrate greater than a surface 133 of this chip 13 height with respect to this first surface of this substrate.This first adhesive material 14 coats this first surface 111, this chip 13 and these conducting elements 12 of part of this substrate 11, and exposes this surface 133 of this chip 13.
This upper substrate 15 has a first surface 151 and a second surface 152, and this second surface 152 electrically connects these conducting elements 12.Should go up chip 16 and be arranged to this first surface 151 of this upper substrate 15, and be electrically connected to this upper substrate 15.This second adhesive material 17 coats this first surface 151 of this upper substrate 15 and should go up chip 16.
Referring to figs. 2 to Fig. 8, the sketch map of an embodiment of the manufacturing approach of demonstration semiconductor package of the present invention.With reference to figure 2, a substrate 11 is provided, this substrate 11 has a first surface 111 and a second surface 112.Form several conducting elements 12 this first surface 111 again in this substrate 11.In one embodiment, these conducting elements 12 can be soldered ball.
With reference to figure 3, this first surface 111 of a chip 13 to this substrate 11 is set, and this chip 13 is electrically connected to this substrate.In the present embodiment, utilize several projections 131, be arranged at 13 of this substrate 11 and this chips, electrically connect this substrate 11 and this chip 13.With reference to figure 4, this manufacturing approach of the present invention comprises in addition and forms a primer 132 in 13 of this substrate 11 and this chips, and coats the step of these projections 131.
With reference to figure 5, cover a mould 21 on this first surface 111 of this substrate 11, an inner surface of this mould 21 has a film 22; One surface 133 of these film 22 these chips 13 of contact; And the part of these film 22 ccontaining these conducting elements 12, that is this film 22 covered to 12 last times of these conducting elements; Receive these conducting elements 12 to push and be absorbed in, with the part upper end of ccontaining these conducting elements 12.
With reference to figure 6, inject first adhesive material 14 in this mould 21, to form first surface 111, this chip 13 and these conducting elements 12 of part that first adhesive material 14 coats this substrate 11.And do not coat this surface 133 of this chip 13 because of these surface 133, the first adhesive materials 14 of these film 22 these chips 13 of contact.Remove this mould 21 and this film 22 again; And this surface 133 of this chip 13 be exposed to this first adhesive material 14 outside; And this surface 133 of this chip 13 roughly with a flush of this first adhesive material 14, with make semiconductor encapsulating structure 30 of the present invention, as shown in Figure 7.The height of these conducting elements 12 of the part that appears in the present embodiment, is the 20%-70% of these conducting element 12 whole heights.That is this adhesive material coats the 30%-80% of these conducting element whole heights.
This semiconductor package 30 of the present invention can be the following encapsulating structure of the invention described above semiconductor package 10 (Fig. 1), and its structure is no longer narrated at this as stated.Owing to utilize this surface 133 of these film 22 these chips 13 of contact; And the part of these film 22 ccontaining these conducting elements 12; So that this surface 133 of these conducting elements 12 of part and this chip 13 exposes; So must knownly not remove the step of part adhesive material, and must not remove cull, can not cause the pollution on soldered ball surface yet.Therefore can simplify technology, shorten the process time and reduce manufacturing cost, be beneficial to volume production.
With reference to figure 8, the manufacturing approach of semiconductor package of the present invention comprises the step that encapsulating structure 40 on is provided in addition.Encapsulating structure 40 be should go up and chip 16, one second adhesive material 17 and several bond pads 41 on the upper substrate 15, comprised.This upper substrate 15 has a first surface 151 and a second surface 152, and chip 16 electrically connects this first surface 151 of this upper substrate 15 on this, and these bond pads 41 are arranged at this second surface 152 of this upper substrate 15.
These bond pads 41 that stack encapsulating structure 40 on this again are on these conducting elements 12.Then, carry out reflow (Reflow) step, make these bond pads 41 and these conducting elements 12 electrically connect, with make this semiconductor package 10 of the present invention, as shown in Figure 1.And form several first soldered balls 18 this second surface 112 in addition, to electrically connect with outer member in this substrate 11.
With reference to figure 9, show the sketch map of another embodiment of semiconductor package of the present invention.Be that with semiconductor package 10 differences of the present invention semiconductor package 50 of the present invention does not have primer 132, and utilize first adhesive material 14 to coat these projections 131.Semiconductor package 50 of the present invention is given identical label with semiconductor package 10 components identical of the present invention, and no longer narration.
With reference to Figure 10, the sketch map of another embodiment of the last encapsulating structure of demonstration semiconductor package of the present invention.The encapsulating structure 70 of should going up of semiconductor package of the present invention comprises on the upper substrate 15, a chip 16, one second adhesive material 17, several bond pads 71 and several second soldered balls 72.Be that with encapsulating structure 40 differences that should go up of above-mentioned Fig. 8 these second soldered balls 72 are arranged at these bond pads 71.
With reference to Figure 11, show the sketch map of an embodiment again of semiconductor package of the present invention.Be that with semiconductor package 10 differences of the present invention semiconductor package 80 of the present invention comprises the upward encapsulating structure 70 of Figure 10, so these second soldered balls 72 electrically connect with these conducting elements 12.Semiconductor package 80 of the present invention is given identical label with semiconductor package 10 components identical of the present invention, and no longer narration.
With reference to Figure 12, show the sketch map of the another embodiment of semiconductor package of the present invention; Figure 13 is the conducting element of Figure 12 and the local enlarged diagram of part of groove.Semiconductor package 60 of the present invention can be the following encapsulating structure of the invention described above semiconductor package 10 (Fig. 1); Be that with the invention described above semiconductor package 30 differences semiconductor package 60 of the present invention has several grooves 61, be formed at first adhesive material 14 on every side of these conducting elements 12.In the present embodiment; Laser capable of using burns the mode of melting and removes first adhesive material 14 around these conducting elements 12; To form these grooves 61, make when carrying out reflow (Reflow) step, these bond pads 41 are electrically connected with these conducting elements 12 smoothly.Wherein, the peripheral width A of these grooves 61 is greater than the diameter of these conducting elements 12 about 20% to 50%; And the depth B of these grooves 61 be about these conducting elements 12 diameter 5% to 50%.
Only the foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in this technological personage.Interest field of the present invention should be listed like claims.

Claims (9)

1. the manufacturing approach of a semiconductor package may further comprise the steps:
(a) substrate is provided, this substrate has a first surface and a second surface;
(b) form several conducting elements this first surface in this substrate;
(c) this first surface of a chip to this substrate is set, and this chip is electrically connected to this substrate;
(d) cover a mould on this substrate, an inner surface of this mould has a film, a surface of this this chip of film contact, and the part of the ccontaining said conducting element of this film; And
(e) form this first surface, this chip and the part said conducting element of an adhesive material, and expose this surface of this chip to coat this substrate.
2. method as claimed in claim 1, the adhesive material on every side that wherein is included in said conducting element after this step (e) in addition forms the step of groove.
3. method as claimed in claim 1, wherein this step (e) more comprises afterwards:
(f) encapsulating structure on is provided; Encapsulating structure be should go up and chip and several bond pads on the upper substrate, comprised; This upper substrate has a first surface and a second surface; Should go up this first surface that chip electrically connects this upper substrate, said bond pad is arranged at this second surface of this upper substrate;
(g) stack said bond pad on said conducting element; And
(h) carry out reflow, make said bond pad and said conducting element electrically connect.
4. semiconductor package comprises:
One substrate has a first surface and a second surface;
One chip is arranged at this first surface of this substrate, and is electrically connected to this substrate;
Several conducting elements are arranged at this first surface of this substrate; And
One adhesive material; Utilizing a mould to irritate mold technique forms; One inner surface of this mould has a film, a surface of this this chip of film contact, and the part of the ccontaining said conducting element of this film; This adhesive material coats this first surface, this chip and the said conducting element of part of this substrate, and exposes this surface of this chip.
5. semiconductor package as claimed in claim 4, other comprises several grooves, is formed at the adhesive material on every side of said conducting element.
6. semiconductor package as claimed in claim 5, the peripheral width of wherein said groove is greater than the diameter of said conducting element about 20% to 50%; And the degree of depth of said groove be about said conducting element diameter 5% to 50%.
7. semiconductor package as claimed in claim 4, this adhesive material coats the 30%-80% of said conducting element whole height.
8. stacking type encapsulating structure comprises:
One substrate has a first surface and a second surface;
One chip is arranged to this first surface of this substrate, and is electrically connected to this substrate;
Several conducting elements are arranged at this first surface of this substrate;
One first adhesive material; Utilizing a mould to irritate mold technique forms; One inner surface of this mould has a film, a surface of this this chip of film contact, and the part of the ccontaining said conducting element of this film; This first adhesive material coats this first surface, this chip and the said conducting element of part of this substrate, and exposes this surface of this chip;
One upper substrate have a first surface and a second surface, and this second surface electrically connects said conducting element;
Chip on one is arranged to this first surface of this upper substrate, and is electrically connected to this upper substrate; And
One second adhesive material coats this first surface of this upper substrate and should go up chip.
9. stacking type encapsulating structure as claimed in claim 8, other comprises several grooves, is formed at the adhesive material on every side of said conducting element.
CN2012101121470A 2012-04-17 2012-04-17 Semiconductor encapsulation structure and manufacturing method thereof Pending CN102623359A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579207A (en) * 2013-11-07 2014-02-12 华进半导体封装先导技术研发中心有限公司 Stacked packaging device and manufacturing method thereof
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CN104658933A (en) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 POP structure applying lamination process and preparation method thereof
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CN104658933A (en) * 2014-12-30 2015-05-27 华天科技（西安）有限公司 POP structure applying lamination process and preparation method thereof

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