CN102456677A - Packaging structure for ball grid array and manufacturing method for same - Google Patents
Packaging structure for ball grid array and manufacturing method for same Download PDFInfo
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- CN102456677A CN102456677A CN2010105249953A CN201010524995A CN102456677A CN 102456677 A CN102456677 A CN 102456677A CN 2010105249953 A CN2010105249953 A CN 2010105249953A CN 201010524995 A CN201010524995 A CN 201010524995A CN 102456677 A CN102456677 A CN 102456677A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a packaging structure for a multi-chip ball grid array and a manufacturing method for the same, wherein the packaging structure for a ball grid array comprises a substrate; at least two chips fixed on the upper surface of the substrate and the lower surface of the substrate respectively, wherein a signal end is formed on each chip; pad parts disposed on the upper surface and the lower surface of the substrate and provided with through holes penetrating through the substrate in a thickness direction, wherein the pad parts form electric connections with the signal ends via leads; conducting parts which are conducting pins inserted and fixed in the through holes; and plastic packaging parts for protecting the substrate, the conducting parts and the chips. According to the packaging structure for a multi-chip ball grid array and the manufacturing method for the same disclosed by the invention, the generation for a cantilever in a multi-chip packaging can be reduced, the manufacturing technique can be simplified, and a warping phenomenon in structure can be prevented.
Description
Technical field
The present invention relates to ball grid array package structure and manufacturing approach thereof; Relate in particular to through upper surface and lower surface and chip is set and draws internal circuit, realize the ball grid array package structure and the manufacturing approach thereof of the encapsulation of multilayer chiop thus through conductive part at substrate.
Background technology
BGA (BGA) encapsulation technology is a kind of surface attaching type encapsulation, and it replaces traditional lead frame through producing spherical salient point (ball bump) at the back side of substrate by array way, makes that the integrated level of semiconductor device is higher, performance is better.The BGA encapsulation technology can increase significantly device the I/O number of pins, reduce solder pad space length; And then dwindle packaging part size, save the footprint of encapsulation, thereby make high density, the high-performance of PC chipset, microprocessor etc., the microminiaturization of many pin package device become possibility.
Yet along with the development of technology, electronic product need be realized high-velocity electrons system, miniaturization, multifunction, high reliability and high-performance, and the density that causes encapsulating constantly increases, thereby the multilayer chiop packaged type occurred.
The encapsulation of multicore sheet is on high-density multi-layered interconnect substrates; The a plurality of chip laminates that adopt the microwelding packaging technology will constitute electronic circuit assemble; Form the microelectronic product of high density, high-performance, high reliability, can adapt to short, little, light, the thin and high speed of contemporary electronic systems, high-performance, high reliability.
Fig. 1 is the sketch map of existing multilayer chiop encapsulating structure.Can know that by Fig. 1 existing multilayer chiop encapsulating structure comprises substrate 101, first chip 102, second chip 103, first adhesive linkage 104, second adhesive linkage 105, metal wire 106, soldered ball 107 and Plastic Division 108.Said first chip 102 is arranged at the upper surface of substrate 101 through first adhesive linkage 104, and second chip 103 through second adhesive linkage 105 be arranged at first chip 102 above.The signal end of first, second chip 102,103 is connected to the welding disk of substrate 101 through metal wire 106, and the signal end of said thus first, second chip 102,103 extends to the outside through said substrate 101, be connected thereby can form with external circuit.Externalities is avoided receiving in order to protect said chip 102,103 and metal wire 106, substrate 101 in said Plastic Division 108.
But aforesaid existing multilayer chiop encapsulating structure has following problem:
1) when the size of a plurality of chips inconsistent; And when the size of chip that is arranged at upside is bigger, can produce cantilever design, thereby cause relatively difficulty of lead key closing process; Particularly serious under the very big situation of size that cantilever stretches out, therefore this technology is prone to be subject to the size of chip;
2) in existing processes; At first will then carry out lead key closing process to this first chip with first die bonding in substrate, the upside at said first chip is provided with second chip then; Again second chip is carried out lead key closing process afterwards; Therefore process need come and go and carry out, and program is complicated, and the time of consumption is longer;
3) because chip only is arranged in the one side of substrate, thus encapsulating structure be prone to produce structure warpage, especially overall dimensions thin the time more very.
Summary of the invention
The present invention proposes in order to address the above problem; Its purpose is to provide a kind of ball grid array package structure and manufacturing approach thereof; Through a plurality of chips being pasted on the upper surface and the lower surface of substrate respectively; Can avoid cantilever design effectively thus, and can simplify technology, and prevent that encapsulating structure from producing the phenomenon of warpage.
For the attainment of one's purpose, according to an aspect of the present invention, a kind of ball grid array package structure is provided, comprises: substrate; At least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate, and the top signal end that is formed with respectively of each chip; Welding disk is arranged at the upper surface and the lower surface of said substrate, and has the through hole that runs through said substrate at thickness direction, and is electrically connected with said signal end formation through lead-in wire; Conductive part, it is a conductive pin, inserts and is fixed in said through hole; The Plastic Division is in order to protect said substrate, said conductive part and said chip.
Preferably, said conductive pin is perpendicular to said substrate.
And, according to an aspect of the present invention, a kind of method that is used to make said ball grid array package structure is provided, may further comprise the steps: at least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate; Said conductive pin is arranged at the through hole of said welding disk; To the chip of the upper surface that is adhered to said substrate respectively and the lower surface bonding that goes between; To the top of said substrate and followingly carry out plastic packaging respectively, and make the bottom of said conductive pin be exposed to the surface of Plastic Division; Soldered ball is implanted in bottom to being exposed to the surperficial said conductive pin in said Plastic Division.
For the attainment of one's purpose, according to a further aspect in the invention, a kind of ball grid array package structure is provided, comprises: substrate; At least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate, and the top signal end that is formed with respectively of each chip; The Plastic Division have first Plastic Division that is arranged at below the said substrate and the second top Plastic Division that is arranged at said substrate, and first Plastic Division is formed with through hole; Welding disk is arranged at the upper surface of said substrate and at least one side in the lower surface, and possesses the through hole along said substrate thickness direction, and this through hole is communicated with said through hole; Conductive part forms through at said through hole electric conducting material being set, so that said first welding disk and second welding disk are extended to the outside.
Preferably, said first welding disk forms with said through hole through the through hole that is arranged at said substrate and is connected.
And, according to a further aspect in the invention, a kind of method of ball grid array package structure is provided, may further comprise the steps: chip is individually fixed in the upper surface of said substrate and the lower surface of said substrate; To the chip of the upper surface that is adhered to said substrate respectively and the lower surface bonding that goes between; To the following and top plastic packaging that carries out respectively of said substrate, to form first Plastic Division and second Plastic Division; Hole in one of them Plastic Division in said first Plastic Division and second Plastic Division, to form through hole; In the through hole of said through hole and said substrate, electric conducting material is set and forms conductive part, extend to the outside with welding disk with said substrate; Said conductive part is implanted soldered ball.
Preferably, said electric conducting material is a copper.
According to the present invention, through both sides chip is set, and carries out lead key closing process simultaneously, thereby can effectively reduce the generation of the cantilever in the multicore sheet encapsulation, and can improve the efficient of lead-in wire bonding at substrate.And, owing to chip is set, can prevent the warping phenomenon of thin encapsulating structure thus in the both sides of substrate.
Description of drawings
Fig. 1 is the sketch map of existing multilayer chiop encapsulating structure;
Fig. 2 is the sketch map of multichip packaging structure according to an embodiment of the invention;
Fig. 3 is the flow chart according to a manufacturing process of multichip packaging structure of the present invention;
Fig. 4 is the flow chart according to another manufacturing process of multichip packaging structure of the present invention.
Main symbol description: 201 is substrate, and 202 is first chip, and 203 is second chip, and 204 is first adhesive linkage, and 205 is second adhesive linkage, and 206 is metal wire, and 207 is soldered ball, and 208 is first Plastic Division, and 209 is conductive part, and 210 is second Plastic Division.
Embodiment
Below, specify ball grid array package structure and manufacturing approach thereof according to an embodiment of the invention with reference to accompanying drawing.Yet the present invention can implement with many different modes, and should not be understood that to be limited to following embodiment.In the accompanying drawings, for clarity, exaggerative size is represented, and is used identical label to represent identical parts in the different drawings.
Fig. 2 is the sketch map of multichip packaging structure according to an embodiment of the invention; Fig. 3 is the flow chart according to a manufacturing process of multichip packaging structure of the present invention; Fig. 4 is the flow chart according to another manufacturing process of multichip packaging structure of the present invention.
Can know that by figure multicore sheet ball grid array package structure comprises substrate 201, first chip 202, second chip 203, first adhesive linkage 204, second adhesive linkage 205, metal wire 206, soldered ball 207, first Plastic Division 208, conductive part 209, second Plastic Division 210 according to an embodiment of the invention.Said substrate 201 is a multi-layer sheet, and surface and lower surface all can be provided with chip above that.In the present embodiment, through second adhesive linkage 205 second chip 203 is set, through first adhesive linkage 204 first chip 202 is set at the lower surface of said substrate 201 at the upper surface of said substrate 201.Said first adhesive linkage 202 and second adhesive linkage 204 use the heat-conducting type bonded adhesives and form, to guarantee heat dispersion.Said metal wire 206 preferably adopts gold thread in order to the signal end that connects each chip and the welding disk of said substrate 201.
Said welding disk can be arranged at the upper surface of said substrate 201 and at least one side in the lower surface.And said welding disk can comprise the through hole that runs through substrate along the thickness direction of said substrate 201.Said conductive part 209 can adopt conductive pin, also can adopt by through electric conducting material being filled in the conductive pole that the through hole that forms on said first Plastic Division 208 and the through hole on the said substrate constitute.When said conductive part 209 adopted conductive pin, this conductive pin inserted and is fixed in the through hole of said substrate 201, and said conductive pin forms vertical with substrate 201.When said conductive part 209 adopts the conductive pole that is made up of electric conducting material; Need when forming first Plastic Division, reserve through hole; And this through hole should be communicated with the through hole of substrate, forms conductive pole through the through hole of electric conducting material being inserted on said through hole and the said substrate 201 thus.Preferably, said electric conducting material is a copper.Said soldered ball 207 is formed on an end or the end of conductive pole of the conductive pin of the lower surface that is exposed to said first Plastic Division 208, thereby the signal end of chip is extended to the outside of encapsulating structure.
Below, in conjunction with Fig. 3 and Fig. 4 the manufacturing process flow according to multichip packaging structure of the present invention is carried out detailed explanation.
As shown in Figure 3, following according to a manufacturing process of multichip packaging structure of the present invention: at first, shown in a of Fig. 3, at lower surface and upper surface bonding first chip of difference and second chip of substrate.At this moment, utilize first adhesive linkage and the second adhesive linkage fixed chip.Then, shown in the b of Fig. 3, respectively to the upper surface of said substrate and the lower surface bonding that goes between.At this moment, at first, then substrate overturn is come, to the other one side bonding that goes between to the bonding that goes between of the wherein one side in the upper surface of substrate or the lower surface.Thus, second chip is set after the bonding again, to the go between technological process of bonding of second chip, can saves time significantly again, improve operating efficiency with respect to prior art first chip is gone between.Then, shown in the c of Fig. 3, upper surface and the lower surface to said substrate carries out plastic packaging respectively, with protection chip and metal wire etc.Then, shown in the d of Fig. 3, form through hole in first Plastic Division.At this moment, the method that forms through hole has two kinds, wherein a kind ofly for the coordinate information according to the through hole of substrate is holed in first Plastic Division, and through hole is communicated with the through hole of substrate; Another kind is when forming first Plastic Division, directly to form the through hole that is communicated with the through hole of substrate through mould.At this moment, said through hole is vertical with substrate at the thickness direction of first Plastic Division, and is communicated with the through hole of the thickness direction of said substrate.And, for fear of when boring because of the error damaged substrate, should make the diameter of the diameter of through hole greater than through hole.Then, shown in the e of Fig. 3, at said through hole and the inner filled conductive material of through hole, to form conductive pole.This moment, said electric conducting material was a copper.At last, shown in the f of Fig. 3, the conductive pole that is exposed to the said first Plastic Division lower surface is implanted soldered ball.
As shown in Figure 4, following according to another manufacturing process of multichip packaging structure of the present invention: at first, shown in the A of Fig. 4, at lower surface and upper surface bonding first chip of difference and second chip of substrate.At this moment, utilize first adhesive linkage and the second adhesive linkage fixed chip.Then, shown in the B of Fig. 4, in the through hole of substrate, conductive pin is set.At this moment, conductive pin should be perpendicular to substrate.Then, shown in the C of Fig. 4, respectively to the chip of the upper surface of said substrate and the lower surface bonding that goes between.At this moment, at first, then substrate overturn is come, to the chip of the other one side bonding that goes between to the bonding that goes between of the wherein chip of one side in the upper surface of substrate or the lower surface.Thus, second chip is set after the bonding again, and, can saves time significantly, improve operating efficiency again to the go between technological process of bonding of second chip with respect to prior art first chip is gone between.Then, shown in the D of Fig. 4, below top the reaching of substrate, carry out plastic packaging respectively.At this moment, should make the bottom of said conductive pin be exposed to the surface of Plastic Division.At last, shown in the E of Fig. 4, implant soldered ball in the bottom of the conductive pin that is exposed to the surface, Plastic Division.
In above explanation, be that example describes a chip to be set respectively, but the present invention is not limited thereto at basic upper surface and lower surface, the present invention also is applicable to the packaging technology that plural chip is set respectively at basic upper surface and lower surface.
The invention is not restricted to the foregoing description, without departing from the present invention, can carry out various distortion and modification.
Claims (8)
1. ball grid array package structure is characterized in that comprising:
Substrate;
At least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate, and the top signal end that is formed with respectively of each chip;
Welding disk is arranged at the upper surface and the lower surface of said substrate, and has the through hole that runs through said substrate at thickness direction, and is electrically connected with said signal end formation through lead-in wire;
Conductive part, it is a conductive pin, inserts and is fixed in said through hole;
The Plastic Division is in order to protect said substrate, said conductive part and said chip.
2. according to the ball grid array package structure of claim 1, it is characterized in that said conductive pin is perpendicular to said substrate.
3. ball grid array package structure is characterized in that comprising:
Substrate;
At least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate, and the top signal end that is formed with respectively of each chip;
The Plastic Division have first Plastic Division that is arranged at below the said substrate and the second top Plastic Division that is arranged at said substrate, and first Plastic Division is formed with through hole;
Welding disk is arranged at the upper surface of said substrate and at least one side in the lower surface, and possesses the through hole along said substrate thickness direction, and this through hole is communicated with said through hole;
Conductive part forms through at said through hole electric conducting material being set, so that said first welding disk and second welding disk are extended to the outside.
4. according to the ball grid array package structure of claim 3, it is characterized in that said first welding disk is connected with said through hole formation through the through hole that is arranged at said substrate.
5. method that is used to make the ball grid array package structure of claim 1 is characterized in that may further comprise the steps:
At least two chips are individually fixed in the upper surface of said substrate and the lower surface of said substrate;
Said conductive pin is arranged at the through hole of said welding disk;
To the chip of the upper surface that is adhered to said substrate respectively and the lower surface bonding that goes between;
To the top of said substrate and followingly carry out plastic packaging respectively, and make the bottom of said conductive pin be exposed to the surface of Plastic Division;
Soldered ball is implanted in bottom to being exposed to the surperficial said conductive pin in said Plastic Division.
6. the method for ball grid array package structure according to claim 5 is characterized in that in the step of the through hole that said conductive pin is arranged at said weld part, making said conductive part perpendicular to said substrate.
7. method that is used to make the ball grid array package structure of claim 3 is characterized in that may further comprise the steps:
Chip is individually fixed in the upper surface of said substrate and the lower surface of said substrate;
To the chip of the upper surface that is adhered to said substrate respectively and the lower surface bonding that goes between;
To the following and top plastic packaging that carries out respectively of said substrate, to form first Plastic Division and second Plastic Division;
Hole in one of them Plastic Division in said first Plastic Division and the said Plastic Division, to form through hole;
In the through hole of said through hole and said substrate, electric conducting material is set and forms conductive part, extend to the outside with welding disk with said substrate;
Said conductive part is implanted soldered ball.
8. the method for ball grid array package structure according to claim 7 is characterized in that said electric conducting material is a copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105249953A CN102456677B (en) | 2010-10-27 | 2010-10-27 | Packaging structure for ball grid array and manufacturing method for same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105249953A CN102456677B (en) | 2010-10-27 | 2010-10-27 | Packaging structure for ball grid array and manufacturing method for same |
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| CN102456677A true CN102456677A (en) | 2012-05-16 |
| CN102456677B CN102456677B (en) | 2013-08-21 |
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