CN2370565Y - Stacking device for electronic element - Google Patents
Stacking device for electronic element Download PDFInfo
- Publication number
- CN2370565Y CN2370565Y CN99200739U CN99200739U CN2370565Y CN 2370565 Y CN2370565 Y CN 2370565Y CN 99200739 U CN99200739 U CN 99200739U CN 99200739 U CN99200739 U CN 99200739U CN 2370565 Y CN2370565 Y CN 2370565Y
- Authority
- CN
- China
- Prior art keywords
- electronic component
- substrate
- metal level
- hole
- electronic element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The utility model relates to an electronic element packaging device which saves conducting lines and transfers fast. An electronic element stacking device comprises a basal plate, an upper pit, a lower pit, an upper electronic element, a lower electronic element and conducting lines. The utility model is characterized in that a metal layer is arranged between the upper surface and the lower surface of the base. The upper pit penetrates from the upper surface to the metal layer and forms the bottom of the upper pit. The lower pit penetrates from the lower surface to the metal layer and forms the bottom of the lower pit. The upper electronic element is disposed on the metal layer at the bottom of the upper pit and covers a first sealing adhesive body. The lower electronic element is disposed on the metal layer at the bottom of the lower pit and covers a second sealing adhesive body. The utility model is used in electronic equipment.
Description
The utility model relates to the electronic package device.
Existing electronic package is as shown in Figure 1, 2: as Fig. 1, one substrate 110 comprises organic material layer 111, metal level 112, metal level 112 is positioned at organic material layer 111, and substrate 110 comprises 115 of upper surfaces 113, a lower surface 114, one holes in addition and is through to lower surface 114 from upper surface 113.One wafer 121 is positioned at directly over the substrate 110 upper surfaces 113 set holes 115, wafer 121 is connected the contact 123 of substrate 110 upper surfaces 113 by lead 122, the adhesive body 124 that pours into is sealed the entire wafer 121 that protrudes on substrate 110 upper surfaces 113, forms gas-tight seal.Hole 115 inwalls are provided with metal level 125, and metal level 125 is just touching the wafer 121 directly over being positioned at, and a Metal Ball 126 is welded in metal level 125 extensions of lower surface 114.Metal level 112 or the Metal Ball 126 of heat in metal level 125 conducts to substrate 110 that wafer 121 produces.Lower surface 114 covers an epoxy compounds 116, and epoxy compounds 116 is also filled in the metal level 125 of hand-hole 115.Because wafer 121 protruding placing on the substrate 110 make the increase of substrate 110 thickness and cause the wafer 121 and the spacing of contact 123 to increase, and cause lead 122 length to increase, and then the signal passing time is increased; In addition, lead 122 resistance also increase thereupon, signal transmission thereby weaken and slow down, and make lead 122 expense materials, easily impaired.As Fig. 2, a substrate 210 comprises organic substance 211 and metal level 212, and metal level 212 is positioned at organic material layer 211, and substrate 210 comprises a upper surface 215 and a lower surface 216 in addition; 213 in one hole is through to metal level 212 from upper surface 215, and metal level 212 a part of sheet metals 214 are filled in the hand-holes 213.One wafer 221 is positioned at directly over the substrate 210 upper surfaces 215 set holes 213, is connected to the contact 223 of upper surface 215 by lead 222, pours into adhesive body 224 and seals the entire wafer 221 that protrudes on the upper surface 215, and form gas-tight seal.Sheet metal 214 is just touching the wafer 221 directly over being positioned at, and the heat palpus sheet metal 214 that wafer 221 produces conducts to metal level 212 and dispels the heat.It causes a series of shortcoming also as above-mentioned.
The purpose of this utility model provides a kind of shortening electronic component and contact spacing, and conductor length and resistance thereof are reduced, and makes the fast electronic component stack device of signal transmission.
The purpose of this utility model is achieved in that the electronic component stack device, and it comprises electronic component on hole on the substrate,, the lower cave,, once electronic component and lead, it is characterized in that: establish a metal level between upper surface of base plate and lower surface; Last hole is through to metal level from upper surface, and forms upward hole bottom; Lower cave is through to metal level and forms the lower cave bottom from lower surface; Last electronic component places the metal level of hole bottom and covers one first adhesive body; Following electronic component places the metal level of lower cave bottom and covers one second adhesive body.
Above-mentioned design, the heat that this upper and lower electronic component of metal level heat loss through conduction is produced because electronic component sinks to substrate, and has reduced distance between itself and the contact, thereby has reached minimizing conductor length and resistance thereof, the effect that the signal transmission is accelerated.
Below by drawings and Examples the utility model is described further again:
Fig. 1,2 existing substrates combine schematic diagram with wafer;
The substrate of Fig. 3 the utility model preferred embodiment combines schematic diagram with electronic component;
The substrate of Fig. 4 the utility model preferred embodiment is stacked in the vertical view of printed circuit board (PCB);
Fig. 5 is the 5-5 cutaway view of Fig. 4.
As shown in Figure 3: the utility model comprises on the substrate 410, an electronic component 421 on hole 414, the lower cave 417,, once electronic component 431 and lead 422,432, and it is characterized in that: substrate 410 upper surfaces 413 and 416 of lower surfaces are established a metal level 412; Last hole 414 is through to metal level 412 from upper surface 413, and forms upward hole 414 bottoms 415; Lower cave 417 is through to metal level 412 and forms lower cave 417 bottoms 418 from lower surface 416; Last electronic component 421 places the metal level 412 of hole 414 bottoms 415 and covers one first adhesive body 425; Following electronic component 431 places the metal level 412 of lower cave 417 bottoms 418 and covers one second adhesive body 435.Substrate 410 comprises an organic material layer 411 and metal level 412, metal level 412 places in the organic material layer 411, organic material layer 411 connects supreme, lower cave 414,417 from upper and lower surperficial 413,416 respectively, and connecting each contact 423,433 of upper and lower electronic component 421,431 respectively with lead 422,432, upper and lower hole 414,417 is established adhesive body 425,435 respectively and is formed sealing.Wherein, the metal level 412 of substrate 410 is provided with and connects the Metal Ball 419 of substrate 410 surfaces for heat loss through conduction.By Fig. 1,2,3 as seen, in the structure of the present utility model, when its substrate 410 is stacked to another substrate 410, using several Metal Ball 419 places between two substrates 410, adhesive body 425,435 on each substrate 410 is not touched mutually, and the little lead of electronic component 421,431 and contact 423,433 spacings shortens, and signal transmits quick.
Shown in Fig. 4,5, wherein, substrate 410 piles up with another substrate 410, and each substrate 410 is put formation one compound crystal blade unit on the printed circuit board (PCB) 400.Wherein, this substrate 410 is used Metal Ball 419 and is fixed on this printed circuit board (PCB) 400.Wherein, substrate 410 is used Metal Ball 419 on this printed circuit board (PCB) 400.
Wherein, on this electronic component 421 and down electronic component 431 be provided with contact 423,433 and use lead 422,432 and connect electronic component 421 and the contact 423,433 of following electronic component 431 and the contact 424,434 of this substrate 410 this on respectively.Two substrates 410 are piled up in the utility model explanation on printed circuit board (PCB) 400, it is as the same still can to pile up other substrate 410 effects again, and advantage is obvious.
Claims (6)
1, electronic component stack device, it comprises electronic component on hole on the substrate,, the lower cave,, once electronic component and lead, it is characterized in that: establish a metal level between upper surface of base plate and lower surface; Last hole is through to metal level from upper surface, and forms upward hole bottom; [cave is through to metal level and forms the lower cave bottom from lower surface in following hole; Last electronic component places the metal level of hole bottom and covers one first adhesive body; Following electronic component places the metal level of lower cave bottom and covers one second adhesive body.
2, electronic component stack device as claimed in claim 1 is characterized in that: wherein, the metal level of substrate is provided with and connects the Metal Ball of substrate surface for heat loss through conduction.
3, as claim 1,2 described electronic component stack devices, it is characterized in that: wherein, substrate and another substrate pile up, and each substrate is put formation one compound crystal blade unit on the printed circuit board (PCB).
4, electronic component stack device as claimed in claim 3 is characterized in that: wherein, this substrate is used Metal Ball and is fixed on this printed circuit board (PCB).
5, electronic component stack device as claimed in claim 3 is characterized in that: wherein, substrate is used Metal Ball on this printed circuit board (PCB).
6, electronic component stack device as claimed in claim 1 is characterized in that: wherein, electronic component and following electronic component are provided with contact and use lead and connect electronic component and the contact of following electronic component and the contact of this substrate on this respectively on this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99200739U CN2370565Y (en) | 1999-01-20 | 1999-01-20 | Stacking device for electronic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99200739U CN2370565Y (en) | 1999-01-20 | 1999-01-20 | Stacking device for electronic element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2370565Y true CN2370565Y (en) | 2000-03-22 |
Family
ID=33996664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99200739U Expired - Fee Related CN2370565Y (en) | 1999-01-20 | 1999-01-20 | Stacking device for electronic element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2370565Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456677A (en) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Packaging structure for ball grid array and manufacturing method for same |
| CN101661929B (en) * | 2008-08-27 | 2012-05-30 | 日月光半导体制造股份有限公司 | Stacked type chip package structure and stack type chip package structure |
-
1999
- 1999-01-20 CN CN99200739U patent/CN2370565Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661929B (en) * | 2008-08-27 | 2012-05-30 | 日月光半导体制造股份有限公司 | Stacked type chip package structure and stack type chip package structure |
| CN102456677A (en) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Packaging structure for ball grid array and manufacturing method for same |
| CN102456677B (en) * | 2010-10-27 | 2013-08-21 | 三星半导体(中国)研究开发有限公司 | Packaging structure for ball grid array and manufacturing method for same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |