CN210535652U - Large-board-level chip packaging module - Google Patents
Large-board-level chip packaging module Download PDFInfo
- Publication number
- CN210535652U CN210535652U CN201921479603.9U CN201921479603U CN210535652U CN 210535652 U CN210535652 U CN 210535652U CN 201921479603 U CN201921479603 U CN 201921479603U CN 210535652 U CN210535652 U CN 210535652U
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- Prior art keywords
- heat dissipation
- layer
- metal
- dielectric material
- material layer
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- 238000004806 packaging method and process Methods 0.000 title claims description 13
- 239000010410 layer Substances 0.000 claims abstract description 74
- 230000017525 heat dissipation Effects 0.000 claims abstract description 58
- 239000003989 dielectric material Substances 0.000 claims abstract description 28
- 229920003023 plastic Polymers 0.000 claims abstract description 13
- 239000012790 adhesive layer Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 12
- 239000008393 encapsulating agent Substances 0.000 claims description 4
- 230000005855 radiation Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- -1 methyl vinyl Chemical group 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a big board-level chip package module, include: a dielectric material layer having a plurality of first through holes disposed thereon; the plurality of chips are arranged on the lower surface of the dielectric material layer, one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port, and each input/output port is respectively opposite to one first through hole; the heat dissipation adhesive layer is arranged on one surface of each chip far away from the dielectric material layer; each heat dissipation structure is connected with one chip through the heat dissipation adhesive layer; and the plastic package layer is arranged on the lower surface of the dielectric material layer and wraps the plurality of chips and the side wall of the heat dissipation structure, and the lower surface of the plastic package layer exposes the lower end face of the heat dissipation structure so as to facilitate heat dissipation.
Description
Technical Field
The utility model relates to a chip package field, concretely relates to big board-level chip package module.
Background
In recent years, a large board level fan-out type packaging technology has been greatly developed, and the large board level fan-out type packaging technology has the characteristics of small surface area, small thickness, high pin number density, lower thermal impedance, excellent electrical performance and the like, can realize low-cost manufacturing of system-in-package and 3D packaging, and can better meet the requirements of a terminal market on product efficiency and volume.
With the development of large board level fan-out type packaging technology, packaging structures with higher chip density and smaller size are emerging continuously. The existing large board level fan-out type packaging structure also has the problem of insufficient heat dissipation capability, and the quality and the performance of a semiconductor chip are seriously influenced. In addition, the existing large board level fan-out type packaging structure also has the problem of low manufacturing efficiency of the heat dissipation structure.
Therefore, the prior art has defects and needs to be improved urgently.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a big board-level chip package module can improve the radiating efficiency.
The utility model provides a big board-level chip packaging module, include:
a dielectric material layer having a plurality of first through holes disposed thereon;
the plurality of chips are arranged on the lower surface of the dielectric material layer, one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port, and each input/output port is respectively opposite to one first through hole;
the heat dissipation adhesive layer is arranged on one surface of each chip far away from the dielectric material layer;
each heat dissipation structure is connected with one chip through the heat dissipation adhesive layer;
the plastic packaging layer is arranged on the lower surface of the dielectric material layer and wraps the plurality of chips and the side walls of the heat dissipation structure, and the lower end surface of the heat dissipation structure is exposed by the lower surface of the plastic packaging layer so as to facilitate heat dissipation;
the metal circuit layer is arranged on the upper surface of the dielectric material layer and is electrically connected with the input/output port through the first through hole;
the ink layer is arranged on the metal circuit layer and the dielectric material layer, and a plurality of second through holes are formed in the ink layer;
a plurality of conductive metal pads disposed in the second vias and electrically connected to the metal line layer.
Big board-level chip package module in, heat radiation structure is metal grid structure, metal grid structure include the metal substrate layer and set up in a plurality of metal protruding structures of the lower surface of metal substrate layer.
In the large board-level chip package module of the present invention, the plurality of metal bumps are spaced apart from each other in a rectangular array.
Big board-level chip package module in, heat radiation structure is metal grid structure, metal grid structure include the metal substrate layer and set up in a plurality of groove structure of the lower surface of metal substrate layer.
In the large board-level chip package module of the present invention, the plurality of groove structures are spaced apart from each other in a rectangular array.
Big board-level chip package module in, heat radiation structure is the heat dissipation sheetmetal, the lower surface of heat dissipation sheetmetal is provided with the heat dissipation line.
Big board-level chip package module in, plastic envelope layer encircles a plurality of chips set up in order to form a plurality of third through-holes, heat radiation structure is located in the third through-hole, just heat radiation structure's lower terminal surface with the lower surface on plastic envelope layer flushes.
The utility model discloses a directly contact heat radiation structure with the chip through the heat dissipation glue film, and the plastic packaging layer directly exposes this heat dissipation glue film empty in the air, can improve the radiating efficiency greatly.
Drawings
Fig. 1 is a schematic structural diagram of a large board-level chip package module according to an embodiment of the present invention.
Fig. 2 is a structural diagram of a heat dissipation structure of a large board-level chip package module according to an embodiment of the present invention.
Fig. 3 is another structural diagram of a heat dissipation structure of a large board-level chip package module according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, fig. 1 is a structural diagram of a large board level chip package module according to some embodiments of the present invention. This big board-level chip package module includes: the semiconductor package comprises a dielectric material layer 10, a plurality of chips 20, a heat dissipation adhesive layer 30, a plurality of heat dissipation structures 40, a plastic package layer 50, a metal circuit layer 60, an ink layer 70 and a plurality of conductive metal pads 80.
Wherein, a plurality of first through holes 11 are arranged on the dielectric material layer 10; the dielectric material layer 10 may be formed of ABF, BCB, PI, etc. The plurality of chips 20 are disposed on the lower surface of the dielectric material layer 10, one surface of each chip 20 contacting the dielectric material layer 10 is provided with an input/output port 21, and each input/output port 21 is directly opposite to one first through hole 11. The heat dissipation adhesive layer 30 is disposed on a surface of each of the chips 20 away from the dielectric material layer 10. The main component in the heat dissipation adhesive layer 30 may be graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, or a material with good heat dissipation property of aluminum oxide. Each heat dissipation structure 40 is connected to one of the chips 20 through the heat dissipation adhesive layer 30. The plastic package layer 50 is disposed on the lower surface of the dielectric material layer 10 and wraps the plurality of chips 20 and the side walls of the heat dissipation structure 40, and the lower surface of the plastic package layer 50 exposes the lower end surface of the heat dissipation structure 40 to facilitate heat dissipation. The metal circuit layer 60 is disposed on the upper surface of the dielectric material layer 10 and electrically connected to the input/output port 21 through the first through hole 11. The ink layer 70 is disposed on the metal circuit layer 60 and the dielectric material layer 10, and a plurality of second through holes 71 are disposed on the ink layer 70. Wherein the plurality of conductive metal pads are disposed in the second via 71 and electrically connected to the metal wiring layer 60.
Referring to fig. 2, in some embodiments, the heat dissipation structure 40 is a metal grid structure, and the metal grid structure includes a metal substrate layer 41 and a plurality of metal bump structures 42 disposed on a lower surface of the metal substrate layer 41. The plurality of metal bump structures 42 are spaced apart in a rectangular array.
Referring to fig. 3, in some embodiments, the plurality of groove structures are arranged in a rectangular array at intervals. The heat dissipation structure 40 is a metal grid structure including a metal substrate layer 41 and a plurality of groove structures 43 disposed on a lower surface of the metal substrate layer. A plurality of groove structures 43 are spaced apart in a rectangular array.
In some embodiments, the heat dissipation structure 40 is a heat dissipation metal sheet, and the lower surface of the heat dissipation metal sheet is provided with heat dissipation lines. The heat dissipation lines can increase the heat dissipation area to improve the heat dissipation efficiency.
In some embodiments, the encapsulant layer 50 is disposed around the plurality of chips 20 to form a plurality of third through holes, the heat dissipation structure 40 is located in the third through holes, and a lower end surface of the heat dissipation structure 40 is flush with a lower surface of the encapsulant layer 50.
The utility model discloses a directly contact heat radiation structure with the chip through the heat dissipation glue film, and the plastic packaging layer directly exposes this heat dissipation glue film empty in the air, can improve the radiating efficiency greatly.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that the scope of the present invention shall be determined by the scope of the appended claims.
Claims (7)
1. A large board level chip package module, comprising:
a dielectric material layer having a plurality of first through holes disposed thereon;
the plurality of chips are arranged on the lower surface of the dielectric material layer, one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port, and each input/output port is respectively opposite to one first through hole;
the heat dissipation adhesive layer is arranged on one surface of each chip far away from the dielectric material layer;
each heat dissipation structure is connected with one chip through the heat dissipation adhesive layer;
the plastic packaging layer is arranged on the lower surface of the dielectric material layer and wraps the plurality of chips and the side walls of the heat dissipation structure, and the lower end surface of the heat dissipation structure is exposed by the lower surface of the plastic packaging layer so as to facilitate heat dissipation;
the metal circuit layer is arranged on the upper surface of the dielectric material layer and is electrically connected with the input/output port through the first through hole;
the ink layer is arranged on the metal circuit layer and the dielectric material layer, and a plurality of second through holes are formed in the ink layer;
a plurality of conductive metal pads disposed in the second vias and electrically connected to the metal line layer.
2. The large board-scale chip package module according to claim 1, wherein the heat dissipation structure is a metal grid structure, and the metal grid structure includes a metal substrate layer and a plurality of metal bump structures disposed on a lower surface of the metal substrate layer.
3. The large board scale chip package module of claim 2, wherein the plurality of metal bump structures are spaced apart in a rectangular array.
4. The large board-scale chip package module according to claim 1, wherein the heat dissipation structure is a metal grid structure, and the metal grid structure includes a metal substrate layer and a plurality of groove structures disposed on a lower surface of the metal substrate layer.
5. The large board scale chip package module assembly according to claim 4, wherein the plurality of groove structures are spaced apart in a rectangular array.
6. The large board-scale chip package module according to claim 1, wherein the heat dissipation structure is a heat dissipation metal sheet, and a lower surface of the heat dissipation metal sheet is provided with heat dissipation lines.
7. The large board scale chip package module according to claim 1, wherein the encapsulant layer is disposed around the plurality of chips to form a plurality of third through holes, the heat dissipation structure is located in the third through holes, and a lower end surface of the heat dissipation structure is flush with a lower surface of the encapsulant layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921479603.9U CN210535652U (en) | 2019-09-06 | 2019-09-06 | Large-board-level chip packaging module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921479603.9U CN210535652U (en) | 2019-09-06 | 2019-09-06 | Large-board-level chip packaging module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210535652U true CN210535652U (en) | 2020-05-15 |
Family
ID=70604572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921479603.9U Active CN210535652U (en) | 2019-09-06 | 2019-09-06 | Large-board-level chip packaging module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210535652U (en) |
-
2019
- 2019-09-06 CN CN201921479603.9U patent/CN210535652U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Large board level chip package module Effective date of registration: 20201224 Granted publication date: 20200515 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong fozhixin microelectronics technology research Co.,Ltd.|Guangdong Xinhua Microelectronics Technology Co.,Ltd. Registration number: Y2020980009995 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230425 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: 528225 room a208-1, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20200515 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong Xinhua Microelectronics Technology Co.,Ltd.|Guangdong fozhixin microelectronics technology research Co.,Ltd. Registration number: Y2020980009995 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |