CN211295100U - Large board level fan-out type chip packaging structure - Google Patents
Large board level fan-out type chip packaging structure Download PDFInfo
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- CN211295100U CN211295100U CN201921479612.8U CN201921479612U CN211295100U CN 211295100 U CN211295100 U CN 211295100U CN 201921479612 U CN201921479612 U CN 201921479612U CN 211295100 U CN211295100 U CN 211295100U
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- layer
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- heat dissipation
- material layer
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- 238000004806 packaging method and process Methods 0.000 title abstract description 13
- 230000017525 heat dissipation Effects 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 239000003989 dielectric material Substances 0.000 claims abstract description 25
- 229920003023 plastic Polymers 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 87
- 239000008393 encapsulating agent Substances 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 2
- -1 methyl vinyl Chemical group 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model provides a big board-level fan-out type chip package structure, include: a dielectric material layer having a plurality of first through holes disposed thereon; the plurality of chips are arranged on the lower surface of the dielectric material layer, and one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port; the plastic packaging layer is arranged on the lower surface of the dielectric material layer and wraps the side walls of the plurality of chips, and the lower surface of the plastic packaging layer exposes the lower surfaces of the chips; a heat dissipation layer disposed on the lower surface of the plastic package layer and the lower surface of the chip; the metal circuit layer is arranged on the upper surface of the dielectric material layer and is electrically connected with the input/output port through a first through hole; the first ink layer is arranged on the metal circuit layer and the dielectric material layer, and a plurality of second through holes are formed in the ink layer; a plurality of conductive metal pads disposed in the second vias and electrically connected to the metal line layer.
Description
Technical Field
The utility model relates to a chip package field, concretely relates to big board-level fan-out type chip package structure.
Background
In recent years, a large board level fan-out type packaging technology has been greatly developed, and the large board level fan-out type packaging technology has the characteristics of small surface area, small thickness, high pin number density, lower thermal impedance, excellent electrical performance and the like, can realize low-cost manufacturing of system-in-package and 3D packaging, and can better meet the requirements of a terminal market on product efficiency and volume.
With the development of large board level fan-out type packaging technology, packaging structures with higher chip density and smaller size are emerging continuously. The existing large board level fan-out type packaging structure also has the problem of insufficient heat dissipation capability, and the quality and the performance of a semiconductor chip are seriously influenced. In addition, the existing large board level fan-out type packaging structure also has the problem of low manufacturing efficiency of the heat dissipation structure.
Therefore, the prior art has defects and needs to be improved urgently.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a big board-level fan-out type chip packaging structure can improve the radiating efficiency.
The utility model provides a big board-level fan-out type chip package structure, include:
a dielectric material layer having a plurality of first through holes disposed thereon;
the plurality of chips are arranged on the lower surface of the dielectric material layer, one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port, and each input/output port is respectively opposite to one first through hole;
a plastic package layer disposed on a lower surface of the dielectric material layer and enclosing the sidewalls of the plurality of chips, the lower surface of the plastic package layer exposing the lower surfaces of the chips;
a heat dissipation layer disposed on a lower surface of the plastic encapsulant layer and a lower surface of the chip;
the metal circuit layer is arranged on the upper surface of the dielectric material layer and is electrically connected with the input/output port through the first through hole;
the first ink layer is arranged on the metal circuit layer and the dielectric material layer, and a plurality of second through holes are formed in the ink layer;
a plurality of conductive metal pads disposed in the second vias and electrically connected to the metal line layer.
Big board-level fan-out type chip package structure in, the heat dissipation layer is the metal heat dissipation layer, the lower surface on heat dissipation layer is provided with second printing ink layer.
In the large board level fan-out chip package structure of the present invention, the heat dissipation layer is a metal sheet.
Big board-level fan-out type chip package structure in, the heat dissipation layer is the heat dissipation glue film, the lower surface on heat dissipation layer is provided with second printing ink layer.
Big board-level fan-out chip package structure in, the lower surface on plastic packaging body layer with the lower surface of chip flushes.
In the large board-level fan-out chip package structure of the present invention, the plurality of chips are arranged in a rectangular array at intervals.
The utility model discloses a do the plastic packaging body layer thin in order to expose the lower surface of chip for the lower surface direct contact of heat dissipation layer and this chip, thereby can improve the radiating efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a large board-level fan-out chip package structure according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
Referring to fig. 1, fig. 1 is a structural diagram of a large board-level fan-out chip package structure according to some embodiments of the present invention. A large board level fan-out chip package structure comprising: the semiconductor package comprises a dielectric material layer 10, a plurality of chips 20, a plastic encapsulant layer 30, a heat dissipation layer 40, a metal circuit layer 50, a first ink layer 60 and a plurality of conductive metal pads 70.
Wherein, a plurality of first through holes 11 are arranged on the dielectric material layer 10; the plurality of chips 20 are arranged on the lower surface of the dielectric material layer 10, one surface of each chip 20, which is in contact with the dielectric material layer 10, is provided with an input/output port 21, and each input/output port 21 is respectively opposite to one first through hole 11; the plastic package layer 30 is disposed on the lower surface of the dielectric material layer 10 and wraps the side walls of the plurality of chips 20, and the lower surface of the plastic package layer 30 exposes the lower surfaces of the chips 20; the heat dissipation layer 40 is disposed on the lower surface of the plastic package layer 30 and the lower surface of the chip 20; the metal circuit layer 50 is disposed on the upper surface of the dielectric material layer 10 and electrically connected to the input/output port 21 through the first through hole 11; the first ink layer 60 is disposed on the metal circuit layer 50 and the dielectric material layer 10, and a plurality of second through holes 61 are disposed on the first ink layer 60; a plurality of conductive metal pads 70 disposed at the second via holes 61 and electrically connected to the metal wiring layer 50. The plurality of chips 20 are arranged at intervals in a rectangular array.
Specifically, in some embodiments, the heat dissipation layer 40 may be a metal heat dissipation layer 40, and the lower surface of the heat dissipation layer 40 is provided with a second ink layer 80. For example, the metal heat dissipation layer may be a metal layer formed by physical vapor deposition. Alternatively, the heat dissipation layer 40 is a metal sheet, such as a metal aluminum sheet.
When the plastic package layer 30 is manufactured, the plastic package layer 30 completely wraps the chip when packaging is started. Then, the lower surface of the plastic package layer 30 is thinned to expose the lower surface of the chip.
In some embodiments, the heat dissipation layer 40 is a heat dissipation adhesive layer, and the second ink layer 80 is disposed on the lower surface of the heat dissipation layer 40. The main component in the heat dissipation glue layer can be graphene, silica gel, silicone grease, methyl vinyl polysiloxane mixture, methyl hydrogen polysiloxane mixture, aluminum oxide and other materials with good heat dissipation performance.
Wherein, in some embodiments, a lower surface of the plastic encapsulant layer 30 is flush with a lower surface of the chip 20.
Wherein, the utility model discloses in the big board level fan-out type chip package structure that provides can form single function chip package structure through the cutting.
The utility model discloses a do the plastic packaging body layer thin in order to expose the lower surface of chip for the lower surface direct contact of heat dissipation layer and this chip, thereby can improve the radiating efficiency.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so that the scope of the present invention shall be determined by the scope of the appended claims.
Claims (6)
1. A large board level fan-out chip package structure, comprising:
a dielectric material layer having a plurality of first through holes disposed thereon;
the plurality of chips are arranged on the lower surface of the dielectric material layer, one surface of each chip, which is in contact with the dielectric material layer, is provided with an input/output port, and each input/output port is respectively opposite to one first through hole;
a plastic package layer disposed on a lower surface of the dielectric material layer and enclosing the sidewalls of the plurality of chips, the lower surface of the plastic package layer exposing the lower surfaces of the chips;
a heat dissipation layer disposed on a lower surface of the plastic encapsulant layer and a lower surface of the chip;
the metal circuit layer is arranged on the upper surface of the dielectric material layer and is electrically connected with the input/output port through the first through hole;
the first ink layer is arranged on the metal circuit layer and the dielectric material layer, and a plurality of second through holes are formed in the ink layer;
a plurality of conductive metal pads disposed in the second vias and electrically connected to the metal line layer.
2. The package structure of claim 1, wherein the heat dissipation layer is a metal heat dissipation layer, and a second ink layer is disposed on a lower surface of the heat dissipation layer.
3. The large board level fan-out die package structure of claim 2, wherein the heat spreading layer is a metal sheet.
4. The package structure of claim 1, wherein the heat dissipation layer is a heat dissipation adhesive layer, and a second ink layer is disposed on a lower surface of the heat dissipation layer.
5. The large board level fan-out die package structure of claim 1, wherein a lower surface of the encapsulant layer is flush with a lower surface of the die.
6. The package structure of claim 1, wherein the plurality of dies are spaced in a rectangular array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921479612.8U CN211295100U (en) | 2019-09-06 | 2019-09-06 | Large board level fan-out type chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921479612.8U CN211295100U (en) | 2019-09-06 | 2019-09-06 | Large board level fan-out type chip packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN211295100U true CN211295100U (en) | 2020-08-18 |
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| CN201921479612.8U Active CN211295100U (en) | 2019-09-06 | 2019-09-06 | Large board level fan-out type chip packaging structure |
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| CN (1) | CN211295100U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649286A (en) * | 2022-05-19 | 2022-06-21 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
-
2019
- 2019-09-06 CN CN201921479612.8U patent/CN211295100U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649286A (en) * | 2022-05-19 | 2022-06-21 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure and fan-out type packaging method |
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Large board level fan out chip packaging structure Effective date of registration: 20201224 Granted publication date: 20200818 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong fozhixin microelectronics technology research Co.,Ltd.|Guangdong Xinhua Microelectronics Technology Co.,Ltd. Registration number: Y2020980009995 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230427 Address after: Room A107, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province, 528225 Patentee after: Guangdong fozhixin microelectronics technology research Co.,Ltd. Address before: 528225 room a208-1, scientific research building, block a, neifo high tech think tank center, Nanhai Software Science Park, Shishan town, Nanhai District, Foshan City, Guangdong Province Patentee before: Guangdong fozhixin microelectronics technology research Co.,Ltd. Patentee before: Guangdong Xinhua Microelectronics Technology Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20200818 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: Guangdong Xinhua Microelectronics Technology Co.,Ltd.|Guangdong fozhixin microelectronics technology research Co.,Ltd. Registration number: Y2020980009995 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right |